2, 4, and 8-Channel Low Capacitance ESD Protection Arrays
Features
•2, 4, and 8 channels of ESD protection
•Provides
ESD protection to IEC61000-4-2
- 8kV contact discharge
- 15kV air discharge
•Low loading capacitance of 2.0pF max.
•Low clamping voltage
•Channel I/O to I/O capacitance 1.5pF typical
•Zener diode protects supply rail and eliminates the
need for external by-pass capacitors
•Each I/O pin can withstand over 1000 ESD strikes
•Available in SOT, and MSOP packages
•Lead-free version available
Applications
•DVI ports, HDMI ports in notebooks, set top boxes,
digital TVs, LCD displays
•Serial ATA ports in desktop PCs and hard disk
drives
•PCI Express ports
•General purpose high-speed data line ESD
protection
Product Description
The CM1293 family of diode arrays has been designed
to provide ESD protection for electronic components or
sub-systems requiring minimal capacitive loading.
These devices are ideal for protecting systems with
high data and clock rates or for circuits requiring low
capacitive loading. Each ESD channel consists of a
pair of diodes in series which steer the positive or negative ESD current pulse to either the positive (V
negative (V
between V
protects the V
) supply rail. A Zener diode is embedded
N
and VN, offering two advantages. First, it
P
rail against ESD strikes, and second,
CC
it eliminates the need for a bypass capacitor that would
otherwise be needed for absorbing positive ESD
strikes to ground. The CM1293 will protect against
ESD pulses up to (±15kV air, ±8kV contact discharge)
per the IEC 61000-4-2 Level 4 standard.
This device is particularly well-suited for protecting systems using high-speed ports such as USB2.0,
IEEE1394 (Firewire
®, iLink™), Serial ATA, DVI, HDMI
and corresponding ports in removable storage, digital
camcorders, DVD-RW drives and other applications
where extremely low loading capacitance with ESD
protection are required in a small package footprint.
P
) or
The CM1293 family of devices is available with
optional lead-free finishing.
Peak Discharge Voltage at any
channel input, in system
a) Contact discharge per
Notes 2, 4 & 5; T
=25°C
A
±8
kV
IEC 61000-4-2 standard
b) Human Body Model,
MIL-STD-883, Method
Notes 2, 3 & 5; T
=25°C
A
±15
kV
3015
R
V
DYN
Channel Clamp Voltage
CL
Positive Transients
Negative Transients
Dynamic Resistance
Positive Transients
Negative Transients
At 8kV ESD HBM; TA=25°C; Notes 2 & 3
TA=25°C; Notes 5 & 6
+9.0
-9.0
1.2
0.6
V
V
Ω
Ω
Note 1: All parameters specified at TA = -40°C to +85°C unless otherwise noted.
Note 2: These parameters guaranteed by design and characterization.
Note 3: Human Body Model per MIL-STD-883, Method 3015, C
Note 4: Standard IEC 61000-4-2 with C
Note 5: These measurements performed with no external capacitor on V
Note 6: Measured under pulsed conditions, pulse width = 0.7mS, maximum current = 1.5A.
01/26/06490 N. McCarthy Blvd., Milpitas, CA 95035-5112● Tel: 408.263.3214●Fax: 408.263.7846●www.cmd.com5
Page 6
Application Information
Design Considerations
CM1293
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to Figure 3, which illustrates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to
the power supply is represented by L
age V
where I
on the line being protected is:
CL
VCL = Fwd voltage drop of D1 + V
+ L
x d(I
2
is the ESD current pulse, and V
ESD
ESD
) / dt
and L2. The volt-
1
+ L1 x d(I
SUPPLY
) / dt
ESD
SUPPLY
is
the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(I
ΔI
/Δt, or 30/(1x10-9). So just 10nH of series induc-
ESD
tance (L
ment in V
and L2 combined) will lead to a 300V incre-
1
!
CL
)/dt can be approximated by
ESD
Similarly for negative ESD pulses, parasitic series
inductance from the V
pin to the ground rail will lead
N
to drastically increased negative voltage on the line
being protected.
The CM1293 has an integrated Zener diode between
V
and VN. This greatly reduces the effect of supply rail
P
inductance L
on VCL by clamping VP at the break-
2
down voltage of the Zener diode. However, for the lowest possible V
, especially when VP is biased at a
CL
voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22μF ceramic chip
capacitor be connected between VP and the ground
plane.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the V
pin of the Protection Array as possible, with
P
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also California Micro Devices Application Note
AP209, “Design Considerations for ESD Protection”, in
the Applications section at www.calmicro.com.
V
P
0.22μF
V
N
D
1
D
2
ONE
CHANNEL
OF
CM1213
2
PATH OF ESD CURRENT PULSE I
L
1
CHANNEL
INPUT
25A
0A
POSITIVE SUPPLY RAIL
LINE BEING
PROTECTED
V
CL
GROUND RAIL
ESD
CHASSIS GROUND
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
V
CC
L
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground