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CLC5956
12-bit, 65 MSPS Broadband Monolithic A/D Converter
CLC5956 12-bit, 65 MSPS Broadband Monolithic A/D Converter
June 1999
General Description
The CLC5956 is a monolithic 12-bit, 65 MSPS
analog-to-digital converter subsystem. The device has been
optimized for use in cellularbase stations and other applications where high resolution, high sampling rate, wide dynamic range, low power dissipation, and compact size are
required. The CLC5956 features differential analog inputs,
low jitter differential PECL clock inputs, a low distortion
track-and-hold with DC to 300 MHz input bandwidth, a bandgap voltage reference, TTL compatible CMOS output logic,
and a proprietary 12-bit multi-stage quantizer. The CLC5956
is fabricated on the ABIC-IV 0.8 micron BiCMOS process.
The part features a 73 dB spurious free dynamic range
(SFDR) and 67 dB SNR. The wideband track-and-hold allows sampling of IF signals to greater than 250 MHz. The
part produces two-tone, dithered, spurious-free dynamic
range of 83 dBFS at 75 MHz input frequency.The differential
analog input provides excellent common-mode rejection,
while the differential PECL clock inputs permit the use of balanced transmission to minimize jitter in distributed systems.
The 48-pin TSSOP package provides an extremely small
footprint for applications where space is a critical consideration. The CLC5956 operates from a single +5V power supply over the industrial temperature range of −40˚C to +85˚C.
National thoroughly tests each part to verify full compliance
with the guaranteed specifications.
Block Diagram
Features
n Wide dynamic range
n IF sampling capability
n 300 MHz input bandwidth
n Small 48-pin TSSOP
n Single +5V supply
n Low cost
Key Specifications
n Sample Rate 65 MSPS
n SFDR 73 dBc
n SFDR with dither 85 dBFS
n SNR 67 dB
n Low power consumption 615 mW
Applications
n Cellular base-stations
n Digital communications
n Infrared/CCD imaging
n IF sampling
n Electro-optics
n Instrumentation
n Medical imaging
n High definition video
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© 1999 National Semiconductor Corporation DS015011 www.national.com
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Pin Configuration Ordering Information
CLC5956IMTD 48-Pin TSSOP
CLC5956IMTDX 48-Pin TSSOP (Taped Reel)
CLC5956PCASM Evaluation Board
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Pin Descriptions
Pin
Name
A
IN
A
IN
ENCODE
ENCODE
Pin
No.
13, 14
9, 10
Differential input with a common mode voltage of +2.4V. The ADC
full scale input is 1.024 VPPon each of the complimentary input
signals.
Differential clock where ENCODE initiates a new data conversion
cycle on each rising edge. Logic for these inputs are a 50%duty
cycle differential PECL signal.
Internal common mode voltage reference. Nominally +2.4V. Can
VCM 21
be used for the input common mode voltage. This voltage is
derived from an internal bandgap reference.
D0–D11
GND
+AV
CC
+DV
CC
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30–34,
39–45
1–4, 8, 11, 12, 15, 19,
20, 23–26, 35, 36, 47, 48
5–7, 16–18, 22
37, 38, 46
Digital data outputs are CMOS and TTL compatible. D0 is the LSB
and D11 is the MSB. MSB is inverted. Output coding is two’s
complement.
Circuit ground.
+5V power supply for the analog section. Bypass to ground with a
0.1 µF capacitor.
+5V power supply for the digital section. Bypass to ground with a
0.1 µF capacitor.
Description
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage (V
Differential Voltage between any Two
Grounds
Analog Input Voltage Range GND to V
Digital Input Voltage Range −0.5V to +V
Output Short Circuit Duration (one-pin
to ground) Infinite
) −0.5V to +6V
CC
<
200 mV
Recommended Operating
Conditions
Positive Supply Voltage (VCC) +5V±5
Analog Input Voltage Range 2.048 V
Operating Temperature Range −40˚C to +85˚C
CC
Package Thermal Resistance (Note 6)
CC
Package θ
JA
48-Pin TSSOP 56˚C/W 16˚C/W
diff.
PP
θ
JC
Junction Temperature (Note 6) 175˚C
Storage Temperature Range −65˚C to +150˚C
Lead Solder Duration (+300˚C) 10 sec.
Reliability Information
Transistor Count 5000
Converter Electrical Characteristics
=
The following specifications apply for AV
limits apply for T
=
=
T
min
−40˚C to T
A
CC
max
=
DV
+5V, 52 MSPS, 50%Encode Clock Duty Cycle, C
CC
=
+85˚C, all other limits T
=
25˚C (Notes 2, 3, 4).
A
Symbol Parameter Conditions Min Typ Max Units
DYNAMIC PERFORMANCE
BW Large-Signal Bandwidth V
Overvoltage Recovery Time V
t
DS
t
AJ
Effective Aperture Delay −0.21 ns
Aperture Jitter 0.4 ps(rms)
=FS−3dB 300 MHz
IN
=
1.5 FS (0.01%)12ns
IN
NOISE AND DISTORTION
=
f
20 MHz, FS −1 dB 63 66 dBFS
IN
=
f
5 MHz, FS −3 dB 67 dBFS
IN
=
f
SNR
SFDR
IMD
Signal-to-Noise Ratio (without
harmonics)
Spurious-Free Dynamic Range
Spurious-Free Dynamic Range
(dithered)
Intermodulation Distortion
Intermodulation Distortion
(dithered)
25 MHz, FS −3 dB 66 dBFS
IN
=
f
75 MHz, FS −3 dB 64 dBFS
IN
=
f
150 MHz, FS −3 dB 62 dBFS
IN
=
f
250 MHz, FS −3 dB 59 dBFS
IN
=
f
20 MHz, FS −1 dB 66 70 dBc
IN
=
f
5 MHz, FS −3 dB 73 dBc
IN
=
f
25 MHz, FS −3 dB 70 dBc
IN
=
f
75 MHz, FS −3 dB 68 dBc
IN
=
f
150 MHz, FS −3 dB 58 dBc
IN
=
f
250 MHz, FS −3 dB 55 dBc
IN
=
f
19 MHz, FS −6 dB 85 dBFS
IN
=
149.84 MHz, f
f
1
MHz, FS −10 dB
=
249.86 MHz, f
f
1
MHz, FS −10 dB
=
74 MHz, f
f
1
−12 dB
2
2
=
75 MHz, FS
2
=
=
149.7
249.69
DC ACCURACY AND PERFORMANCE
DNL Differential Non-Linearity DC; Full Scale 0.65 LSB
INL Integral Non-Linearity DC; Full Scale 1.7 LSB
Bipolar Offset Error −1 mV
Bipolar Gain Error −0.1
ANALOG INPUTS
V
IN
RIN(SE)
Analog Diff Input Voltage Range 2.048 V
Analog Input Resistance
(Single-Ended)
=
7 pF. Boldface
L
68 dBFS
58 dBFS
83 dBFS
%
500 Ω
PP
%
FS
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Converter Electrical Characteristics (Continued)
=
The following specifications apply for AV
limits apply for T
=
=
T
min
−40˚C to T
A
CC
max
=
DV
+5V, 52 MSPS, 50%Encode Clock Duty Cycle, C
CC
=
+85˚C, all other limits T
=
25˚C (Notes 2, 3, 4).
A
Symbol Parameter Conditions Min Typ Max Units
ANALOG INPUTS
R
IN
(Diff)
C
IN
Analog Input Resistance
(Differential)
Analog Input Capacitance 2 pF
ENCODE INPUTS
V
IL
V
IH
I
IL
I
IH
Logic Input Low Voltage 3.0 3.5 V
Logic Input High Voltage 4.0 4.5 V
Logic Input Low Current 1 5 µA
Logic Input High Current 16 25 µA
DIGITAL OUTPUTS
V
OL
V
OH
Logic Output Low Voltage 0.4 V
Logic Output High Voltage 2.4 V
TIMING
F
max Maximum Conversion Rate 65 MSPS
s
F
min Minimum Conversion Rate 10 MSPS
s
PWH Pulse Width High 7.7 ns
PWL Pulse Width Low 7.7 ns
Pipeline Delay (Note 5) 3.0 CLK Cy
Output Propagation Delay 1.6 ns
POWER REQUIREMENTS
I
CC
Total Operating Supply Current 65 MSPS 123 150 mA
Power Consumption 65 MSPS 615 750 mW
Power Supply Rejection Ratio 64 dB
Note 1: “Absolute Maximum Ratings” are limiting values, to be applied individually,andbeyondwhichtheserviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability.
Note 2: Limits are 100%tested at 25˚C.
Note 3: Typical characteristics are the mean values of the distributions of deliverable converters at 25˚C.
Note 4: Outgoing quality levels are determined from tested parameters.
Note 5: Max pipeline delay rating is based upon product characterization and simulation.
Note 6: The absolute maximum junction (T
junction-to-ambient thermal resistance (θ
TSSOP, θ
under normal operation willtypicallybeabout625mW(615mWquiescentpower+10mW due to 1 TTL load on each digital output).Thevaluesofabsolutemaximum
power dissipation will only be reached when the CLC5956 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply
voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
is 56˚C/W, so PDmax=2.68W at 25˚C and 1.6W at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this device
JA
max) temperature for this device is 175˚C. The maximum allowable power dissipation is dictated by TJmax, the
J
), and the ambient temperature (TA), and can be calculated using the formula PDmax=(TJmax – TA)/θJA. For the 48-pin
JA
=
7 pF. Boldface
L
1000 Ω
Typical Performance Characteristics (AV
SNR and SFDR vs Input Frequency
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SNR and SFDR vs Input Frequency
=
=
DV
CC
+5V)
CC
SNR and SFDR vs Input Frequency
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Typical Performance Characteristics (AV
=
=
DV
CC
+5V) (Continued)
CC
SNR and SFDR vs Sample Rate
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Differential Non-Linearity
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SNR and SFDR vs Input Amplitude
Single Tone Output Spectrum
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Integral Non-Linearity
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SNR and SFDR vs Input Amplitude
Single Tone Output Spectrum (with
Dither)
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SNR and SFDR vs Input Amplitude
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SNR and SFDR vs Input Amplitude
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Two Tone Output Spectrum (with
Dither)
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Two Tone Output Spectrum
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Two Tone Output Spectrum
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Typical Performance Characteristics (AV
=
=
DV
CC
+5V) (Continued)
CC
Spectral Response
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Timing Diagram
Full Scale Analog Input Levels
SINAD vs Input Level
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Single IF Down Converter
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Evaluation Board
Evaluation Board Schematic
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Evaluation Board (Continued)
CLC730079 Layer 1
CLC730079 Layer 3
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CLC730079 Layer 2
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CLC730079 Layer 4
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Evaluation Printed Circuit Board
The Evaluation board for the CLC5956 allows for easy test
and evaluation of the product. The part may be ordered with
all components loaded and tested. The order number is the
CLC5956PCASM. The user supplies an analog input signal,
encode signal and power to the board and is able to take
latched 12-bit digital data out of the board.
ENCODE Input (ENC)
The ENCODE input is an SMA connector with a 50Ω termination. The signal is converted from single to differential and
its frequency is divided by four to produce a low jitter, symmetrical encode signal for the CLC5956. The user should
provide a sinusoidal or square wave signal of 10 dBm to
16 dBm amplitude at four times the converter’s desired
sample rate. It is recommended that the source be low jitter
to maintain best performance. The transformer will pass signals in the 40 MHz to 260 MHz range which allows sample
rates of 10 Msps to 65 Msps.
Clock Option
The CLC5956 board is configured for a 4x clock input to provide optimal performance with some (i.e., HP8662) synthesizers. The HP8662 output has lower jitter above 160 MHz.
Using a 208 MHz clock to sample at 52 MHz minimizes the
effect of the synthesizer on the measurement.
To use a 1x clock, replace the divide-by-4 sine-to-PECL converter (U4, MC10EL33D) with an MC10EL16D. The
MC10EL16D sine-to-PECL converter does not divide the
clock. This approach would be suitable for use with a synthesizer that has optimal jitter performance at 52 MHz (i.e.,
HP8643 or HP8644).
The best ADC performance is obtained with a low-jitter crystal oscillator module installed at Y1 on the evaluation board.
U4 should be replaced with an MC10EL16D. Placing the
clock source on the evaluation board reduces ground loop
issues and thus improves performance.
Analog Input (AIN)
The analog input is an SMA connector with a 50Ω termination. The signal is converted from single to differential by a
transformer with a 5 MHz to 260 MHz bandwidth and approximately one dB loss. Full scale is approximately 11 dBm
or 2.2 V
input signal be low jitter, low noise and low distortion to allow
for proper test and evaluation of the CLC5956.
. It is recommended that the source for the analog
PP
Supply Voltages (J1 pins 31 A&B
and 32 A&B)
The CLC5956PCASM is powered from a single 5V supply
connected from the referenced pins on the Eurocard connector.The recommended supplies are low noise linear supplies.
Digital Outputs (J1 pins 7A (MSB,
D11), 8B (D10) through 18B (LSB)
and 20B (Data Ready)
The digital outputs are provided on the Eurocard connector.
The outputs are buffered by 5V CMOS latches with 50Ω series output resistors. The rising edge of Data Ready may be
used to clock the output data into data collection cards or
logic analyzers. The board has a location for the HP
01650-63203 termination adapter for HP 16500 logic analyzers to simplify connection to the analyzer.
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead TSSOP (Millimeters Only)
Order Number CLC5956IMTD
NS Package Number MTD48
CLC5956 12-bit, 65 MSPS Broadband Monolithic A/D Converter
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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