Datasheet CLC5633IMX, CLC5633IM Datasheet (NSC)

Features

■

130mA output current

■

0.03%, 0.06° differential gain, phase

■

3.0mA/ch supply current

■

130MHz bandwidth (Av= +2)

■

-92/-96dBc HD2/HD3 (1MHz)

■

20ns settling to 0.05%

■

410V/µs slew rate

■

Stable for capacitive loads up to 1000pf

■

Single 5V to ±5V supplies

Applications

■

Video line driver

■

Coaxial cable driver

■

Twisted pair driver

■

Transformer/coil driver

■

High capacitive load driver

■

Portable/battery-powered applications

■

A/D driver

Typical Application

Single Supply Cable Driver

General Description

The CLC5633 is a triple, low-cost, high-speed (130MHz) buffer
which features user-programmable gains of +2, +1, and -1V/V.
The CLC5633 also has a new output stage that delivers high
output drive current (130mA), but consumes minimal quiescent
supply current (3.0mA/ch) from a single 5V supply. Its current
feedback architecture, fabricated in an advanced complementary
bipolar process, maintains consistent performance over a wide
range of gains and signal levels , and has a linear-phase response
up to one half of the -3dB frequency.

The CLC5633 offers 0.1dB gain flatness to 20MHz and differen­tial gain and phase errors of 0.03% and 0.06°. These features are
ideal for professional and consumer video applications.

The CLC5633 offers superior dynamic performance with a
130MHz small-signal bandwidth, 410V/µs slew rate and 5.0ns
rise/fall times (2V

step

). The combination of low quiescent power,
high output current drive, and high-speed performance make
the CLC5633 well suited for many battery-powered personal
communication/computing systems.

The ability to drive low-impedance, highly capacitive loads,
with minimum distortion makes the CLC5633 ideal for cable
applications. The CLC5633 will drive a 100Ω load with only

-73/-92dBc second/third harmonic distortion (Av= +2, V

out

=
2Vpp, f = 1MHz). With a 25Ω load, and the same conditions, it
produces only -75/-75dBc second/third harmonic distortion. It is
also optimized for driving high currents into single-ended
transformers and coils.

When driving the input of high-resolution A/D converters, the
CLC5633 provides excellent -92/-96dBc second/third harmonic
distortion (Av= +2, V

out

= 2Vpp, f = 1MHz, RL= 1kΩ) and fast

settling time.

CLC5633
Triple, High Output, Programmable Gain Buffer

N

June 1999

CLC5633

Triple, High Output, Programmable Gain Buffer

© 1999 National Semiconductor Corporation http://www.national.com

Printed in the U.S.A.

Pinout

DIP & SOIC

Maximum Output Voltage vs. R

10

9

)

8

pp

7
6
5
4
3

Output Voltage (V

2
1

10

VCC = ±5V

Vs = +5V

100

RL (Ω)

L

1000

+5V

6.8µF

+

+5V

0.1µF

V

in

5kΩ

5kΩ

0.1µF

0.1µF

1 14
2 13
3 12
4 11
5 10
6 9
7 8

1kΩ

+

-

1kΩ

-

1kΩ

-

+

CLC5633

1kΩ

+

1kΩ
1kΩ

Note: Channel 2 and 3 not shown.

10m of 75Ω

Coaxial Cable

75Ω

0.1µF

75Ω

NC OUT21 14
NC -IN2
NC +IN2

+V

V

o

+IN1 +IN3

-IN1 -IN3

OUT1 OUT3

+

1kΩ

1kΩ

-

-

-

+

2 13
3 12
4 11

s

5 10
6 9
7 8

1kΩ

+

1kΩ
1kΩ

1kΩ

-V

s

http://www.national.com 2

PARAMETERS CONDITIONS TYP MIN/MAX RATINGS UNITS NOTES
Ambient Temperature CLC5633IN/IM +25°C +25°C 0 to 70°C -40 to 85°C

FREQUENCY DOMAIN RESPONSE

-3dB bandwidth V

o

= 0.5V

pp

100 80 70 70 MHz

V

o

= 2.0V

pp

97 79 74 72 MHz

-

0.1dB bandwidth Vo= 0.5V

pp

20 17 17 13 MHz

gain peaking <200MHz, V

o

= 0.5V

pp

0 0.5 1.0 1.0 dB

gain rolloff <30MHz, V

o

= 0.5V

pp

0.2 0.5 0.6 0.6 dB

linear phase deviation <30MHz, V

o

= 0.5V

pp

0.15 0.3 0.4 0.4 deg

differential gain NTSC, R

L

= 150Ω to -1V 0.04 – – – %

differential phase NTSC, R

L

= 150Ω to -1V 0.1 – – – deg

TIME DOMAIN RESPONSE

rise and fall time 2V step 4.8 6.4 6.8 7.3 ns
settling time to 0.05% 1V step 20 24 40 60 ns
overshoot 2V step 5 7 11 14 %
slew rate 2V step 290 170 150 140 V/µs

DISTORTION AND NOISE RESPONSE

2

nd

harmonic distortion 2Vpp, 1MHz -72 – – – dBc

2V

pp

, 1MHz; RL= 1kΩ -84 – – – dBc

2V

pp

, 5MHz -71 -54 -52 -52 dBc

3

rd

harmonic distortion 2Vpp, 1MHz -87 – – – dBc

2V

pp

, 1MHz; RL= 1kΩ -95 – – – dBc

2V

pp

, 5MHz -78 -61 -54 -54 dBc

equivalent input noise

voltage (e

ni

) >1MHz 4.9 5.9 6.4 6.4 nV/√Hz

non-inverting current (i

bn

) >1MHz 6.6 8.5 9.3 9.3 pA/√Hz

inverting current (i

bi

) >1MHz 11.1 14.7 15.8 15.8 pA/√Hz

crosstalk (input referred) 10MHz, 1V

pp

-54 – – – dB

crosstalk, all hostile (input referred) 10MHz, 1V

pp

-52 – – – dB

STATIC DC PERFORMANCE

input offset voltage 13 30 35 35 mV A

average drift 80 – – – µV/˚C

input bias current (non-inverting) 5 18 24 24 µAA

average drift 30 – – – nA/˚C

gain accuracy ±0.3 ±1.5 ±2.0 ±2.0 % A

internal resistors (R

f

, Rg) 1000 ±20% ±26% ±30% Ω
power supply rejection ratio DC 48 45 43 43 dB
common-mode rejection ratio DC 44 41 39 39 dB
supply current (per amplifier) R

L

= ∞ 3.0 3.4 3.6 3.6 mA A

MISCELLANEOUS PERFORMANCE

input resistance (non-inverting) 1.0 0.62 0.56 0.56 MΩ
input capacitance (non-inverting) 2.2 3.3 3.3 3.3 pF
input voltage range, High 4.2 4.1 4.0 4.0 V
input voltage range, Low 0.8 0.9 1.0 1.0 V
output voltage range, High R

L

= 100Ω 4.0 3.9 3.8 3.8 V

output voltage range, Low R

L

= 100Ω 1.0 1.1 1.2 1.2 V

output voltage range, High R

L

= ∞ 4.1 4.0 4.0 3.9 V

output voltage range, Low R

L

= ∞ 0.9 1.0 1.0 1.1 V
output current 100 80 65 40 mA B
output resistance, closed loop DC 400 600 600 600 mΩ

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.

+5V Electrical Characteristics

(Av= +2, RL= 100Ω,Vs= +5V1,Vcm= VEE+ (Vs/2), RLtied to Vcm, unless specified)

Absolute Maximum Ratings

supply voltage (VCC- VEE)

+

14V
output current (see note C) 140mA
common-mode input voltage

VEEto

V

CC

maximum junction temperature +150°C
storage temperature range -65°C to +150°C
lead temperature (soldering 10 sec) +300°C
ESD rating (human body model) 2000V

Notes

A) J-level:spec is 100% tested at +25°C.
B)The short circuit current can exceed the maximum safe

output current.

1) V

s

= VCC- V

EE

Reliability Information

Transistor Count 147
MTBF (based on limited test data) 301Mhr

3 http://www.national.com

PARAMETERS CONDITIONS TYP GUARANTEED MIN/MAX UNITS NOTES
Ambient Temperature CLC5633IN/IM +25°C +25°C 0 to 70°C -40 to 85°C

FREQUENCY DOMAIN RESPONSE

-3dB bandwidth V

o

= 1.0V

pp

130 100 90 90 MHz

V

o

= 4.0V

pp

80 60 55 55 MHz

-

0.1dB bandwidth Vo= 1.0V

pp

20 17 12 12 MHz

gain peaking <200MHz, V

o

= 1.0V

pp

0 0.5 1.0 1.0 dB

gain rolloff <30MHz, V

o

= 1.0V

pp

0.1 0.3 0.5 0.5 dB

linear phase deviation <30MHz, V

o

= 1.0V

pp

0.2 0.4 0.6 0.6 deg

differential gain NTSC, R

L

=150Ω 0.03 0.08 – – %

differential phase NTSC, R

L

=150Ω 0.06 0.1 – – deg

TIME DOMAIN RESPONSE

rise and fall time 2V step 5.0 6.5 7.0 7.7 ns
settling time to 0.05% 2V step 20 30 44 67 ns
overshoot 2V step 14 17 18 19 %
slew rate 2V step 410 310 240 225 V/µs

DISTORTION AND NOISE RESPONSE

2

nd

harmonic distortion 2Vpp, 1MHz -73 – – – dBc

2V

pp

, 1MHz; RL= 1kΩ -92 – – – dBc

2V

pp

, 5MHz -69 -58 -56 -56 dBc

3

rd

harmonic distortion 2Vpp, 1MHz -92 – – – dBc

2V

pp

, 1MHz; RL= 1kΩ -96 – – – dBc

2V

pp

, 5MHz -72 -66 -65 -65 dBc

equivalent input noise

voltage (e

ni

) >1MHz 4.9 5.9 6.4 6.4 nV/√Hz

non-inverting current (i

bn

) >1MHz 6.6 8.5 9.3 9.0 pA/√Hz

inverting current (i

bi

) >1MHz 11.1 14.7 15.8 15.8 pA/√Hz

crosstalk (input referred) 10MHz, 1V

pp

-54 – – – dB

crosstalk, all hostile (input referred) 10MHz, 1V

pp

-52 – – – dB

STATIC DC PERFORMANCE

output offset voltage 7 30 35 35 mV

average drift 80 – – – µV/˚C

input bias current (non-inverting) 5 18 25 25 µA

average drift 40 – – – nA/˚C

gain accuracy ±0.3 ±1.5 ±2.0 ±2.0 %

internal resistors (R

f

, Rg) 1000 ±20% ±26% ±30% Ω
power supply rejection ratio DC 48 45 43 43 dB
common-mode rejection ratio DC 44 41 39 39 dB
supply current (per amplifier) R

L

= ∞ 3.2 3.8 4.0 4.0 mA

MISCELLANEOUS PERFORMANCE

input resistance (non-inverting) 1.1 0.63 0.57 0.57 MΩ
input capacitance (non-inverting) 1.9 2.85 2.85 2.85 pF
common-mode input range

±

4.2

±

4.1

±

4.1

±

4.0 V

output voltage range R

L

= 100Ω

±

3.8

±

3.6

±

3.6

±

3.5 V

output voltage range R

L

= ∞

±

4.0

±

3.8

±

3.8

±

3.7 V
output current 130 100 80 50 mA B
output resistance, closed loop DC 400 600 600 600 mΩ

±5V Electrical Characteristics

(Av= +2, RL= 100Ω,VCC= ±5V, unless specified)

Notes

B)The short circuit current can exceed the maximum safe

output current.

Ordering Information

Model Temperature Range Description

CLC5633IN -40°C to +85°C 8-pin PDIP
CLC5633IM -40°C to +85°C 8-pin SOIC
CLC5633IMX -40°C to +85°C 8-pin SOIC tape and reel

Pac kage Thermal Resistance

Package

θθ

JC

θθ

JA

Plastic (IN) 60°C/W 110°C/W
Surface Mount (IM) 55°C/W 125°C/W

http://www.national.com 4

+5V T ypical Performance

(Av= +2, RL= 100Ω,Vs= +5V1,Vcm= VEE+ (Vs/2), RLtied to Vcm, unless specified)

Frequency Response

Vo = 0.5V

Gain

Phase

pp

Av = +1

Av = -1

Av = +2

Normalized Magnitude (1dB/div)

1M

10M

100M

Frequency (Hz)

Frequency Response vs. Vo (Av = 2)

Vo = 0.1V

Vo = 2V

pp

Vo = 2.5V

pp

Magnitude (1dB/div)

1M

10M

100M

Frequency (Hz)

PSRR & CMRR

60

CMRR

50

PSRR

40

30

20

PSRR & CMRR (dB)

10

0

1k 10k 100M

100k 1M 10M

Frequency (Hz)

2nd & 3rd Harmonic Distortion, RL =

-40

3rd, 10MHz

2nd, 10MHz

-50

-60

Distortion (dBc)

2nd, 1MHz

-70

3rd, 1MHz

-80
0 0.5 1 1.5 2 2.5

Output Amplitude (Vpp)

Large & Small Signal Pulse Response

Large Signal

Small Signal

Output Voltage (0.05V/div)

Time (10ns/div)

pp

Vo = 1V

pp

Phase (deg)

0

-90

-180

-270

-360

-450

Frequency Response vs. R

Vo = 0.5V

pp

Gain

Phase

RL = 25Ω

Magnitude (1dB/div)

1M

10M

L

RL = 100Ω

100M

Frequency (Hz)

Frequency Response vs. Vo (Av = 1)

Vo = 0.1V

pp

Vo = 1.5V

pp

Vo = 2V

pp

Vo = 2.5V

10M

pp

100M

Magnitude (1dB/div)

1M

Frequency (Hz)

Equivalent Input Noise

3.6

3.5

3.4

Inverting Current 8.7pA/√Hz

Non-Inverting Current 7pA/√Hz

Voltage 3.35nV/√Hz

3.3

Noise Voltage (nV/√Hz)

3.2
10k 100k 1M 10M

Frequency (Hz)

2nd & 3rd Harmonic Distortion, RL = 100Ω

-55

3rd, 10MHz

-65

2nd, 1MHz

-75

Distortion (dBc)

-85

-95

2nd, 10MHz

3rd, 1MHz

0 0.5 1 1.5 2 2.5

Output Amplitude (Vpp)

Output Impedance vs. Frequency

50

40

30

20

10

Output Impedance (Ω)

0

10k 100k 1M 10M

1k

Frequency (Hz)

RL = 1kΩ

100M

Phase (deg)

0

-90

-180

-270

-360

-450

12.5

Noise Current (pA/√Hz)

10

7.5

5

2.5

Gain Flatness & Linear Phase

Vo = 0.5V

Gain

Phase

pp

Magnitude (0.05dB/div)

0

10

20

30

Frequency (MHz)

Frequency Response vs. Vo (Av = -1)

Vo = 0.1V

Vo = 2V

Vo = 2.5V

Vo = 1V

pp

pp

pp

pp

Magnitude (1dB/div)

1M

10M

100M

Frequency (Hz)

2nd & 3rd Harmonic Distortion

-50

Vo = 2V

pp

-60

2nd

RL = 100Ω

-70

2nd

RL = 1kΩ

-80

Distortion (dBc)

-90

-100
1M

3rd

RL = 100Ω

3rd

RL = 1kΩ

10M

Frequency (Hz)

2nd & 3rd Harmonic Distortion, RL = 1kΩ

-50

-60

-70

-80

-90

Distortion (dBc)

-100

-110

0 0.5 1 1.5 2 2.5

2nd, 1MHz

3rd, 1MHz

3rd, 10MHz

2nd, 10MHz

Output Amplitude (Vpp)

IBN & VIO vs. Temperature

2.5

1.5 7

(mV)

IO

0 6.5

0.5 6

I

-1.5 5.5

Offset Voltage V

BN

V

IO

-2.5

-60

-20 0 20 60

100-40 40 80

Temperature (°C)

0.05

0

Phase (deg)

-0.05

-0.1

-0.15

-0.2

7.5

I

BN

(µA)

5

5 http://www.national.com

±5V T ypical Performance

(Av= +2, RL= 100Ω,VCC= ± 5V, unless specified)

Frequency Response

Vo = 1.0V

pp

Av = -1

Gain

Phase

Av = +2

Normalized Magnitude (1dB/div)

1M

10M

Frequency (Hz)

Frequency Response vs. Vo (Av = 2)

Vo = 0.1V

Vo = 5V

pp

Vo = 1V

pp

Magnitude (1dB/div)

1M

10M

Frequency (Hz)

Large & Small Signal Pulse Response

Large Signal

Small Signal

Output Voltage (0.5V/div)

Time (10ns/div)

2nd & 3rd Harmonic Distortion, RL = 25Ω

-45

-50

-55

2nd, 10MHz

3rd, 10MHz

-60

-65

-70

Distortion (dBc)

-75

-80

2nd, 1MHz

3rd, 1MHz

-85
0 0.5 1 1.5 2 2.5

Output Amplitude (Vpp)

Short Term Settling Time

0.2

0.15

0.1

0.05
0

-0.05

(% Output Step)

o

-0.1

V

-0.15

-0.2
1 10 100 1000 10000

Time (ns)

Av = +1

100M

pp

Vo = 2V

100M

Vo = 2V step

0

-45

-90

-135

-180

-225

pp

Phase (deg)

Magnitude (1dB/div)

Magnitude (1dB/div)

0.02
0

-0.02

Gain (%)

-0.12

-60

-65

-70

-75

-80

-85

Distortion (dBc)

-90

-95

0.2

0.15

0.1

0.05
0

-0.05

(% Output Step)

o

-0.1

V

-0.15

-0.2

Frequency Response vs. R

Vo = 1.0V

pp

Gain

Phase

RL = 100Ω

L

Phase (deg)

RL = 1kΩ

0

-90

RL = 25Ω

-180

-270

-360

-450

1M

10M

100M

Frequency (Hz)

Frequency Response vs. Vo (Av = 1)

Vo = 1V

pp

pp

pp

pp

100M

1M

Vo = 0.1V

Vo = 5V

Vo = 2V

10M

Frequency (Hz)

Differential Gain & Phase

f = 3.58MHz

Phase Neg Sync

Gain Neg Sync

Gain Pos Sync

1234

Phase Pos Sync

-0.02

-0.04

-0.06

Phase (deg)

-0.08-0.04

-0.1-0.06

-0.12-0.08

Distortion Level (dBc)

-0.14-0.1

-0.16

-100

Number of 150 Ω Loads

2nd & 3rd Harmonic Distortion, RL = 100Ω

3rd, 10MHz

2nd, 10MHz

2nd, 1MHz

3rd, 1MHz

Distortion (dBc)

-100

-110

0 0.5 1 1.5 2 2.5

Output Amplitude (Vpp)

Long Term Settling Time

Vo = 2V step

(mV)

OS

Offset Voltage V

1

µ

10

µ

100

µ

1m 10m

Time (s)

Gain Flatness & Linear Phase

VO = 1V

Gain

0

pp

-0.1

Phase (deg)

-0.2

Phase

Magnitude (0.1dB/div)

-0.3

-0.4

-0.5

0

10 15 20 30

5

25

Frequency (MHz)

Frequency Response vs. Vo (Av = -1)

Vo = 1V

pp

Vo = 0.1V

Vo = 5V

Vo = 2V

pp

pp

pp

Magnitude (1dB/div)

1M

10M

100M

Frequency (Hz)

2nd & 3rd Harmonic Distortion

-60

Vo = 2V

pp

2nd

RL = 100Ω

-70

2nd

-80

RL = 1kΩ

3rd

-90

3rd

RL = 1kΩ

RL = 100Ω

110

Frequency (MHz)

2nd & 3rd Harmonic Distortion, RL = 1kΩ

-60

2nd, 10MHz

-70

-80

-90

3rd, 10MHz

2nd, 1MHz

3rd, 1MHz

012345

Output Amplitude (Vpp)

IBN & VOS vs. Temperature

7.5 2.5

7.0

6.5 0.5

1.5

I

BN

(µA)

6.0 -0.5

V

5.5 -1.5

5.0

OS

I

BN

-2.5

-60 -20 20 60 100

Temperature (°C)

http://www.national.com 6

±5V Typical Channel Matching Performance

(Av= +2, RL= 100Ω,VCC= ± 5V, unless specified)

CLC5633 Operation

The CLC5633 is a current feedback buffer built in an
advanced complementary bipolar process. The
CLC5633 operates from a single 5V supply or dual ±5V
supplies. Operating from a single 5V supply, the
CLC5633 has the following features:

■

Gains of +1, -1, and 2V/V are achievable without
external resistors

■

Provides 100mA of output current while
consuming only 15mW of power

■

Offers low -84/-95dBc 2nd and 3rd harmonic
distortion

■

Provides BW > 90MHz and 1MHz distortion
< -70dBc at Vo= 2V

pp

The CLC5633 performance is further enhanced in ±5V
supply applications as indicated in the

±5V Electrical

Characteristics

table and

±5V Typical Performance

plots.

If gains other than +1, -1, or +2V/V are required, then the
CLC5602 can be used. The CLC5602 is a current feed­back amplifier with near identical performance and allows
for external feedback and gain setting resistors.

Current Feedback Amplifiers

Some of the key f eatures of current feedbac k technology are:

■

Independence of AC bandwidth and voltage gain

■

Inherently stable at unity gain

■

Adjustable frequency response with feedbac k resistor

■

High slew rate

■

Fast settling

Current feedback operation can be described using a simple
equation. The voltage gain for a non-inver ting or inverting
current feedback amplifier is approximated by Equation 1.

Equation 1

where:

■

Avis the closed loop DC voltage gain

■

Rfis the feedback resistor

■

Z(jω) is the CLC5633’s open loop
transimpedance gain

■

is the loop gain

The denominator of Equation 1 is approximately equal to
1 at low frequencies. Near the -3dB corner frequency, the
interaction between Rfand Z(jω) dominates the circuit
performance. The value of the feedback resistor has a
large affect on the circuits performance. Increasing R

f

has the following affects:

■

Decreases loop gain

■

Decreases bandwidth

■

Reduces gain peaking

■

Lowers pulse response overshoot

■

Affects frequency response phase linearity

V
V

A

1

R

Z(j )

o

in

v

f

=

+

ω

ZjRω

()

CLC5633 Design Information

Closed Loop Gain Selection

The CLC5633 is a current feedback op amp with
Rf = Rg = 1kΩ on chip (in the package). Select from
three closed loop gains without using any external gain or
feedback resistors. Implement gains of +2, +1,
and -1V/V by connecting pins 5 and 6 (or 9 and 10, or 12
and 13) as described in the chart below.

Gain

Input Connections

A

v

Non-Inverting (pins 5,10, & 12) Inverting (pins 6,9, & 13)

-1V/V ground input signal
+1V/V input signal NC (open)
+2V/V input signal ground

Channel Matching

Channel 2

Channel 3

Channel 1

Magnitude (0.5dB/div)

1M 10M 100M

Frequency (Hz)

All Hostile Crosstalk

-30

-40

-50

-60

Magnitude (dB)

-70

-80
1M

Frequency (Hz)

Pulse Crosstalk

Active Output

Channel 1

Inactive Output

Channel 2

Inactive Output

Channel 3

10M 100M

Active Channel

Amplitude (0.2V/div)

Time (10ns/div)

Amplitude (20mV/div)

Inactive Channel

7 http://www.national.com

The gain accuracy of the CLC5633 is excellent and
stable over temperature change. The internal gain
setting resistors, Rfand Rgare diffused silicon resistors
with a process variation of ± 20% and a temperature
coefficient of ˜ 2000ppm/°C. Although their absolute
values change with processing and temperature, their
ratio (Rf/Rg) remains constant. If an external resistor is
used in series with Rg, gain accuracy over temperature
will suffer.

Single Supply Operation (VCC= +5V, VEE= GND)

The specifications given in the

+5V Electrical Character-

istics

table for single supply operation are measured with
a common mode voltage (Vcm) of 2.5V. Vcmis the volt­age around which the inputs are applied and the
output voltages are specified.

Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC5633 is typically +0.8V to
+4.2V. The typical output range with RL=100Ω is +1.0V
to +4.0V.

For single supply DC coupled operation, keep input
signal levels above 0.8V DC. For input signals that drop
below 0.8V DC, AC coupling and level shifting the signal
are recommended. The non-inverting and inverting
configurations for both input conditions are illustrated in
the following 2 sections.

DC Coupled Single Supply Operation

Figures 1, 2, and 3 on the following page, show the
recommended configurations for input signals that
remain above 0.8V DC.

Figure 1: DC Coupled, Av= -1V/V Configuration

Figure 2: DC Coupled, Av= +1V/V Configuration

Figure 3: DC Coupled, Av= +2V/V Configuration

AC Coupled Single Supply Operation

Figures 4, 5, and 6 show possible non-inv erting and invert­ing configurations for input signals that go below 0.8V DC.

Figure 4: AC Coupled, Av= -1V/V Configuration

The input is AC coupled to prevent the need for
level shifting the input signal at the source. The resistive
voltage divider biases the non-inverting input to VCC÷2
= 2.5V (For VCC= +5V).

Figure 5: AC Coupled, Av= +1V/V Configuration

Note: Rt and RL and Rg are tied to Vcm for minimum power
consumption and maximum output swing.

Channel 2 and 3 not shown.

V

CC

6.8µF

1 14

+

2 13

1kΩ

+

-

1kΩ

3 12

0.1µF

V

in

V

cm

R

t

V

o

R

V

cm

L

V

cm

1kΩ

-

1kΩ

+

1kΩ

-

+

1kΩ

4 11
5 10
6 9
7 8

CLC5633

Note: Rb provides DC bias for the non-inverting input. Rb, RL and Rt are tied to Vcm

for minimum power consumption and maximum output swing.
Channel 2 and 3 not shown.

V

CC

6.8µF

1 14

+

2 13

1kΩ

+

-

1kΩ

3 12

0.1µF

V

in

R

b

V

cm

V

o

R

t

R

L

V

cm

V

cm

1kΩ

-

1kΩ

+

1kΩ

-

+

1kΩ

4 11
5 10
6 9
7 8

CLC5633

Select Rt to yield desired Rin = Rt||Rg, where Rg = 1kΩ.

Note: Rt and RL are tied to Vcm for minimum power
consumption and maximum output swing.

Channel 2 and 3 not shown.

V

CC

6.8µF

+

1 14
2 13
3 12

0.1µF

V

in

R

t

V

o

V

cm

R

L

V

cm

4 11
5 10
6 9
7 8

+

-

1kΩ

-

1kΩ

-

+

CLC5633

1kΩ

1kΩ

+

1kΩ
1kΩ

Note: Channel 2 and 3 not shown.

V

CC

6.8µF

V

CC

0.1µF

R

V

V V 2.5

=− +

o

in

in

R

Low frequency cutoff

where Rg = 1kΩ.

1 14

+

2 13
3 12
4 11
5 10
6 9

C

V

C

o

7 8

1

,

=

2RC

π

g

C

1kΩ

+

-

1kΩ

-

+

1kΩ

-

+

CLC5633

1kΩ

1kΩ
1kΩ

Note: Channel 2 and 3 not shown.

V

CC

C

C

V

in

V 2V 2.5

o

Low frequency cutoff

whereR

V

CC

R

R

C

=+

in

R

=>>

in

2

6.8µF

+

0.1µF

V

=

2RC

π

RR

source

1 14
2 13
3 12
4 11
5 10
6 9

o

1

in

7 8

,

C

1kΩ

+

-

1kΩ

-

1kΩ

-

+

CLC5633

1kΩ

+

1kΩ
1kΩ

http://www.national.com 8

Figure 6: AC Coupled, Av= +2V/V Configuration

Dual Supply Operation

The CLC5633 operates on dual supplies as well as sin­gle supplies. The non-inverting and inverting configura­tions are shown in Figures 7, 8 and 9.

Figure 7: Dual Supply, Av= -1V/V Configuration

Figure 8: Dual Supply, Av= +1V/V Configuration

Figure 9: Dual Supply, Av= +2V/V Configuration

Load Termination

The CLC5633 can source and sink near equal amounts
of current. For optimum performance, the load should be
tied to Vcm.

Driving Cables and Capacitive Loads

When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC5633
will improve stability and settling performance. The

Frequency Response vs. C

L

plot, shown below in
Figure 10, gives the recommended series resistance
value for optimum flatness at var ious capacitive loads.

Figure 10: Frequency Response vs. C

L

Transmission Line Matching

One method for matching the characteristic impedance
(Zo) of a transmission line or cable is to place the
appropriate resistor at the input or output of the amplifier.
Figure 11 shows typical inverting and non-inverting
circuit configurations for matching transmission lines.

C

C

V

in

V 2V 2.5

o

Low frequency cutoff

whereR

Note: Channel 2 and 3 not shown.

V

CC

6.8µF

+

V

CC

0.1µF

R

R

C

V

o

=+

in

R

=>>

in

2

=

2RC

π

RR

source

1

,

in

C

1 14
2 13

1kΩ

+

-

1kΩ

3 12

1kΩ

-

1kΩ

+

1kΩ

-

+

1kΩ

4 11
5 10
6 9
7 8

CLC5633

Note: Channel 2 and 3 not shown.

V

CC

6.8µF

+

1 14
2 13
3 12

0.1µF

V

in

R

t

4 11
5 10
6 9

V

o

7 8

1kΩ

+

-

1kΩ

-

+

1kΩ

-

+

CLC5633

1kΩ
1kΩ

1kΩ

0.1µF

+

6.8µF

V

EE

Note: Rb provides DC bias for the
non-inverting input. Select Rt to
yield desired Rin = Rt||1kΩ.

Channel 2 and 3 not shown.

V

CC

6.8µF

1 14

+

2 13

1kΩ

+

-

1kΩ

3 12

0.1µF

V

R

in

b

V

o

R

t

1kΩ

-

1kΩ

+

1kΩ

-

+

1kΩ

4 11
5 10
6 9
7 8

CLC5633

0.1µF

+

6.8µF

V

EE

Note: Channel 2 and 3 not shown.

-60

2nd, 10MHz

-70

-80

-90

Distortion (dBc)

-100

3rd, 10MHz

2nd, 1MHz

3rd, 1MHz

V

CC

6.8µF

1 14

+

2 13

1kΩ

+

-

1kΩ

3 12

0.1µF

V

in

R

t

V

o

1kΩ

-

1kΩ

+

1kΩ

-

+

1kΩ

4 11
5 10
6 9
7 8

0.1µF

+

6.8µF

CLC5633

V

EE

-110
012345

Output Amplitude (Vpp)

9 http://www.national.com

Non-inverting gain applications:

■

Connect pin 2 as indicated in the table in the

Closed Loop Gain Selection

section.

■

Make R1, R2, R6, and R7equal to Zo.

■

Use R3to isolate the amplifier from reactive
loading caused by the transmission line,
or by parasitics.

Inverting gain applications:

■

Connect R3directly to ground.

■

Make the resistors R4, R6, and R7equal to Zo.

■

Make R5II Rg= Zo.

The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C6to match the output transmission line over a
greater frequency range. C6compensates for the increase
of the amplifier’s output impedance with frequency

Figure 11:Transmission Line Matching

Power Dissipation

Follow these steps to determine the power consumption
of the CLC5633:

1. Calculate the quiescent (no-load) power:
P

amp

= ICC(VCC- VEE)

2. Calculate the RMS power at the output stage:
Po= (VCC- V

load

) (I

load

), where V

load

and I

load

are the RMS voltage and current across the
external load.

3. Calculate the total RMS power:
Pt= P

amp

+ P

o

The maximum power that the DIP and SOIC,
packages can dissipate at a given temperature is
illustrated in Figure 12. The power derating curve for
any CLC5633 package can be derived by utilizing the
following equation:

where
T

amb

= Ambient temperature (°C)

θJA= Thermal resistance, from junction to ambient,

for a given package (°C/W)

Figure 12: Power Derating Curve

Layout Considerations

A proper printed circuit layout is essential for achieving
high frequency performance. National provides
evaluation boards for the CLC5633 (CLC730075-DIP,
CLC730074-SOIC) and suggests their use as a guide for
high frequency layout and as an aid f or de vice testing and
characterization.

General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:

■

Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.

■

Place the 6.8µF capacitors within 0.75 inches
of the power pins.

■

Place the 0.1µF capacitors less than 0.1 inches
from the power pins.

■

Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance.

■

Minimize all trace lengths to reduce series
inductances.

■

Use flush-mount printed circuit board pins for
prototyping, never use high profile DIP sockets.

Evaluation Board Information

A data sheet is available f or the CLC730075/ CLC730074
evaluation boards .The evaluation board data sheets pro­vide:

■

Evaluation board schematics

■

Evaluation board lay outs

■

General information about the boards

The evaluation boards are designed to accommodate
dual supplies. The boards can be modified to provide
single supply operation. For best performance; 1) do
not connect the unused supply, 2) ground the unused
supply pin.

(175 T

amb

JA

°− )

θ

Note: Channel 2 and 3 not shown.

Z

R

+

V

2

-

R

+

V

1

-

0

1

Z

0

4

R

R

1 14
2 13

R

3

3 12

2

4 11
5 10
6 9
7 8

5

1kΩ

+

-

1kΩ

-

1kΩ

-

+

CLC5633

+

1kΩ
1kΩ

1kΩ

Z

R

6

C

6

0

V

o

R

7

1.0

0.8

0.6

0.4

Power (W)

0.2

0

-40 -20 0 20 40 60 80 100 120 180

Ambient Temperature (°C)

IN

IM

140 160

http://www.national.com 10

Special Evaluation Board
Considerations for the CLC5633

To optimize off-isolation of the CLC5633, cut the Rftrace
on both the CLC730074 and the CLC730075 evaluation
boards. This cut minimizes capacitive feedthrough
between the input and the output.

SPICE Models

SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for National’s
monolithic amplifiers that:

■

Support Berkeley SPICE 2G and its many derivatives

■

Reproduce typical DC, AC, Transient, and Noise
performance

■

Support room temperature simulations

The

readme

file that accompanies the diskette lists
released models, and provides a list of modeled parame­ters. The application note OA-18, Simulation SPICE
Models for National’s Op Amps, contains schematics and
a reproduction of the readme file.

Application Circuits

Single Supply Cable Driver

Figure 13 below shows the CLC5633 driving 10m of 75Ω
coaxial cable. The CLC5633 is set for a gain of +2V/V

to compensate for the divide-by-two voltage drop at
Vo. The response after 10m of cable is illustrated in
Figure 14.

Figure 13: Single Supply Cable Driver

Figure 14: Response After 10m of Cable

V

0.1µF

in

+5V

5kΩ

5kΩ

6.8µF

0.1µF

0.1µF

+5V

1 14

+

2 13
3 12
4 11
5 10
6 9
7 8

1kΩ

+

-

1kΩ

-

1kΩ

-

+

CLC5633

1kΩ

+

1kΩ
1kΩ

Note: Channel 2 and 3 not shown.

75Ω

0.1µF

10m of 75Ω

Coaxial Cable

V

75Ω

Vin = 10MHz, 0.5V

o

100mV/div

pp

20ns/div

11 http://www.national.com

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CLC5633

Triple, High Output, Programmable Gain Buffer

http://www.national.com 12

Customer Design Applications Support

National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax [phone].

Life Support Policy

National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of
the president of National Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perfor m, when proper ly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.

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Corporation Europe Hong Kong Ltd. Japan Ltd.

1111 West Bardin Road Fax:[phone] 2501 Miramar Tower Tel: [phone]
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said
circuitry and specifications.

N