Datasheet CLC451AJP, CLC451AJM5X, CLC451AJM5, CLC451AJE-TR13, CLC451AJE Datasheet (NSC)

Features

■

100mA output current

■

1.5mA supply current

■

85MHz bandwidth (Av= +2)

■

-66/-75dBc HD2/HD3 (1MHz)

■

25ns settling to 0.05%

■

260V/µs slew rate

■

Stable for capacitive loads up to 1000pF

■

Single 5V to ±5V supplies

■

Available in Tiny SOT23-5 package

Applications

■

Coaxial cable driver

■

Twisted pair driver

■

Transformer/Coil Driver

■

High capacitive load driver

■

Video line driver

■

Portable/battery-powered applications

■

A/D driver

V

EE

1kΩ

1kΩ

0.1µF

6.8µF

V

in

5kΩ

5kΩ

+

+5V

+5V

1

CLC451

7
6

8

5

3
4

2

1kΩ

1kΩ

0.1µF

0.1µF
V

o

10m of 75Ω

Coaxial Cable

75Ω

0.1µF

75Ω

Typical Application

Single Supply Cable Driver

Pinout

DIP & SOIC

General Description

The CLC451 is a low cost, high speed (85MHz) buffer that
features user-programmable gains of +2, +1, and -1V/V. It has a
new output stage that delivers high output drive current (100mA),
but consumes minimal quiescent supply current (1.5mA) from a
single 5V supply. Its current feedback architecture, fabricated in
an advanced complementary bipolar process, maintains consis­tent performance over a programmable range of gains and wide
signal levels, and has a linear-phase response up to one half of
the -3dB frequency. The CLC451’s internal feedback network
provides an excellent gain accuracy of 0.3%

The CLC451 offers superior dynamic performance with a 85MHz
small-signal bandwidth, 260V/µs slew rate and 6.5ns rise/fall
times (2V

step

). The combination of the small SOT23-5 package,
low quiescent power, high output current drive, and high-speed
performance make the CLC451 well suited for many battery­powered personal communication/computing systems.

The ability to drive low-impedance, highly capacitive loads,
makes the CLC451 ideal for single ended cable applications. It
also drives low impedance loads with minimum distortion. The
CLC451 will drive a 100Ω load with only -78/-65dBc second/third
harmonic distortion (Av= +2, V

out

= 2Vpp, f = 1MHz). With a 25Ω
load, and the same conditions, it produces only -55/-60dBc sec­ond/third harmonic distortion. It is also optimized for driving high
currents into single-ended transformers and coils.

When driving the input of high-resolution A/D converters, the
CLC451 provides excellent -66/-75dBc second/third harmonic
distortion (Av= +2, V

out

= 2Vpp, f = 1MHz, RL= 1kΩ) and fast

settling time.

Maximum Output Voltage vs. R

L

Output Voltage (V

pp

)

RL (Ω)

1

2

3

4

5

6

7

8

9

10

10

100

1000

Vs = +5V

VCC = ±5V

CLC451
Single Supply, Low-Power, High Output,
Programmable Buffer

N

June 1999

CLC451

Single Supply, Low-Power, High Output, Programmable Buffer

Response After 10m of Cable

100mV/div

20ns/div

Vin = 10MHz, 0.5V

pp

V

inv

V

CC

V

EE

V

o

V

non-inv

1kΩ

1kΩ

+-

Pinout

SOT23-5

© 1999 National Semiconductor Corporation http://www.national.com

Printed in the U.S.A.

http://www.national.com 2

PARAMETERS CONDITIONS TYP MIN/MAX RATINGS UNITS NOTES
Ambient T emper ature CLC451AJ +25°C +25°C 0 to 70°C -40 to 85°C

FREQUENCY DOMAIN RESPONSE

-3dB bandwidth V

o

= 0.5V

pp

85 60 55 55 MHz

V

o

= 2.0V

pp

70 55 50 45 MHz

-

0.1dB bandwidth Vo= 0.5V

pp

20 15 13 13 MHz

gain peaking <200MHz, V

o

= 0.5V

pp

0 0.5 0.9 1.0 dB

gain rolloff <30MHz, V

o

= 0.5V

pp

0.2 0.5 0.7 0.7 dB

linear phase deviation <30MHz, V

o

= 0.5V

pp

0.1 0.4 0.5 0.5 deg

TIME DOMAIN RESPONSE

rise and fall time 2V step 6.5 9.0 9.7 10.5 ns
settling time to 0.05% 1V step 25 – – – ns
overshoot 2V step 13 15 18 18 %
slew rate 2V step 260 180 165 150 V/µs

DISTORTION AND NOISE RESPONSE

2

nd

harmonic distortion 2Vpp, 1MHz -78 -72 -70 -70 dBc

2V

pp

, 1MHz; RL= 1kΩ -66 -60 -58 -58 dBc

2V

pp

, 5MHz -60 -54 -52 -52 dBc

3

rd

harmonic distortion 2Vpp, 1MHz -65 -61 -59 -59 dBc

2V

pp

, 1MHz; RL= 1kΩ -75 -69 -67 -67 dBc

2V

pp

, 5MHz -52 -48 -46 -46 dBc

equivalent input noise

voltage (e

ni

) >1MHz 3.0 3.7 4 4 nV/√Hz

non-inverting current (i

bn

) >1MHz 6.9 9 10 10 pA/√Hz

inverting current (i

bi

) >1MHz 8.5 11 12 12 pA/√Hz

STATIC DC PERFORMANCE

input offset voltage 8 30 37 37 mV A

average drift 80 – – – µV/˚C

input bias current (non-inverting) 3 14 17 18 µAA

average drift 25 – – – nA/˚C

gain accuracy ±0.3 ±1.5 ±2.0 ±2.0 % A

internal resistors (R

f

, Rg) 1000 ±20% ±26% ±30% Ω
power supply rejection ratio DC 49 46 44 44 dB
common-mode rejection ratio DC 51 48 46 46 dB
supply current R

L

= ∞ 1.5 1.7 1.8 1.8 mA A

MISCELLANEOUS PERFORMANCE

input resistance (non-inverting) 0.5 0.37 0.33 0.33 MΩ
input capacitance (non-inverting) 1.5 2.3 2.3 2.3 pF
input voltage range, High 4.2 4.1 4.0 4.0 V
input voltage range, Low 0.8 0.9 1.0 1.0 V
output voltage range, High R

L

= 100Ω 4.0 3.9 3.8 3.8 V

output voltage range, Low R

L

= 100Ω 1.0 1.1 1.2 1.2 V

output voltage range, High R

L

= ∞ 4.1 4.0 4.0 3.9 V

output voltage range, Low R

L

= ∞ 0.9 1.0 1.0 1.1 V
output current 100 80 65 40 mA B
output resistance, closed loop DC 400 600 600 600 mΩ

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.

+5V Electrical Characteristics

(Av= +2, RL= 100Ω,Vs= +5V1,Vcm= VEE+ (Vs/2), RLtied to Vcm, unless specified)

Absolute Maximum Ratings

supply voltage (VCC- VEE)

+

14V
output current (see note C) 140mA
common-mode input voltage

VEEto

V

CC

maximum junction temperature +150°C
storage temperature range -65°C to +150°C
lead temperature (soldering 10 sec) +300°C
ESD rating (human body model) 500V

Notes

A) J-level:spec is 100% tested at +25°C.
B)The short circuit current can exceed the maximum safe

output current.

1) V

s

= VCC- V

EE

Reliability Information

Transistor Count 49
MTBF (based on limited test data) 31Mhr

3 http://www.national.com

PARAMETERS CONDITIONS TYP GUARANTEED MIN/MAX UNITS NOTES
Ambient T emper ature CLC451AJ +25°C +25°C 0 to 70°C -40 to 85°C

FREQUENCY DOMAIN RESPONSE

-3dB bandwidth V

o

= 1.0V

pp

100 80 68 65 MHz

V

o

= 4.0V

pp

55 45 42 40 MHz

-

0.1dB bandwidth Vo= 1.0V

pp

20 15 13 13 MHz

gain peaking <200MHz, V

o

= 1.0V

pp

0 0.5 0.9 1.0 dB

gain rolloff <30MHz, V

o

= 1.0V

pp

0.2 0.7 0.8 0.8 dB

linear phase deviation <30MHz, V

o

= 1.0V

pp

0.1 0.3 0.4 0.4 deg

differential gain NTSC, R

L

=150Ω 0.3 – – – %

differential phase NTSC, R

L

=150Ω 0.3 – – – deg

TIME DOMAIN RESPONSE

rise and fall time 2V step 5.0 6.5 7.0 7.7 ns
settling time to 0.05% 2V step 20 – – – ns
overshoot 2V step 10 13 15 15 %
slew rate 2V step 350 260 240 220 V/µs

DISTORTION AND NOISE RESPONSE

2

nd

harmonic distortion 2Vpp, 1MHz -72 -66 -64 -64 dBc

2V

pp

, 1MHz; RL= 1kΩ -69 -63 -61 -61 dBc

2V

pp

, 5MHz -66 -60 -58 -58 dBc

3

rd

harmonic distortion 2Vpp, 1MHz -65 -61 -59 -59 dBc

2V

pp

, 1MHz; RL= 1kΩ -73 -67 -65 -65 dBc

2V

pp

, 5MHz -52 -48 -46 -46 dBc

equivalent input noise

voltage (e

ni

) >1MHz 3.0 3.7 4 4 nV/√Hz

non-inverting current (i

bn

) >1MHz 6.9 9 10 10 pA/√Hz

inverting current (i

bi

) >1MHz 8.5 11 12 12 pA/√Hz

STATIC DC PERFORMANCE

output offset voltage 3 30 35 35 mV

average drift 80 – – – µV/˚C

input bias current (non-inverting) 1 12 19 19 µA

average drift 40 – – – nA/˚C

gain accuracy ±0.3 ±1.5 ±2.0 ±2.0 %

internal resistors (R

f

, Rg) 1000 ±20% ±26% ±30% Ω
power supply rejection ratio DC 48 45 43 43 dB
common-mode rejection ratio DC 53 50 48 48 dB
supply current R

L

= ∞ 1.6 1.9 2.0 2.0 mA

MISCELLANEOUS PERFORMANCE

input resistance (non-inverting) 0.7 0.50 0.45 0.45 MΩ
input capacitance (non-inverting) 1.2 1.8 1.8 1.8 pF
common-mode input range

±

4.2

±

4.1

±

4.1

±

4.0 V

output voltage range R

L

= 100Ω

±

3.8

±

3.6

±

3.6

±

3.5 V

output voltage range R

L

= ∞

±

4.0

±

3.8

±

3.8

±

3.7 V
output current 130 100 80 50 mA B
output resistance, closed loop DC 400 600 600 600 mΩ

±5V Electrical Characteristics

(Av= +2, RL= 100Ω,VCC= ±5V, unless specified)

Notes

B)The short circuit current can exceed the maximum safe

output current.

Ordering Information

Model Temperature Range Description

CLC451AJP -40°C to +85°C 8-pin PDIP
CLC451AJE -40°C to +85°C 8-pin SOIC
CLC451AJM5 -40°C to +85°C 5-pin SOT
CLC451ALC -40°C to +85°C dice

Pac kage Thermal Resistance

Package

θθ

JC

θθ

JA

Plastic (AJP) 105°C/W 155°C/W
Surface Mount (AJE) 95°C/W 175°C/W
Surface Mount (AJM5) 140°C/W 210°C/W
Dice (ALC) 25°C/W –

http://www.national.com 4

+5V T ypical P erformance

(Av= +2, RL= 100Ω,Vs= +5V1,Vcm= VEE+ (Vs/2), RLtied to Vcm, unless specified)

Frequency Response

Normalized Magnitude (1dB/div)

Frequency (Hz)

10M

Vo = 0.5V

pp

Phase (deg)

-225

-180

-135

-90

-45

0

100M1M

Av = 1

Av = -1

Av = 2

Av = 1

Av = 2

Av = -1

Gain

Phase

Frequency Response vs. R

L

Magnitude (1dB/div)

Frequency (Hz)

10M

Vo = 0.5V

pp

Phase (deg)

-450

-360

-270

-180

-90

0

100M1M

RL = 1kΩ

RL = 100Ω

RL = 25Ω

RL = 1kΩ

RL = 100Ω

RL = 25Ω

Gain

Phase

Frequency Response vs. Vo (Av = 2)

Magnitude (1dB/div)

Frequency (Hz)

10M

100M1M

Vo = 1V

pp

Vo = 2V

pp

Vo = 0.1V

pp

Vo = 2.5V

pp

Frequency Response vs. Vo (Av = +1)

Magnitude (1dB/div)

Frequency (Hz)

10M

100M1M

Vo = 1V

pp

Vo = 2V

pp

Vo = 0.1V

pp

Vo = 2.5V

pp

Frequency Response vs. Vo (Av = -1)

Magnitude (1dB/div)

Frequency (Hz)

10M

100M1M

Vo = 1V

pp

Vo = 2V

pp

Vo = 0.1V

pp

Vo = 2.5V

pp

Frequency Response vs. C

L

Magnitude (1dB/div)

Frequency (Hz)

1M

10M

100M

Vo = 0.5V

pp

CL = 10pF

Rs = 49.9Ω

CL = 100pF

Rs = 21Ω

CL = 1000pF

Rs = 6.7Ω

C

L

1k

R

s

+

-

1k

1k

Gain Flatness

Magnitude (0.05dB/div)

Frequency (MHz)

10

20

30

Vo = 0.5V

pp

Equivalent Input Noise

Noise Voltage (nV/√Hz)

Frequency (Hz)

4

3.5

0.1k 1k 10k 100k 1M 10M

3

2.5

Non-Inverting Current 6.9pA/√Hz

Inverting Current 8.5pA/√Hz

Voltage 3.0nV/√Hz

Noise Current (pA/√Hz)

10

11

12

9

6

8

7

2nd & 3rd Harmonic Distortion

Distortion (dBc)

Frequency (Hz)

1M

10M

Vo = 2V

pp

-90

-80

-70

-60

-50

-40

2nd

RL = 1kΩ

2nd

RL = 100Ω

3rd

RL = 100Ω

3rd

RL = 1kΩ

2nd Harmonic Distortion, RL = 25Ω

Distortion (dBc)

Output Amplitude (Vpp)

0 0.5 1 1.5 2 2.5

-25

-30

-35

-40

-45

-50

-55

2MHz

5MHz

10MHz

1MHz

3rd Harmonic Distortion, RL = 25Ω

Distortion (dBc)

Output Amplitude (Vpp)

0 0.5 1 1.5 2 2.5

-20

-30

-40

-50

-60

2MHz

5MHz

10MHz

1MHz

2nd Harmonic Distortion, RL = 100Ω

Distortion (dBc)

Output Amplitude (Vpp)

0 0.5 1 1.5 2 2.5

-55

-60

-65

-70

-75

-80

-85

-90

2MHz

5MHz

10MHz

1MHz

3rd Harmonic Distortion, RL = 100Ω

Distortion (dBc)

Output Amplitude (Vpp)

0 0.5 1 1.5 2 2.5

-30

-35

-40

-45

-50

-55

-60

-65

-70

2MHz

5MHz

10MHz

1MHz

2nd Harmonic Distortion, RL = 1kΩ

Distortion (dBc)

Output Amplitude (Vpp)

0 0.5 1 1.5 2 2.5

-60

-65

-70

-75

-80

-85

2MHz

5MHz

10MHz

1MHz

3rd Harmonic Distortion, RL = 1kΩ

Distortion (dBc)

Output Amplitude (Vpp)

0 0.5 1 1.5 2 2.5

-50

-55

-60

-65

-70

-75

-80

-85

2MHz

5MHz

10MHz

1MHz

5 http://www.national.com

+5V T ypical P erformance

(Av= +2, RL= 100Ω,Vs= + 5V1,Vcm= VEE+ (Vs/2), RLtied to Vcm, unless specified)

Closed Loop Output Resistance

Output Resistance (Ω)

Frequency (Hz)

10k 100k 1M 10M

100M

0.01

0.1

1

10

100

Recommended Rs vs. C

L

R

s

(Ω)

CL (pF)

10 100 1000

0

10

20

30

40

50

C

L

1k

R

s

+

-

1k

1k

Large & Small Signal Pulse Response

Output Voltage (0.5V/div)

Time (10ns/div)

Large Signal

Small Signal

PSRR & CMRR

PSRR & CMRR (dB)

Frequency (Hz)

1k 10k 100M

0

10

20

30

40

50

60

100k 1M 10M

PSRR
CMRR

IBN, Vos vs. Temperature

Offset Voltage V

os

(mV)

Temperature (°C)

-100 -50 0 50 100 150

-1.1

I

BN

(µA)

1

-1 2

-0.9 3

-0.8 4

-0.7 5

-0.6 6

I

BN

V

os

Maximum Output Voltage vs. R

L

Output Voltage (V

pp

)

RL (Ω)

10 100 1000

1

1.5

2

2.5

3

3.5

4

4.5

5

±5V T ypical P erformance

(Av= +2, RL= 100Ω,VCC= ± 5V,unless specified)

Frequency Response

Normalized Magnitude (1dB/div)

Frequency (Hz)

1M

10M

100M

Phase (deg)

-45

0

-90

-225

-135

-180

Gain

Phase

Vo = 1V

pp

Av = +1

Av = -1

Av = 2

Frequency Response vs. R

L

Magnitude (1dB/div)

Frequency (Hz)

1M

10M

100M

Phase (deg)

-90

0

-180

-450

-270

-360

Gain

Phase

Vo = 1V

pp

RL = 1kΩ

RL = 100Ω

RL = 25Ω

Frequency Response vs. Vo (Av = 2)

Magnitude (1dB/div)

Frequency (Hz)

1M

10M

100M

Vo = 5V

pp

Vo = 1V

pp

Vo = 2V

pp

Vo = 0.1V

pp

Frequency Response vs. Vo (Av = +1)

Magnitude (1dB/div)

Frequency (Hz)

1M

10M

100M

Vo = 5V

pp

Vo = 1V

pp

Vo = 2V

pp

Vo = 0.1V

pp

Frequency Response vs. Vo (Av = -1)

Magnitude (1dB/div)

Frequency (Hz)

1M

10M

100M

Vo = 2V

pp

Vo = 1V

pp

Vo = 0.1V

pp

Frequency Response vs. C

L

Magnitude (1dB/div)

Frequency (Hz)

1M

10M

100M

Vo = 1V

pp

CL = 10pF

Rs = 49.9Ω

CL = 100pF
Rs = 17.4Ω

CL = 1000pF

Rs = 6.7Ω

C

L

1k

R

s

+

-

1k

1k

http://www.national.com 6

±5V T ypical P erformance

(Av= +2, RL= 100Ω,VCC= ± 5V,unless specified)

Gain Flatness

Magnitude (0.05dB/div)

Vo = 1V

pp

Frequency (MHz)

0 5 10 15 20 25 30

Large & Small Signal Pulse Response

Output Voltage (0.5V/div)

Time (10ns/div)

Large Signal

Small Signal

2nd & 3rd Harmonic Distortion

Distortion (dBc)

Frequency (Hz)

1M

10M

Vo = 2V

pp

-90

-80

-70

-60

-50

-40

2nd

RL = 1kΩ

2nd

RL = 100Ω

3rd

RL = 100Ω

3rd

RL = 1kΩ

2nd Harmonic Distortion, RL = 25Ω

Distortion (dBc)

Output Amplitude (Vpp)

012345

-30

-35

-40

-45

-50

-55

-60

2MHz

5MHz

10MHz

1MHz

3rd Harmonic Distortion, RL = 25Ω

Distortion (dBc)

Output Amplitude (Vpp)

012345

-25

-30

-35

-40

-45

-50

-55

-60

2MHz

5MHz

10MHz

1MHz

2nd Harmonic Distortion, RL = 100Ω

Distortion (dBc)

Output Amplitude (Vpp)

012345

-58

-60

-62

-64

-66

-68

-70

-72

-74

2MHz

5MHz

10MHz

1MHz

3rd Harmonic Distortion, RL = 100Ω

Distortion (dBc)

Output Amplitude (Vpp)

012345

-30

-40

-50

-60

-70

-80

2MHz

5MHz

10MHz

1MHz

2nd Harmonic Distortion, RL = 1kΩ

Distortion (dBc)

Output Amplitude (Vpp)

012345

-60

-65

-70

-75

-80

-85

2MHz

5MHz

10MHz

1MHz

3rd Harmonic Distortion, RL = 1kΩ

Distortion (dBc)

Output Amplitude (Vpp)

012345

-50

-55

-60

-65

-70

-75

-80

-85

2MHz

5MHz

10MHz

1MHz

Recommended Rs vs. C

L

R

s

(Ω)

CL (pF)

10 100 1000

50

40

30

20

10

0

C

L

1k

R

s

+

-

1k

1k

Maximum Output Voltage vs. R

L

Output Voltage (V

pp

)

RL (Ω)

10 100 1000

2

3

4

5

6

7

8

10

9

Differential Gain & Phase

Gain (%)

Number of 150Ω Loads

1234

-0.1

Phase (deg)

-0.3

-0.2 -0.4

-0.3 -0.5

-0.4 -0.6

-0.5 -0.7

-0.6 -0.8

-0.7 -0.9

f = 3.58MHz

Gain Positive Sync

Phase Negative Sync

Phase Positive Sync

Gain Negative Sync

IBN, Vos vs. Temperature

Offset Voltage V

os

(mV)

Temperature (°C)

-100 -50 0 50 100 150

-0.5

0

0.5

1

1.5

I

BN

(µA)

-4

0

4

8

12

I

BN

V

os

Short Term Settling Time

V

o

(% Output Step)

Time (ns)

1 10 100 1000

-0.2

-0.1

0

0.1

0.2

Vo = 2Vstep

Long Term Settling Time

V

o

(% Output Step)

Time (s)

1µ10µ100µ1m 10m 100m 1

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

Vo = 2Vstep

7 http://www.national.com

CLC451 Operation

The CLC451 is a current feedback buffer built in an
advanced complementary bipolar process. The CLC451
operates from a single 5V supply or dual ±5V supplies.
Operating from a single 5V supply, the CLC451 has the
following features:

■

Gains of +1, -1, and 2V/V are achievable without
external resistors

■

Provides 100mA of output current while
consuming only 7.5mW of power

■

Offers low -66/-75dBc 2nd and 3rd harmonic
distortion

■

Provides BW > 60MHz and 1MHz distortion
< -55dBc at Vo= 2V

pp

The CLC451 performance is further enhanced in ±5V
supply applications as indicated in the

±5V Electrical

Characteristics

table and

±5V Typical Performance

plots.

If gains other than +1, -1, or +2V/V are required, then the
CLC450 can be used. The CLC450 is a current feedbac k
amplifier with near identical performance and allows for
external feedback and gain setting resistors.

Current Feedback Amplifiers

Some of the key f eatures of current feedback technology are:

■

Independence of AC bandwidth and voltage gain

■

Inherently stable at unity gain

■

Adjustable frequency response with feedbac k resistor

■

High slew rate

■

Fast settling

Current feedback operation can be described using a simple
equation. The voltage gain for a non-inverting or inverting
current feedback amplifier is approximated by Equation 1.

Equation 1

where:

■

Avis the closed loop DC voltage gain

■

Rfis the feedback resistor

■

Z(jω) is the CLC451’s open loop transimpedance
gain

■

is the loop gain

The denominator of Equation 1 is approximately equal to
1 at low frequencies. Near the -3dB corner frequency, the
interaction between Rfand Z(jω) dominates the circuit
performance. The value of the feedback resistor has a
large affect on the circuits performance. Increasing R

f

has the following affects:

■

Decreases loop gain

■

Decreases bandwidth

■

Reduces gain peaking

■

Lowers pulse response overshoot

■

Affects frequency response phase linearity

V
V

A

1

R

Z(j )

o
in

v

f

=

+

ω

ZjRω

()

CLC451 Design Information

Closed Loop Gain Selection

The CLC451 is a current feedback op amp with
Rf = Rg = 1kΩ on chip (in the package). Select from
three closed loop gains without using any external gain or
feedback resistors. Implement gains of +2, +1, and

-1V/V by connecting pins 2 and 3 as described in the
chart below.

The gain accuracy of the CLC451 is excellent and
stable over temperature change. The internal gain
setting resistors, Rfand Rgare diffused silicon resistors
with a process variation of ± 20% and a temperature
coefficient of ˜ 2000ppm/°C. Although their absolute
values change with processing and temperature, their
ratio (Rf/Rg) remains constant. If an external resistor is
used in series with Rg, gain accuracy over temperature
will suffer.

Single Supply Operation (VCC= +5V, VEE= GND)

The specifications given in the

+5V Electrical Character-

istics

table for single supply operation are measured with
a common mode voltage (Vcm) of 2.5V. Vcmis the volt­age around which the inputs are applied and the
output voltages are specified.

Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC451 is typically +0.8V to
+4.2V. The typical output range with RL=100Ω is +1.0V
to +4.0V.

For single supply DC coupled operation, keep input
signal levels above 0.8V DC. For input signals that drop
below 0.8V DC, AC coupling and level shifting the signal
are recommended. The non-inverting and inverting
configurations for both input conditions are illustrated in
the following 2 sections.

DC Coupled Single Supply Operation

Figures 1, 2, and 3 on the following page, show the
recommended configurations for input signals that
remain above 0.8V DC.

Gain

Input Connections

A

v

Non-Inverting (pin3) Inverting (pin2)

-1V/V ground input signal
+1V/V input signal NC (open)
+2V/V input signal ground

http://www.national.com 8

Figure 1: DC Coupled, Av= -1V/V Configuration

Figure 2: DC Coupled, Av= +1V/V Configuration

Figure 3: DC Coupled, Av= +2V/V Configuration

AC Coupled Single Supply Operation

Figures 4, 5, and 6 show possible non-inv erting and invert­ing configurations for input signals that go below 0.8V DC.

Figure 4: AC Coupled, Av= -1V/V Configuration

The input is AC coupled to prevent the need for
level shifting the input signal at the source. The resistive
voltage divider biases the non-inverting input to VCC÷2
= 2.5V (For VCC= +5V).

Figure 5: AC Coupled, Av= +1V/V Configuration

Figure 6: AC Coupled, Av= +2V/V Configuration

Dual Supply Operation

The CLC451 operates on dual supplies as well as single
supplies. The non-inverting and inverting configurations
are shown in Figures 7, 8 and 9.

Figure 7: Dual Supply, Av= -1V/V Configuration

0.1µF

6.8µF

V

o

V

in

R

R

+

V

CC

V

CC

1

CLC451

7
6

8

5

3

4

2

1kΩ

1kΩ

C

C

V V 2.5
Low frequency cutoff

1

2RC

whereR

R

2

RR

o

in

in

C

in

source

=+

=

=>>

π

,

0.1µF

6.8µF

V

o

V

in

R

b

R

t

+

V

cm

V

CC

R

L

V

cm

Note: Rb provides DC bias for the non-inverting input.
R

b

, RL and Rt are tied to Vcm for minimum power

consumption and maximum output swing.

V

cm

1

CLC451

7
6

8

5

3
4

2

1kΩ

1kΩ

Select R

t

to yield desired Rin = Rt||Rg, where Rg = 1kΩ.

0.1µF

6.8µF

V

o

V

in

R

t

+

V

cm

V

CC

R

L

V

cm

Note: Rt and RL are tied to Vcm for minimum power
consumption and maximum output swing.

1

CLC451

7

6

8

5

3
4

2

1kΩ

1kΩ

0.1µF

6.8µF

V

o

V

in

R

t

+

V

cm

V

CC

R

L

V

cm

Note: Rt, RL and Rg are tied to Vcm for minimum power
consumption and maximum output swing.

1

CLC451

7
6

8

5

3

4

2

1kΩ

1kΩ

V

cm

0.1µF

6.8µF

V

o

V

in

R

R

+

V

CC

V

CC

1

CLC451

7
6

8

5

3
4

2

1kΩ

1kΩ

C

C

V V 2.5

Low frequency cutoff

1

2RC

o

in

g

C

=− +

=

π

where Rg = 1kΩ.

,

0.1µF

6.8µF

V

o

V

in

R

R

+

V

CC

V

CC

1

CLC451

7
6

8

5

3
4

2

1kΩ

1kΩ

C

C

C

V 2V 2.5
Low frequency cutoff

1

2RC

whereR

R
2

RR

o

in

in

C

in

source

=+

=

=>>

π

,

0.1µF

6.8µF

V

o

V

in

R

t

+

V

CC

Note: Rb provides DC bias for the
non-inverting input. Select Rt to
yield desired Rin = Rt||1kΩ.

1

CLC451

7
6

8

5

3

4

2

1kΩ

1kΩ

R

b

0.1µF

6.8µF

+

V

EE

9 http://www.national.com

Figure 8: Dual Supply, Av= +1V/V Configuration

Figure 9: Dual Supply, Av= +2V/V Configuration

Bandwidth vs. Output Amplitude

The bandwidth of the CLC451 is at a maximum for
output voltages near 1Vpp. The bandwidth decreases
for smaller and larger output amplitudes. Refer to the

Frequency Response vs.V

o

plots.

Load Termination

The CLC451 can source and sink near equal amounts of
current. For optimum performance, the load should be
tied to Vcm.

Driving Cables and Capacitive Loads

When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC451 will
improve stability and settling performance. The

Frequency Response vs. C

L

and

Recommended R

s

vs. C

L

plots, in the typical performance section, give the
recommended series resistance value for optimum
flatness at various capacitive loads.

Transmission Line Matching

One method for matching the characteristic impedance
(Zo) of a transmission line or cable is to place the
appropriate resistor at the input or output of the amplifier.

Figure 10 shows typical inverting and non-inverting
circuit configurations for matching transmission lines.

Non-inverting gain applications:

■

Connect pin 2 as indicated in the table in the

Closed Loop Gain Selection

section.

■

Make R1, R2, R6, and R7equal to Zo.

■

Use R3to isolate the amplifier from reactive
loading caused by the transmission line,
or by parasitics.

Inverting gain applications:

■

Connect R3directly to ground.

■

Make the resistors R4, R6, and R7equal to Zo.

■

Make R5II Rg= Zo.

The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.
Use C6to match the output transmission line over a
greater frequency range. C6compensates for the increase
of the amplifier’s output impedance with frequency.

Figure 10:Transmission Line Matching

Power Dissipation

Follow these steps to determine the power consumption
of the CLC451:

1. Calculate the quiescent (no-load) power:
P

amp

= ICC(VCC- VEE)

2. Calculate the RMS power at the output stage:
Po= (VCC- V

load

) (I

load

), where V

load

and I

load

are the RMS voltage and current across the
external load.

3. Calculate the total RMS power:
Pt= P

amp

+ P

o

The maximum power that the DIP, SOIC, and SOT
packages can dissipate at a given temperature is
illustrated in Figure 11. The power derating curve for
any CLC451 package can be derived by utilizing the
following equation:

where
T

amb

= Ambient temperature (°C)

θJA= Thermal resistance, from junction to ambient,

for a given package (°C/W)

(175 T

amb

JA

°− )

θ

0.1µF

6.8µF

V

o

V

in

R

t

+

V

CC

1

CLC451

7
6

8

5

3

4

2

1kΩ

1kΩ

0.1µF

6.8µF

+

V

EE

0.1µF

6.8µF

V

o

V

in

R

t

+

V

CC

1

CLC451

7
6

8

5

3

4

2

1kΩ

1kΩ

0.1µF

6.8µF

+

V

EE

Z

0

R

6

V

o

Z

0

R

4

R

5

+

­R

3

Z

0

R

1

R

2

V

1

V

2

+

-

C

6

R

7

1

CLC451

7
6

8

5

3
4

2

1kΩ

1kΩ

http://www.national.com 10

Figure 11: Power Derating Curve

Layout Considerations

A proper printed circuit layout is essential for achieving
high frequency performance. Comlinear provides
evaluation boards for the CLC451 (CLC730013-DIP,
CLC730027-SOIC, CLC730068-SOT) and suggests their
use as a guide for high frequency lay out and as an aid f or
device testing and characterization.

General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:

■

Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.

■

Place the 6.8µF capacitors within 0.75 inches
of the power pins.

■

Place the 0.1µF capacitors less than 0.1 inches
from the power pins.

■

Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance.

■

Minimize all trace lengths to reduce series
inductances.

■

Use flush-mount printed circuit board pins for
prototyping, never use high profile DIP sockets.

Evaluation Board Information

Data sheets are available for the CLC730013/
CLC730027 and CLC730068 evaluation boards. The
evaluation board data sheets provide:

■

Evaluation board schematics

■

Evaluation board lay outs

■

General information about the boards

The CLC730013/CLC730027 data sheet also contains
tables of recommended components to evaluate several
of Comlinear’s high speed amplifiers. This table for the
CLC451 is illustrated below. Refer to the evaluation
board data sheet for schematics and further information.

Components Needed to Evaluate the
CLC451 on the Evaluation Board:

■

Rin, R

out

- Typically 50Ω (Refer to the

Basic

Operation

section of the evaluation board data

sheet for details)

■

Rt- Optional resistor for inverting gain configura­tions (Select Rtto yield desired input impedance
= Rg || Rt)

■

C1, C2- 0.1µF ceramic capacitors

■

C3, C4- 6.8µF tantalum capacitors

Components not used:

■

C5, C6, C7, C

8

■

R1thru R

8

The evaluation boards are designed to accommodate
dual supplies. The boards can be modified to provide
single supply operation. For best performance; 1) do
not connect the unused supply, 2) ground the unused
supply pin.

Special Evaluation Board
Considerations for the CLC451

To optimize off-isolation of the CLC451, cut the Rftrace on
both the CLC730013 and the CLC730027 evaluation
boards. This cut minimizes capacitive feedthrough
between the input and the output. Figure 12 shows where
to cut both evaluation boards for improved off-isolation.

Figure 12: Evaluation Board Changes

SPICE Models

SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for
Comlinear’s monolithic amplifiers that:

■

Support Berkeley SPICE 2G and its many derivatives

■

Reproduce typical DC, AC, Transient, and Noise
performance

■

Support room temperature simulations

The

readme

file that accompanies the diskette lists
released models, and provides a list of modeled parame­ters. The application note OA-18, Simulation SPICE
Models for Comlinear’s Op Amps, contains schematics
and a reproduction of the readme file.

Single Supply Cable Driver

The typical application shown on the front page shows
the CLC451 driving 10m of 75Ω coaxial cable. The
CLC451 is set for a gain of +2V/V to compensate for the
divide-by-two voltage drop at Vo.

Application Circuits

730013
REV C

Cut trace here

R6R3R1

R7

R8

R5

C3

R2

R4

C4

ROUT

OUT

C6C2C1

C5

C8

IN

RIN

RG

RF

C7

-Vcc+V

cc

GND

Comlinear

A National Semiconductor Company

[phone]

+

+

Cut trace here

Power (W)

Ambient Temperature (°C)

0

0.2

0.4

0.6

0.8

1.0

-40 -20 0 20 40 60 80 100 120 180

AJP

AJE

SOT

140 160

11 http://www.national.com

Twisted Pair Driver

The high output current and low distortion, of the
CLC451, make it well suited for driving transformers.
Figure 13 illustrates a typical twisted pair driver utilizing
the CLC451 and a transformer. The transformer
provides the signal and its inversion for the twisted pair.

Figure 13:Twisted Pair Driver

To match the line’s characteristic impedance (Zo) set:

■

RL= Z

o

■

Rm= R

eq

Where Reqis the transformed value of the load imped­ance, (RL), and is approximated by:

Select the transformer so that it loads the line with a
value close to Zo, over the desired frequency range. The
output impedance, Ro, of the CLC451 varies with
frequency and can also affect the return loss.The return
loss, shown below, takes into account an ideal
transformer and the value of Ro.

The load current (IL) and voltage (Vo) are related to the
CLC451’s maximum output voltage and current by:

From the above current relationship, it is obvious that an
amplifier with high output drive capability is required.

R

R

n

eq

L

2

=

Return Loss(dB) 20log n

R
Z

10

2

o
o

≈− ⋅

VnV
I

I

n

o max

L

max

≤⋅

≤

+

V

o

-

R

m

R

L

Z

o

UTP

I

L

R

eq

1:n

V = Av V

in

V

n
4

AV

v

in

=

V

-n
4

AV

v

in

=

V

1n

2

AV

ov

in

=

V

in

R

t

1

CLC451

7
6

8

5

3
4

2

1kΩ

1kΩ

0.1µF

6.8µF

+

V

EE

Av = 2

CLC451, Single Supply, Low-Power,

High Output, Programmable Buffer

http://www.national.com 12

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2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
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