Datasheet CLC449MDC, CLC449AMC, CLC449AJP, CLC449AJE-TR13, CLC449AJE Datasheet (NSC)

Features

■

1.1GHz small-signal bandwidth (Av= +2)

■

2500V/µs slew rate

■

0.03%, 0.02° DG, D

Φ

■

6ns settling time to 0.2%

■

3rd order intercept, 30dBm @ 70MHz

■

Dual ±5V or single 10V supply

■

High output current: 90mA

■

2.5dB noise figure

Applications

■

High performance RGB video

■

RF/IF amplifier

■

Instrumentation

■

Medical electronics

■

Active filters

■

High-speed A/D driver

■

High-speed D/A buffer

Typical Application

120MSPS High-Speed Flash ADC Driver

Pinout

DIP & SOIC

General Description

The CLC449 is an ultra-high-speed monolithic op amp, with a typ­ical -3dB bandwidth of 1.1GHz at a gain of +2. This wideband op
amp supports rise and fall times less than 1ns, settling time of 6ns
(to 0.2%) and slew rate of 2500V/µs.The CLC449 achieves 2nd
harmonic distortion of -68dBc at 5MHz at a low supply current of
only 12mA. These performance advantages have been achieved
through improvements in National’s proven current feedback
topology combined with a high-speed complementary bipolar
process.

The DC to 1.2GHz bandwidth of the CLC449 is suitable for many IF
and RF applications as a versatile op amp building bloc k for replace­ment of AC coupled discrete designs. Operational amplifier
functions such as active filters, gain blocks, differentiation, addition,
subtraction and other signal conditioning functions take full
advantage of the CLC449’s unity-gain stable closed-loop
performance.

The CLC449 performance provides greater headroom for lower
frequency applications such as component video, high-resolution
workstation graphics, and LCD displays. The amplifier’s 0.1dB
gain flatness to beyond 200MHz, plus 0.8ns 2V rise and fall times
are ideal for improved time domain performance. In
addition, the 0.03%/0.02° differential gain/phase performance
allows system flexibility for handling standard NTSC and PAL
signals.

In applications using high-speed flash A/D and D/A converters, the
CLC449 provides the necessary wide bandwidth (1.1GHz), settling
(6ns to 0.2%) and low distortion into 50Ω loads to improve SFDR.

Frequency Response (Av = +2V/V)

CLC449

1.1GHz Ultra-Wideband Monolithic Op Amp

N

June 1999

CLC449

1.1GHz Ultra-Wideband Monolithic Op Amp

© 1999 National Semiconductor Corporation http://www.national.com

Printed in the U.S.A.

http://www.national.com 2

PARAMETERS CONDITIONS TYP MIN/MAX RATINGS UNITS NOTES

CLC449 +25° +25° 0° to +70° -40° to +85°

FREQUENCY DOMAIN RESPONSE

-3dB bandwidth
small signal <0.2V

pp

1100 MHz

large signal <2V

pp

500 380 380 360 MHz

±0.1 dB bandwidth <2V

pp

200 MHz

gain flatness

peaking DC to 200MHz 0 dB
rolloff DC to 200MHz 0.1 0.5 0.5 0.5 dB

linear phase deviation <200MHz 0.8 deg
differential gain 4.43MHz, R

L

=150Ω 0.03 0.05 0.05 0.05 %

differential phase 4.43MHz, R

L

=150Ω 0.02 0.02 0.05 0.05 deg

TIME DOMAIN RESPONSE

rise and fall time 2V step 0.8 1.1 1.1 1.1 ns
settling time to 0.2% 2V step 6 ns
settling time to 0.1% 2V step 11 ns
overshoot 2V step 10 18 18 18 %
slew rate 4V step 2500 2000 2000 2000 V/µs

DISTORTION AND NOISE RESPONSE

2nd harmonic distortion 2V

pp

, 5MHz -63 59 59 59 dBc

2V

pp

, 20MHz -52 -48 -48 -48 dBc

2V

pp

, 50MHz -44 40 40 40 dBc

3rd harmonic distortion 2V

pp

, 5MHz -84 77 75 75 dBc

2V

pp

, 20MHz -73 -66 -64 -64 dBc

2V

pp

, 50MHz -62 55 53 53 dBc
3rd order intercept 70MHz 30 dBm
1dB gain compression @ 50MHz 16 dBm
equivalent input noise

non-inverting voltage 1MHz 2.2 2.9 nV/√Hz
inverting current 1MHz 15 20.0 pA/√Hz
non-inverting current 1MHz 3 5.0 pA/√Hz

STATIC DC PERFORMANCE

input offset voltage 3 7 9 9 mV A

average drift 25 µV/°C

input bias current non-inverting 6 30 45 60 µAA

average drift 50 nA/°C

input bias current inverting 2 20 25 40 µAA

average drift 25 nA/°C
power supply rejection ratio DC 48 43 41 41 dB A
common-mode rejection ratio DC 47 44 45 46 dB
supply current R

L

= ∞ 12 13.5 14 14 mA A

MISCELLANEOUS PERFORMANCE

input resistance non-inverting 400 200 200 150 kΩ
input capacitance non-inverting 1.3 pF
output resistance closed loop 0.1 0.15 0.15 0.25 Ω
output voltage range R

L

= ∞ 3.3 3.1 3.1 3.1 V

R

L

=100Ω 2.9 2.8 2.8 2.8 V
input voltage range common-mode 2.4 2.2 2.1 1.9 V
output current 80 60 50 40 mA

CLC449 Electrical Characteristics

(Av= +2, Rf= 250

ΩΩ,,

Vcc= ±5V, RL= 100ΩΩ; unless specified)

Absolute Maximum Ratings

V

oc

±6V

I

out

is short circuit protected to ground

common-mode input voltage ±V

cc

maximum junction temperature +150°C
operating temperature range

AJ -40°C to +85°C
storage temperature range -65°C to +150°C
lead temperature (soldering 10 sec) +300°C
ESD (human body model) 500V

Notes

A) J-level:spec is 100% tested at +25°C.

Pac kage Thermal Resistance

Package θ

JC

θ

JA

Plastic (AJP) 90°C/W 105°C/W
Surface Mount (AJE) 110°C/W 130°C/W

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.

3 http://www.national.com

10k 100k 1M 10M 100M

Magnitude (3dB/div)

20 log|Z| (dBΩ)

Distortion (dBc)

Noise Voltage (nV/√Hz), Current (pA/√Hz)

Frequency (Hz)

PSRR/CMRR (dB)

Magnitude (3dB/div)

Phase (deg)

Distortion (dBc)

Phase

(deg)

Distortion (dBc)

-3dB Bandwidth (MHz)

R

out

(ohms)

Time (1ns/div)Time (1ns/div)

D.G. (%), D.P. (deg)

Magnitude (0.1dB/div)

Intercept Point (dBm)

Phase (deg)

Magnitude (3dB/div)

Phase (deg) Phase (1deg/div)

PSRR

Po = 10dBm

100M0.1M 1M 10M

0.1k

1k 10k 100k 1M 10M 100M

0.1M 1M 10M 100M

180
160

CLC449 Typical Performance Characteristics

(TA= 25°C,Vcc= + 5V,Rf= 250Ω,Av= +2, RL= 100Ω)

http://www.national.com 4

CLC449 Typical Performance Characteristics

(TA= 25°C,Vcc= + 5V,Rf= 250Ω,Av= +2, RL= 100Ω)

CLC449 OPERATION

Magnitude (1dB/div)

Input Offset Voltage, V

IO

(mV)

Input Bias Current, I

BI

, I

BN

(µA)

Settling Time (ns)

R

s

(ohms)

VSWR

Frequency (Hz)

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

Input VSWR

Non-Inverting

Inverting

0 100M 200M 300M 400M 500M

VSWR

Frequency (Hz)

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

Uncompensated

Compensated

0 100M 200M 300M 400M 500M

|S

12

| (dB)

Frequency (Hz)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100
0 100M 200M 300M 400M 500M

Output VSWR Reverse Isolation (S12)

Gain Compression

CLC449 Extended Application Information

The following design and application topics will supply
you with:

•

A comprehensive set of design parameters and
design parameter adjustment techniques.

•

A set of formulas that support design parameter
change prediction.

•

A series of common applications that the CLC449
supports.

•

A set of easy to use design guidelines for the
CLC449.

Additional design applications are possible with the
CLC449. If you have application questions, call 1-800-272­9959 in the U.S.to contact a technical staff member.

DC Gain (Non-Inverting)

The non-inverting DC voltage gain for the configuration
shown in Figure 1 is:

Figure 1: Non-Inver ting Gain

The normalized gain plots in the

Typical Performance

Characteristics

section show different feedback resistors,
Rf, for different gains. These values of Rfare recom­mended for obtaining the highest bandwidth with minimal
peaking. The resistor Rtin Figure 1 provides DC bias for
the non-inverting input.

For Av≤ 5, calculate the recommended Rfas follows:
Rf≅ 340 - A

v

•

Ri, where Ri= 45Ω.For Av> 5, the

minimum recommended feedback resistor is Rf = 100Ω.

Select Rgto set the DC gain:

Accuracy of DC gain is usually limited by the tolerance of
the external resistors Rfand Rg.

DC Gain (Unity Gain Buffer)

Unity gain buffers are easily designed with a current­feedback amplifier as long as the recommended feed­back resistor Rf= 402Ω is used and Rg= ∞, i.e. open.
Parasitic capacitance at the in verting node may require a
slight increase of the feedback resistor Rfto maintain a
flat frequency response.

DC Gain (Inverting)

The inverting DC voltage gain for the configur ation shown
in Figure 2 is:

A1

R

R

V

f

g

=+

+

-

CLC449

R

f

0.1µF 6.8µF
V

o

V

in

V

cc

R

g

R

t

3

2

4

7

6

+

0.1µF 6.8µF

V

ee

+

R

R

A1

g

f

v

=

−

A

R

R

v

f

g

=−

5 http://www.national.com

Figure 2: Inver ting Gain

The normalized gain plots in the

Typical Performance

Characteristics

section show different feedback resistors,
Rf, for different gains .These values of Rfare recommended
for obtaining the highest bandwidth with minimal peaking.
The resistor Rtin Figure 2 provides DC bias for the non­inverting input.

For |Av| ≤ 4, calculate the recommended Rfas follows:
Rf ≅ 295 - |Av| •Ri, where Ri= 45Ω. For |Av| > 4, the
minimum recommended feedback resistor is Rf = 100 Ω.

Select Rgto set the DC gain:
At large gains, Rgbecomes small and will load the

previous stage. This situation is resolved by driving
Rgwith a low impedance buffer like the CLC111,
or increasing Rfand Rg (see the

Bandwidth (Small

Signal)

sub-section for the tradeoffs).

Accurate DC gain is usually limited by the tolerance of
the external resistors Rfand Rg.

Bandwidth (Small Signal)

The CLC449 current-feedback amplifier bandwidth is a
function of the feedback resistor (Rf), not of the DC volt­age gain (Av). The bandwidth is approximately
proportional to 1/Rf. As a rule, if Rfdoubles, the band­width is cut in half. Other AC specifications will also be
degraded.

Decreasing Rffrom the recommended
value increases peaking and for very small values of
Rfoscillation will occur.

With an inverting amplifier design, peaking is sometimes
observed. This is often the result of layout parasitics
caused by inadequate ground planes or long traces. If
this is observed, placing a 50 to 200Ω resistor between
the non-inverting pin and ground will usually reduce the
peaking.

Bandwidth (Minimum Slew Rate)

Slew rate influences the bandwidth for large signal
sinusoids. To determine an approximate value of slew
rate, necessary to support large sinusoids use the
following equation:

SR ≅ 5 •f •V

peak

V

peak

is the peak output sinusoidal voltage, f is the
frequency of the sinusoid.
The slew rate of the CLC449 in inverting gains is always

higher than in non-inverting gains.

DC Design (Level Shifting)

Figure 3 shows a DC level shifting circuit for inverting
gain configurations. V

ref

produces a DC output level shift

of

which is independent of the DC output produced by Vin.

Figure 3: Level Shifting Circuit

DC Design (Single Supply)

Figure 4 is a typical single-supply circuit. Resistors R

1

and R2form a voltage divider that sets the non-inverting
input DC voltage. This circuit has a DC gain of 1. The
coupling capacitor C1isolates the DC bias point from the
previous stage. Both capacitors make a high pass
response; the high frequency gain is determined by R

f

and Rg.

Figure 4: Single Supply Circuit

The complete gain equation for the circuit in Figure 4 is:

where s = jω, τ1= (R1|| R2) •C1, and τ2= RgC2.

DC Design (DC Offsets)

The DC offset model shown in Figure 5 is used to
calculate the output offset voltage. The equation for out­put offset voltage is:

The current offset terms, IBNand IBI,

do not track each

other

. The specifications are stated in terms of

magnitude only. Therefore, the terms Vos, IBN, and I

BI

may have either positive or negative polarity. Matching
the equivalent resistance seen at both input pins does
not reduce the output offset voltage.

+

-

CLC449

R

f

0.1µF

6.8µF

V

o

V

in

V

cc

0.1µF

6.8µF

V

ee

R

g

R

t

3

2

4

7

6

+

+

R

R

|A |

g

f
v

=

-V

R

R

ref

f

ref

⋅

V

in

R

eq2

+

-

CLC449

R

f

V

o

V

ref

R

ref

R

eq1

+

-

CLC449

R

f

V

o

V

in

V

cc

R

g

R

2

R

1

V

cc

C

1

C

2

VVIR1

R

R

IR

oos

BN

eq1

f

eq2

BI

f

=− + ⋅

()

⋅+











+⋅

()

V
Vs1s

1s 1

R

R

1s

o

in

1

1

2

f

g

2

=

+

⋅

+⋅+











+

τ

τ

τ

τ

http://www.national.com 6

Figure 5: DC Offset Model

DC Design (Output Loading)

RL, Rf, and Rgload the op amp output. The equivalent
closed-loop load impedance seen by the output in Figure
5 is:

•

R

L_eq

= RL|| (Rf+ R

eq2

), non-inverting gain

•

R

L_eq

= RL|| Rf, inverting gain

R

L_eq

needs to be kept large enough so that the
minimum available output current can produce the
required output voltage swing.

Capacitive Loads

Capacitive loads, such as found in A/D converters,
require a series resistor (Rs) in the output to improve set­tling performance. The

Rsand Settling Time vs. C

L

plot

in the

Typical Performance Characteristics

section

provides the information for selecting this resistor.
Also, use a series resistor to reduce the effects of

reactive loads on amplifier loop dynamics. For instance,
driving coaxial cables without an output series resistor
may cause peaking or oscillation.

Transmission Line Matching

One method for matching the characteristic impedance of
a transmission line is to place the appropriate resistor at
the input or output of the amplifier. Figure 6 shows the
typical circuit configurations for matching transmission
lines.

Figure 6:Transmission Line Matching

In non-inverting gain applications, Rgis connected directly
to ground. The resistors R1, R2, R6, and R

7

are equal to the characteristic impedance, Zo, of the
transmission line or cable.

In inverting gain applications, R3is connected directly to
ground. The resistors R4, R6, and R7are equal
to Zo. The parallel combination of R5and Rgis also equal
to Zo.

The input and output matching resistors attenuate the
signal by a factor of 2, therefore additional gain is needed.

Matching the output transmission line over greater
frequency ranges is accomplished by placing C6in
parallel with R6, reducing the output impedance to
compensate for the inter nal increase of the op-amp’s out­put impedance with frequency.

Thermal Design

To calculate the power dissipation for the CLC449,
follow these steps:

•

Calculate the no-load op amp power:
P

amp

= I

cc

•

(Vcc– Vee)

•

Calculate the output stage’s RMS power:
Po= (Vcc– V

load

) •I

load

where V

load

and I

load

are the RMS voltage and

current across the external load.

•

Calculate the total op amp RMS power:
Pt= P

amp

+ P

o

To calculate the maximum allowable ambient tempera­ture, solve the following equation: T

amb

= 175 – P

t

•

θJA,

where θJAis the thermal resistance from junction to
ambient in °C/W and T

amb

is in °C. Thermal resistance

for the various packages are found in the

Package

Thermal Resistance

section.

Dynamic Range (Input /Output Protection)

Input ESD diodes are present on all connected pins for
protection from static voltage damage. For a signal that
may exceed the supply voltages, we recommend using
diode clamps at the amplifier’s input to limit the signals to
less than the supply voltages.

Dynamic Range (Input /Output Levels)

The

Electrical Characteristics

section contains the
Common-Mode Input Range and Output Voltage
Range; these voltage ranges scale with the supplies.
Output Current is also specified in the

Electrical

Characteristics

section.

Unity gain applications are limited by the Common-Mode
Input Range. At greater non-inverting gains, the Output
Voltage Range becomes the limiting factor. Inverting gain
applications are limited by the Output Voltage Range.

For transimpedance or inverting gain applications, the
current (I

inv

) injected at the inverting input pin of the op

amp needs to be:

where V

max

is the Output Voltage Range.

The voltage ranges discussed above are achieved as
long as the equivalent output load is large enough so that
the output current can produce the required output
voltage swing. See the

DC Design (Output Loading)

sub-section for details.

Dynamic Range (Intermods)

For RF applications, the CLC449 specifies a third
order intercept of 30dBm at 70MHz and Po = 10dBm.

R

eq1

R

f

+

-

R

eq2

CLC449

I

BI

I

BN

V

os

V

o

R

L

+

-

+

-

CLC449

R

3

Z

0

R

6

V

o

Z

0

R

1

R

2

+

­R

g

Z

0

R

4

R

5

V

1

V

2

+

-

R

f

C

6

R

7

|I |

V

R

inv

max

f

≤

7 http://www.national.com

A

2-Tone , 3rd Order IMD Intercept

plot is found in the

Typical Performance Characteristics

section. The
output power level is taken at the load. Third-order
harmonic distortion is calculated with the formula:

HD3rd= 2 •(IP3o– Po)

where:

•

IP3o= third-order output intercept, dBm at
the load.

•

Po= output power level, dBm at the load.

•

HD3rd= third-order distortion from the
fundamental, -dBc.

•

dBm is the power in mW, at the load,
expressed in dB.

Realized third-order output distortion is highly
dependent upon the external circuit. Some of the
common external circuit choices that improve 3rdorder
distortion are:

•

short and equal return paths from the load
to the supplies.

•

de-coupling capacitors of the correct value.

•

higher load resistance.

•

a lower ratio of the output swing to the power
supply voltage.

Dynamic Range (Noise)

In RF applications, noise is frequently specified as Noise
Figure (NF). Figure 7 plots NF for the CLC449 at a gain
of 10, with a feedback resistor Rfof 100Ω, and with no
input matching resistor. The minimum Noise Figure
(2.5dB) for these conditions occurs when the source
resistance equals 700Ω.

Figure 7. Noise Figure Plot

Figure 8: CLC449 Noise Model

The CLC449 noise model in Figure 8 is used to develop
the equation below.

The equation for Noise Figure (NF) is:

where:

•

Rsis the source resistance at the non­inverting input.

•

There is no matching resistor from the input
to ground.

•

eni, ibn, ibiare the voltage and current noise
density terms (see in the

Distortion and

Noise Response

sub-section of the

Electrical

Characteristics

section).

•

4kT = 16 x 10

-21

J, T = 290°K.

•

Rfis the feedback resistor and Rgis the gain
setting resistor.

Printed Circuit Board Layout and Measurement

High Frequency op amp performance is strongly depen­dent on proper layout, proper resistive termination and
adequate power supply decoupling. The most impor tant
layout points to follow are:

•

Use a ground plane.

•

Bypass power supply pins with monolithic
capacitors of about 0.1µF value and place
the capacitors less than 0.1” (3mm) from the pin.

•

Bypass power supply pins with 6.8µF tantalum
capacitors for large signal current swings or
improved power supply noise rejection.

•

Minimize trace and lead lengths for components
between the inverting and output pins.

•

Remove ground plane underneath the
amplifier package and within 0.1” (3mm) of all
input/output pads.

•

If parts must be socketed, always use
flush-mount socket pins instead of high profile
sockets.

Evaluation boards are av ailable f or proto-typing and mea­surements. Additional layout information is
available in the evaluation board literature.

+

-

CLC449

e

n

V

o

R

s

i

bn

+

-

V

s

R

f

R

g

*

*

i

bi

*

NF 10LOG

e i R 4 TR i R ||R 4 T R ||R

4TR

ni

bn

s

2

s

bi

f

g

2

f

g

s

2

=

+

()

++⋅

()

+⋅















kk

k

Noise Figure (dB)

Source Resistance (Ω)

20

15

0

10

100

10000

10

5

1000

Low Noise Composite Amp With Input Matching

The composite circuit shown in Figure 9 eliminates the
need for a matching resistor to ground at the input. By
connecting two amplifiers in series, the first non-invert­ing and the second inverting, an overall inverting gain is
realized. The feedback resistor (Rf) connected from the
output of the second amplifier to the non-inverting input
of the first amplifier closes the loop, and generates a set
input resistance (Rin) that can be matched to Rs. This
resistor generates less noise than a matching resistor to
ground at the input.

Figure 9: Composite Amplifier

Input resistance and DC voltage gain of the amplifier are:

Match the source resistance by setting:
Noise voltage produced by Rf, referred to the source Vs, is:

The noise of a simple input matching resistor connected
to ground can be calculated by setting G to 0 in this
equation. Thus, this circuit reduces the thermal noise
produced by the matching resistor by a factor of (1+G).

Rectifier Circuit

Wide bandwidth rectifier circuits have many applications.
Figure 10 shows a 200MHz wideband full-wave rectifier
circuit using a CLC449 and CLC522 amplifier. Schottky or
PIN diodes are used for D1 and D2. They produce an
active half-wave rectifier whose signals are taken at the
feedback diode connection. The CLC522 takes the
difference of the two half-wave rectified signal, producing
a full-wave rectifier. The CLC522 is used at a gain of 5 to

achieve high differential bandwidth. For best high
frequency performance, maintain low parasitic capaci­tance from the diodes D1 and D2 to ground, and from the
input of the CLC522, to ground.

Figure 10: Full-Wave Rectifier

Flash A/D Application

The Typical Application circuit on the front page shows
the CLC449 driving a flash A/D. Flash A/D’s require fast
settling, low distortion, low noise and wide bandwidth to
achieve high Effective Number of Bits and Spurious Free
Dynamic Range (SFDR).

This circuit connects a CLC449 to a TDA8716, 8-bit,
120MHz Flash Converter. The input capacitance for
this converter is typically 13pF plus layout capacitance.
From the

Rsand Settling Time vs. C

L

plot in the

Typical Performance Characteristics

section, select
a series resistor (Rs) of 55Ω. Place Rsin series with
the output of the CLC449 to achieve settling to 0.1% in
approximately 11ns.

Keep the amplifier noise seen at the A/D input at least
3dB lower than the A/D’s noise, to avoid degrading A/D
noise performance.

CLC449 APPLICATIONS

+

-

CLC449

R

f

V

o

R

g2

-

+

20Ω

CLC449

R

f2

R

f1

R

g1

R

in

V

s

R

s

+

-

R

R

1G

,whereG 1

R

R

R

R

V
V

G

R

RR

in

ff1

g1

f2

g2

o
s

in

in

s

=

+

=+











⋅











=− ⋅

+











RR

in

s

=

e4TR

R

R1G

R

2

s

s

in

f

=⋅

⋅+

()











k

+

-

CLC449

V

o

+

-

500Ω

CLC522

250Ω

250Ω

3

250Ω

D

1

D

2

R

g

162Ω

R

1

50Ω

R

2

50Ω

3
4

5
6

2

R

f

800Ω

R

o

50Ω

20Ω

12

9

10

V

g

R

in

50Ω

V

in

2

6

Ordering Information

Model Temperature Range Description

CLC449AJP -40°C to +85°C 8-pin PDIP
CLC449AJE -40°C to +85°C 8-pin SOIC
CLC449AMC -55°C to +125°C dice, MIL-STD-883

Contact factory for other packages and DESC SMD number.

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Reliability Information

Transistor count 26

9 http://www.national.com

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11 http://www.national.com

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CLC449

1.1GHz Ultra-Wideband Monolithic Op Amp

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National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of
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1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perfor m, when proper ly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.

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