Datasheet CH7203-V Datasheet (Chrontel Inc)

MPEG to TV Encoder with 16-bit Input

CH7203

Features

• Outputs to NTSC, PAL (B, D, G, H, I) a n d PAL -60

• 16-bit YCrCb (4:2:2) input format

• S i m ul t aneou s compo s ite/S- vi deo ou tp u ts

• Triple 9-bit video DACs

• 27 MHz DAC operating frequency eliminates
the need for 1/sinc(x) correction filte r

• Low-jitte r phase-lock ed loop circuitry oper ates
us ing a low-cos t 14.31818 MHz crystal

• 40.5 or 33.9 MH z video decoder cloc k output

• 16.934 or 11.289 MHz audio decoder clock output

• 13.5 MH z and 27 MH z video pixel clock outputs

• Optimized luminance an d chrominance internal
fil ters for NTSC and PAL

• HSYNC* and VSYNC* outputs for
ma s ter mod e operati on

• Sleep mode

• CMOS technology in 44-pin PLCC

• 5V single-supply operation

Description

The CH7203 video encoder integrates a dual PLL clock
generat or and a digit al NTSC/ PA L v ideo encoder. B y
generating all essential clock signals for MPEG
playback, and convertin g dig ital video inpu ts to either
NTSC or PA L vi deo si g na l s , t he C H 72 03 is an e s s ent i al
component of any low-cost solution for video-CD
playback machines.

Th e C H72 03 d ua l PLL clo ck sy nth e siz er ge ne rat es a ll
clocks and timing signals from a 14.31818 MHz
reference crystal (see application note 19 “Tuning
Clock Outputs” for selection and tuning of the 14.31818
MHz crystal). The CH7203 generates a 40.5 or 33.9
MHz video decoder clock, 13.5 MHz and 27 MHz
video pixel cl oc ks, and a 16.934 or 11.289 MHz a udio
decod er clock. Timing signals from the PLLs are used
to generate the horizontal and vertical sync signals
which enable operating the CH7203 in master mode.

The fully digital video encoder is pin-programmable to
generate either a 525-line NTSC or a 625-line PAL
compatible video signal. It also features a logic
selectable sleep mode which turns the encoder off while
leaving both PLL’s running.

RSETAVDDVDD

IREF

9

DAC

9

Σ

ΣX

DAC

9

DAC

Y

CVB S

C

X

Y[7:0],

C[7:0]

HSYNC*
VSYNC*

PCLK

2XPCLK

DCLK

ACLK

MOD0 MOD1 FS

BLAN KING

H,V SYNC

GEN ERATO R

16

INTERFACE

STAT E

MACHINE

1/2

PLL1

LINEAR

INTERPOLATO R

OSCPLL2

XI XO/FIN

CRSCRSEN*

Y

FILTER

U

FILTER

V

FILTER

M
U
X

M
U
X

M
U
X

BLANKING

COLO R-B URST

CO NT RO L

SIN + COSINE

GENERATOR

AGNDGN D

Figure 1: Functional Block Diagram

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CRSEN*

FS

MOD1

CRS

C[7]
C[6]
C[5]
C[4]
C[3]
C[2]
C[1]

7
8
9
10
11
12
13
14
15
16
17

AVDD

6

AGND

XI

5

4

VDD

XO/FIN

3

2

CHRONTEL

CH7203

ACLK

1

GND

44

CH7203

2XPCLK

VDD

DCLK

GND

43

42

41

40

39

PCLK

38

MOD0

37

VSYNC*

36

VDD

35

HSYNC*

34

GND

33

GND

32

Y

31

CVBS

30

C

29

AVDD

18

19

20

21

22

C[0]

Y[7]

Y[6]

Y[5]

Y[4]

23

Y[3]

24

Y[2]

25

Y[1]

26

Y[0]

27

AGND

Figure 2: CH7203 Pinout Diagram

28

RSET

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Table 1. Pin Descriptions

Pin Type Symbol Description

1 Out ACLK

2, 36, 42 Power VD D

3InXO/FIN

4In XI

5, 27 Power AGND

6,29 Power AVD D

7 In CRSEN*

8In FS

9InMOD1

10 In CRS

11 – 18 In C[7:0]

Au dio D e c oder Clock O ut put

16.934 MHz or 11.289 MHz clock output (selectable by FS) for
MPEG audio decoder operation. The output swing is 5V.

Digital Supply Voltage

These pins supply the 5V power to the digital section of the
CH7203.

Crystal Output or External F

A 14.31818 MHz (± 50 ppm) parallel resonance crystal may be
attached between XO/FIN and XI. An external CMOS compatible
clock can be connected to XO/FIN as an alternative.

Crystal Inp ut

A 14.31818 MHz (± 50 ppm) parallel resonance crystal should be
attached between XI and XO/FIN. However, if an external CMOS
clock is attached to XO/FIN, XI should be connected to ground.

Analog ground

These pins provide the ground reference for the analog section of
the CH7203. These pins MUST be connected to the system
ground to prevent latchup.

Analog Supply Voltage

These pins supply the 5V power to the analog section of the
CH7203.

Cr Select Enable.

CRSEN*=0, Cr, Cb data sequence is specified by the CRS pin.
CRSEN*=1, C r, C b data sequence is s pecified by t he CH7203’s

internal default condition: Horizontal count = even, data is Cb;
data is Cr otherwise. State of C RS is ignored when CRSEN*=1.

Figure 6

See

Frequency Select.

FS = 1 (default), then DCLK = 40.5 MHz, ACLK = 16.934 MHz
FS = 0, then DCLK = 33.9 MHz, ACLK = 11.289 MHz

Mo de bit 1 -

This input w orks in conjunction with the MOD 0 input to select
NTSC, PAL, or Sleep mode functions. R efer to

Encoder Modes,” on page 6
Cr Select.

When CRSEN*=0, CRS specifies the CrCb data sequence. CRS
is an alternating signal. CRS=1 indicates that C[7:0] carry the Cr
data. C[7:0] carry the Cb data otherwise. See

Video Inpu t

These pins accept the “CrCb” data of the YCrCb (4:2:2) digital
video format. The Cb & Cr data appear alternately. The sequence
of t he C b, Cr dat a is eit her predef ined by t he int ernal horiz ontal
counter (even = Cb, odd = Cr) or as specified by pin CRS (data is
Cr for CRS=1 and Cb otherwise. For more details, please refer to
the timing dia gram shown in

Cb & Cr have a nominal range of 16–240, w ith 128 equal to zero.

1

Internally pulled-up.

on page 7.

Internally pulled-up

Internally pulled-up

In put

REF

for details.

Figure 6

1

Figure 7

on page 7.

CH7203

Table 3 , “V ideo

on page 8.

Note: 1.

required only if the crystal oscillation frequency cannot be controlled to the required accuracy. The capacitance value for the tuning capac­itor should be obtained from the crystal manufacturer. For further information, request a copy of

Outputs.

Please refer to crystal manufacturer specifications for proper load capacitances. The optional variable tuning capacitor is

Applica tion Note AN-19, “Tuning Cloc k

”

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Table 2. Pin Descriptions (continued)

CH7203

Pin

19-26 In Y[7:0]

28 In RSET

30 Out C

31 Out CVBS

32 Out Y

33, 34, 40, 44 Power GND

35 Out HSYNC*

37 Out VSYNC*

38 In MOD0

39 Out PCLK

41 Out DCLK

43 Out 2XPCLK

Type

Symbol Description

Video Inpu t

These pins accept the “Y” data of the YCrCb (4:2:2) digital video
format. For more details, please refer to the timing diagram
shown in

Reference Resistor

A 360 Ω resistor with s hort and w ide t races s hould be attached
between RSET and ground. No other connections should be
made to this pin.

C hrominanc e O ut put

A 75 Ω termination resistor with short traces should be attached
between C and ground for optimum perf ormance.

C om posit e O ut put

A 75 Ω termination resistor with short traces should be attached
between CVBS and ground for optimum performance.

Luminance Output

A 75 Ω termination resistor with short traces should be attached
between Y and ground for optimum perform ance.

Digital Ground

These pins provide the ground reference for the digital section of
the CH7203. These pins MUST be connected to the system
ground through

Ho rizo nta l S y nc O ut put

The horizontal sync output is generated by the CH7203 for master
mode operation. HSYNC* is an act ive low signal with a 5V out put
swing. For additional information, please refer to the timing
diagrams shown in

Vertical Sync Ou tput

The vertical sync output is generated by the CH 7203 for master
mode operation. VSYN C* is an act ive low signal with a 5V output
swing. For additional information, please refer to the timing
diagrams shown in

Mo de bit 0

This input w orks in conjunction with the MOD 1 input to select
NTSC, PAL, or Sleep Mode functions. R efer to

Encoder Modes,” on page 6
Video Pixel Clock Output

13.5 MHz clock output. The output s wing is 5V.

MPE G De coder Clock O ut put

40.5 MHz or 33.9 MHz clock output (selectable by FS). The output
swing is 5V.

Do uble P ixe l Clock O ut put

27 MHz cloc k output. The output swing is 5V.

Figure 7

on page 8. Y has a nominal range of 16-235.

independent

Figures5

Figures5

- internally pulled-up

ground vias.

and 6 on page 7.

and 7 on page 7 and 8.

Table 3 , “V ideo

for details.

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MPEG Decoder

and

System Controlle r

27 pF

14.318

27 pF2

8

19-26

8

2

MHz

11 - 18

41
43

37
35

10

38

1

39

7

9

C[7:0]

ACLK
DCLK

2XPCLK
PCLK

VSYNC*
HSYNC*

CRS

3

4

Y[7:0]

CRSEN

MOD1
MOD0

XO/FIN

XI

CH7203

CVBS

RSET

FS

CH7203

360 Ω

1

S-Video

1

1

Connector

Composite

Connector

Ferrite Bead

32

Y

75 Ω

Ferrite Bead

30

C

75 Ω

Ferrite Bead

31

75 Ω

28

JUMPER

8

Note: 1.

Figure 3: CH7203 Interface Diagram

Please refer t o the Op tional Output Filter diagram below

2.

The pr oper val ue of the s e capaci tors de pend s on t h e c ryst al m an ufacture r ’s speci fi c ati o ns . Pl ea s e re fer t o AN 0 6 for t he
details of the calculation.

47 pF

1.2uH

Y, C , CV BS

75 Ω

1.2uH
OUTPUT

270 pF 15 0 pF

Figure 4: Optional Output Filter

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CH7203

General Description

The CH7203 is a f ully integra te d s olution f or c onverting 1 6-bit YCrCb (4:2:2) d igital v ideo in puts into hig h­quality NTSC o r PAL video s ignals wh ile ge nerating all essential clo ck signals for MPEG playbac k. All
essential circuitry for this conversion and clock generation (Dual PLL’s, linear interpolator, digital filters,
NTSC/PAL encoder, DAC ’s) are contained in the CH7203 making it an essential component of any low-cost
solution for video-CD playback machines. Refer to the Block Diagram on page 1 and the Int erface Diagr am on
page 5.

Fun cti ona l De s cription

The en coded luminance (Y) a nd c olor-difference (U,V) are interpola ted, a nd filter e d through digita l filter s to
minimize aliasing problems. The filtered signals go to the digital encoder where they are transformed to
composite and S-video outputs, and then th ey are converted by the th ree 9-bit DACs to analog outputs.

1 6-bit YCrCb (4:2:2) Input

Y data i s input thro ugh the Y [7 :0] inputs and CrCb data is multiplexed t hrough the C[7:0] inputs. When
CRSEN* = 1, the Cr Select input, C RS, is ignored, and all ev en h orizontal pixels are Cb data and all odd
ho rizo nt al pi x el s ar e C r. Refe r t o Figure6 o n pa ge 7 for th e definition of “even” an d “odd” pixel s. When
CRSEN* = 0, the alternating CRS sign al s pecifies th e C rC b sequ ence. CR S = 1 indicates C[7:0] carries Cr
data, and CRS = 0 indicates C[7:0] carries Cb data.

Cloc k/ Da ta /S y nc hr oni z ati on Tim ing

The CH7203 not o nl y wor ks as an NTSC /PAL encoder, it also sup plies the necessary clocks (1X pixel, 2X
pixel, video system, and audio) and synchronization (HSYNC* and VSYNC*) signals to other building blocks
in the video system. For this reason, the CH7203 wo rks only in the Master mode.

It is importan t to note the CH7203 does not ha ve a “pi xel clock” input pin. Therefore, the timing issues related
to v ide o pix el d a ta be in g su pp li ed f rom , f or e xam ple , the M PE G de cod e r, to t h e CH 7203 (p ins Y [7: 0] a nd
C[ 7:0 ]) ne ed t o be c lar ifi ed . A ss ume t he pi x el s ync hr oni za tion of a s yste m i s bas ed on the 2X p ixe l cl ock
( 2XPLCK). In this type of desi gn, 2XP CLK is distr ibuted across the entire video system, and it is also used to
latch the incoming data appearing at pins Y[7:0] and C[7:0]. Figure 7 on page 8 shows all ti ming reference d
to the 2XPCLK outpu t signa l (l o ade d wit h 50 pF ).

Vide o Enc ode r Modes

Combinat i ons of t he tw o signa l s MO D1 and MOD0 sel ect t he vari ous power s avi ng modes as s hown be low .

Tabl e 3 • Video Encoder Modes

MOD1 MOD0 Video Encoder Mode

11NTSC
10PAL
0 1 PAL-60
0 0 Sleep mode (Enc oder off,both PLLs running)

Freq ue nc y Sel ec t Mo de s

The frequency select input FS affects the DCLK and ACLK o utputs as shown below:
FS = 1 (default) DCLK = 40.5 MHz, ACLK = 16 .934 MHz
FS = 0 DCLK = 33.9 MHz, ACLK = 11.289 MHz

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Timing D iagrams

HSYNC*

VSYNC*

ODD F

ASTER MODE

M

VSYNC*

VEN FIELD

E

AST ER MODE

M

IELD

t

7

CH7203

t

7

2XPCLK

(out)

PCLK

(out)

(in)

(in)

HSYNC*

(out)

Figure 5: HSYNC* and VSYNC* Timing

First (Y,C ) data

Y

C

Pixel[0]

Cb

t10

64 2XP CLK cycles

latched

in af ter HSYNC* goes lo w

Pixel[1] Pixel[2]

Cr Cb Cr

Figure 6: Cb, Cr Sequence Diagram

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Data is latched into the device on the falling edge of 2XPCLK, when PCLK is low.

CH7203

t

1

t

2

2XPCLK
PCLK

t

t

5

6

H/V Sync
Pixel Data

t

3

t4

Figure 7: Clock/Data/ Syn chronization Timing Di agram

Note: Refer to Table 8 on page 14 for timing values

STAR T

STAR T

OF

OF

VS YNC

ANA LOG

ANA LOG

Start of

f i el d 1

FIELD 1

FIELD 1

523 5 24 52 5

520 521 522 523 524 525 1 2 3 4 5 6 7

520 521 522 523 524 525 1 2 3 4 5 6 7

12345678

Pre-equalizing
pu ls e ve rt ic a l

Reference

ANA LOG

ANA LOG

sub- car rie r ph ase

FIELD 2

FIELD 2

colo r fiel d 1

VS YNC

t1+V

Line
vertical

interv al

Verti ca l syn c

pulse interval

Latch Latch Latch

Post-equalizing

pu ls e inter v al

9 101112

89

89

261 262

258 259 260 261 262 263 264 265 266 267 268 269 272

258 259 260 261 262 263 264 265 266 267 268 269 272

523

52452512345678 9

520 521 522 523 524 525 1 2 3 4 5 6 7

261 262 263 264 265 266 267 268 269 270 271 272 273 274 275

258 259 260 261 262 263 264 265 266 267 268 269 272

263

264 265 266 267 268 269 270 271 27 2 273 2 74 275

Start of

fi el d 2

Reference

ANA LOG

sub-carrier phase

FIELD 1

co lo r fiel d 2

Start of

f i el d 3

ANA LOG

Reference

sub-carrier phase

FIELD 2

color field 3

STAR T

OF

VS YNC

t2+V

+V

t

3

270 271

270 271

10 11 12

270 271

Start of

fi eld 4

Reference
su b- c ar r ier ph as e
color field 4

89

Figure 8: Interlaced NTSC Timing Diagram

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START

START

OF

OF

VSYNC

VSYNC

ANALOG

ANALOG
FIELD 1

FIELD 1

CH7203

BURST

BURST

BLANKING

BLANKI NG

INTE R VA L S

621622623624625123456762 0

621622623624625123456762 0

ANALOG

ANALOG
FIELD 2

FIELD 2

30 9 31 0 31 1 31 2 31 3 31 4 31 5 31 6 31 7 31 8 31 9 32 0 32 330 8 32 2

30 9 31 0 31 1 31 2 31 3 31 4 31 5 31 6 31 7 31 8 31 9 32 0 32330 8 32 2

ANALOG

ANALOG
FIELD 3

FIELD 3

621622623624625123456762 0

621622623624625123456762 0

ANALOG

ANALOG
FIELD 4

FIELD 4

30 9 31 0 31 1 31 2 31 3 31 4 31 5 31 6 31 7 31 8 31 9 32 030 8

30 9 31 0 31 1 31 2 31 3 31 4 31 5 31 6 31 7 31 8 31 9 32 030 8

4

BURST PHASE = REFERENCE PHASE = 135 RELATIVE TO U

BURST PHASE = REFERENCE PHASE = 135 RELATIVE TO U

PAL SWIT CH = 0, +V COMPONENT

PAL SWIT CH = 0, +V COMP O NE NT

3
2

°

°

8910

8910

32 1

32 1

8910

8910

32 332 2321

32 332232 1

BURST PHASE = REFERENCE PHASE + 90 = 225 REL AT IVE TO U

BURST PHASE = REFERENCE PHASE + 90 = 225 RELATIVE TO U

PAL SWIT CH = 1, - V CO MP ON ENT

PAL SWIT CH = 1, - V CO MPO NE NT

1

°°

°°

Figure 9: Interlaced PAL Timing Diagram

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CH7203

Color / Level mA V

Wh i t e
Yellow

Cyan
Green

Magenta
Red

Blue
Black

Blank

Sync

24.60

26.59

22.85

24.59

19.85

21.30

18.11

19.30

15.23

16.15

13.49

14.15

10.49

11.0 0

8.74

9.0 0

7.49

7.58

0.50

0.00

0.922

0.997

0.857

0.922

0.745

0.799

0.679

0.724

0.571

0.606

0.506

0.531

0.393

0.413

0.327

0.338

0.281

0.284

0.019

0.000

COLOR BARS :

Note: 1 100% amplitude, 100% saturation color bars are shown

Note: 2 Vref = 1.235V, RSET = 360Ω, 75Ω doubly terminated load

Figure 10: NTSC Y (Luminance) Output Waveform

Color / Level mA V

Wh i t e
Yellow

Cyan
Green

Magenta
Red

Blue
Black

Blank

Blank

Sync

24.60

26.83

22.85

24.69

19.85

21.1 9

18.11

19.0 5

15.23

15.70

13.49

13.57

10.49

10.21

8.74

8.08

7.49

0.50

0.00

0.922

1.006

0.857

0.926

0.745

0.795

0.679

0.715

0.571

0.589

0.506

0.509

0.393

0.383

0.327

0.303

0.281

0.019

0.000

COLOR BARS :

Note: 1 100% amplitude, 100% saturation color bars are shown

Note: 2 Vref = 1.235V, RSET = 360Ω, 75Ω doubly terminated load

Figure 11: PAL Y (Luminance) Video Output Waveform

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CH7203

Color / Level mA V

8.99

5.37

6.43

3.12

4.00

2.37

3.21

0.848

0.951

0.819

0.922

0.735

0.831

0.599

0.681

0.468

0.536

0.337

0.391

0.201

0.241

0.117

0.150

0.089

0.121

Cyan / Red
Green / Magenta

Yellow / Blue

P e ak B ur s t

Blank

P e ak B ur s t

Yellow / Blue

Green / Magenta
Cyan / Red

22.60

25.37

21.85

24.59

19.61

22.16

15.98

18.15

12.49

14.294

10.44

COLOR BARS :

3.579545 MHz Color Burst
(9 cyc le s)

Note: 1 100% amplitude, 100% saturation color bars are shown

Note: 2 Vref = 1.235V, RSET = 360Ω, 75Ω doubly terminated load

Figure 12: NTSC C (Chrominance) Video Output Waveform

Color / Level mA V

8.74

5.37

6.85

3.12

4.27

2.37

3.43

0.848

1.015

0.819

0.983

0.735

0.886

0.609

0.720

0.468

0.572

0.328

0.423

0.201

0.257

0.117

0.160

0.089

0.129

Cyan / Red
Green / Magenta

Yellow / Blue

P e ak B ur s t

Blank

P e ak B ur s t

Yellow / Blue

Green / Magenta
Cyan / Red

22.60

27.0 6

21.85

26.2 2

19.61

23.6 3

16.23

19.2 1

12.49

15.2 4

11.2 8

COLOR BARS :

4.433619 MHz Color Burst
(10 cycles)

Note: 1 100% amplitude, 100% saturation color bars are shown

Note: 2 Vref = 1.235V, RSET = 360Ω, 75Ω doubly terminated load

Figure 13: PAL C (Chromina nce) Video Output Waveform

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CH7203

Note:

Co lor / Level mA V

26.59

9.00

9.62

7.58

4.32

3.72

0.50

0.00

1.271

1.217

0.997

1.026

0.450

0.429

0.338

0.360

0.284

0.162

0.139

0.019

0.000

Pea k Chrom a

White

Pea k Bu rst
Black
Blank 8.16 0.306

Pea k Bu rst

Sync

33.89

32.45

27.37

12.00

11.43

Figure 14: Composite NTSC V ideo Output Waveform

Vref = 1.235V, RSET = 360Ω, 75Ω doubly termin ated load

COLOR BARS :

3.579545 M H z
Col or Burst

(9 Cycles)

WHITE

YE LLOW

CYAN

GRE EN

MAGENTARED

BLA CK

BLUE

Note:

Co lor / Level mA V

12.04

8.08

4.58

4.12

0.50

0.00

1.271

1.240

1.026

1.006

0.450

0.452

0.303

0.171

0.154

0.019

0.000

Pea k Chrom a

White

Pea k Bu rst

Blank/Black 8.64 0.324

Pea k Bu rst

Sync

33.89

33.08

27.37

26.8 3

12.00

Figure 15: Composite PAL Vi deo Output Waveform

Vref = 1.235V, RSET = 360Ω, 75Ω doubly terminated load

COLOR BARS :

4.433619 M H z

Col or Burst

(10 Cycles)

WHITE

YE LLOW

CYAN

GRE EN

MAGENTARED

BLA CK

BLUE

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CH7203

Electrical Specifications

Table 4 • Absolute Maximum Ratings

Symbol Description Min Typ Max Units

VDD relative to GND - 0.5 7.0 V
Input voltage of all digital pins

T

T

AMB

T

STOR

T

T

VPS

P

MAX

SC

J

Analog output short circuit duration Indefinite Sec
Ambient operating temperature - 55 125 °C
Storage temperature - 65 150 °C
Junction temperature 150 °C
V apor phase soldering (one minute) 220 °C
Maximum power dissipation TBD W

Note: Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are

stress ratings only. Function al operation of the device at these or any other conditions above those indicated under the normal
operating conditions is not reco mmended. Exposure to absolute maxi mum rating conditions for extended periods may affect
reliability.

The device is fabricated using high-performance CMOS technology. It should be handled as an ESD-sensitive device.

Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce destructive latchup.

Table 5 • Recommended Operating Conditions

1

GND - 0. 5 VDD + 0.5 V

Symbol Description Min Typ Max Units

A VD D Analog supply voltage 5.00

DVDD D igital supply voltage 5.00

T

A

R

L

Table 6 • Electrical Characteristics (Operating Conditions: T

Ambient operating temperature 0 25 70 °C
Output load to DAC outputs 37.5 Ω

= 0°C – 70°C, VDD = 5V ± 5%)

A

Symbol Description Min Typ Max Unit

Video D/A resolution 9 9 9 Bits
Full scale output current 33.08 mA
Video level error

using internal reference 10 %

Total Current Consumption 135 mA

Note: A s a pp li e d to Ta bl e s 4, 5, an d 6, R ec om me n de d Ope r at in g C on di tion s a re us e d as te s t c on diti on s unless ot her w ise spe c i f ied.

RS E T = 36 0

and NTSC CCIR601 operation. Typical values are based on 25°C and +5V.

Ω,

Table 7 • Digital Inputs / Outputs

Symbol Description Test C ondition @ T

CD

CD

V

V

V

I

V

I

OH
OL

PU
LK

OUT

Output high voltage I

= - 400 µA 2.4 V

OH

Output low voltage IOL = 3.2 mA 0.4 V
Input high voltage 2.0 VDD + 0.5 V

IH

Input low voltage GND - 0.5 0.8 V

IL

Input internal pull-up current 5 25 µA
Input leakage current -10 10 µA
Input capacitance f = 1 MHz, V

IN

= 2.4V 7pF

IN

Output capacitance 10 pF

= 25°C Min T yp Max U nits

A

201-0000-031 R ev 2.0, 6/ 2/99 13

CHRONTEL

Electrical Specifications (continued)

Table 8 • AC Characteristics

Symbol Description Min Typ Max Units

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

10

2XPCLK 37 ns
2XPCLK high t ime 14.8 22. 2 ns
Pixel/Sync setup time 6 ns
Pixel/Sync hold time 3 ns
Sync active delay time 3 ns
Sync inactive delay time 17 ns
HSYNC* to VSYNC* delay 30 30 ns
HSYNC* pulse width 64 x t
VSYNC* delay time 17 20 ns
VSYNC* pulse width 2.0 Hor. lines

1

CH7203

ns

Tes t
Conditions:

Unless ot herwise specified, the testing conditions are t he same as in Tab le 5, “Recommen ded Operating Conditions,”
on page 13 . TTL input values are 0 – 3V, with input rise / fall times < 3 ns, measured between the
reference points at 50% for non-TTL inputs and outputs. TTL reference points at 1.5V for inputs and outputs. Analog
output load < 10 pF.

Since t he CH720 3 do e s not ha ve a pixel c lo c k in pu t, al l in pu t sign a l ti m ing i s c ho se n wit h r e sp e ct to t he outp ut cl oc k
timing of 2XPCLK and PCLK . PCLK can be used at the “Qualifying” clock for certain MPEG decoders.

and

. Timi ng

V

V

IL

IH

14 201-0000-031 Rev 2.0, 6/2/99

CHRONTEL

CH7203

ORDERING INFORMATION

Part number Package type Number of pins Volt age supply

CH7203-V

PLCC 44 5V

Chrontel

2210 O’Toole Avenue

San J ose, CA 95131-1326

Tel: ( 408) 383-9328
Fax: [phone]



19 97 Ch rontel , Inc. All Righ ts Re s er v ed .

C hrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICAT I ONS WITHO UT TH E
SPEC IFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perf or m w hen us ed a s dire cted c an r e asonabl y
e xpect to resu lt in per son al injur y or dea th. C hron te l reserv es t he rig ht t o make chan ges at any ti me witho ut no tic e to imp rov e an d su ppl y the be s t po ssibl e prod uct an d is n ot
re s pon sibl e and does no t assu m e any li ability for mi s app lic a ti on or us e o uts ide the li mits sp ec ifie d in this do cumen t. We pro vide no war r a nt y for the us e of our pr o duct s and a s s um e no
liab ility for errors containe d in this do cument. Printed in the U.S.A.

15 201-0000-031 Rev 2.0, 6/2/99