• Outputs NT SC, PAL ( B,D,G,H,I) and PAL-M (NTSCJ or PAL-60 available as options)
• 8-bit YCrCb (4:2:2) input fo rmat
• Master or slave mode op eration
• Triple 9-bi t DAC fo r co mposi te and S-vi de o output
• 27 MHz DAC operating frequency eliminates
the need for 1/sinc(x) correction filter
• Low-jitter phase-locked loop circuitry operates using a
low- c ost 14. 31818 MHz crys ta l
• 40. 5 or 33.9 MH z video decoder c loc k out put
• 16. 934 or 11.2 89 MHz audio de co de r clo ck ou tput
• 13. 5 MHz and 27 MH z video pi xe l clock out put s
• Inte r nal 4. 6 MHz (m ax ) lum ina nc e a nd 1. 3 MHz
chrominance filters
• Sub-carrier genlocked to HSYNC* and VSYNC*
• Sleep mode
• CMOS technology in 44-pin PLCC
• 5V single-supply operation
Description
The CH7202 video encoder integrates a dual PLL clock
generat or and a digit al N TSC/PAL video encoder. B y
generating all essential clock signals for MPEG
playback, and convertin g dig ital video inpu ts to either
NTSC or PA L vi deo si g na l s , t he C H 72 02 is an e s s ent i al
component of any low-cost solution for video-CD
playback machines.
Th e C H72 02 d ua l PLL clo ck sy nth e siz er ge ne rat es a ll
clocks and timing signals from a 14.31818 MHz
reference crystal (see application note 19 “Tuning
Clock Outputs” for selection and tuning of the 14.31818
MHz crystal). The CH7202 will accept HSYNC*,
VSYNC*, and 2XPCLK clock inputs during slave
mo de op era ti on. Ti m ing si g nals fro m the PLLs can b e
used to generate the horizontal and vertical sync signals
which enable operating the CH7202 in master mode.
The fully digital video encoder is pin-programmable to
generate either a 525-line NTSC or a 625-line PAL
compatible video signal. It also features a logic
selectable sleep mode which turns the encoder off while
leaving both PLL’s running.
M/S*
YC[7:0],
HSYNC*
VSYNC*
PCLK
2XPCLK
DCLK
ACLK
8
MOD0MOD1FS
INTERFACE
STAT E
MACHINE
1/2
CbSWAPYCSWAP
BLAN KING
H,V SYNC
GEN ERATO R
LINEAR
INTERPOLATO R
PLL1
OSCPLL2
XI XO/FIN
Y
FILTER
U
FILTER
V
FILTER
BLANKING
COLO R-B URST
CO NT RO L
Figure 1: Functional Block Diagram
RSETAVDDVDD
IREF
M
U
X
M
U
X
M
U
X
SIN + COSINE
GENERATOR
AGNDGN D
ΣX
X
Σ
DAC
DAC
DAC
Y
CVBS
C
201-0000-030 R ev 2.0, 6/ 2/991
Page 2
CHRONTEL
YCSWAP
CbSWAP
FS
MOD1
YC[7]
YC[6]
YC[5]
YC[4]
YC[3]
YC[2]
YC[1]
7
8
9
10
11
12
13
14
15
16
17
AVDD
6
AGND
XI
5
4
VDD
XO/FIN
3
2
CHRONTEL
CH7202
ACLK
1
GND
44
CH7202
2XPCLK
VDD
DCLK
GND
43
42
41
40
39
PCLK
38
MOD0
37
VSYNC*
36
VDD
35
HSYNC*
34
GND
33
GND
32
Y
31
CVBS
30
C
29
AVDD
18
19
20
YC[0]
NCNCNC
21
NC
22
NC
23
24
NC
25
NC
26
27
M/S*
AGND
Figure 2: CH7202 Pinout Diagram
28
RSET
2201-0000-030 Rev 2.0, 6/2/99
Page 3
CHRONTEL
Table 1. Pin Descriptions
PinTypeSymbolDescription
1OutACLK
2, 36, 42PowerVD D
3InXO/FIN
4In XI
5, 27PowerAGND
6,29PowerAVD D
7InYCSWAP
8In FS
9InMOD1
10InCbSWAP
11 – 18InYC[7:0]
Au dio D e c oder Clock O ut put
16.934 MHz or 11.289 MHz clock output (selectable by FS) for
MPEG audio decoder operation. The output swing is 5V.
Digital Supply Voltage
These pins supply the 5V power to the digital section of the
CH7202.
Crystal Output or External F
A parallel res onance 14.31818 MH z (±50 ppm) crystal may be
attached between XO/FIN and XI. An external CMOS compatible
clock can be connected to XO/FIN as an alternative.
Crystal Inp ut
A parallel resonance 14.31818 MHz (±50 ppm) crystal should be
attached between XI and XO/FIN. However, if an external CMOS
clock is attached to XO/FIN, XI should be connected to ground.
Analog ground
These pins provide the ground reference for the analog section of
the CH7202. These pins MUST be connected to the system
ground to prevent latchup.
Analog Supply Voltage
These pins supply the 5V power to the analog section of the
CH7202.
L um a /Chr om a S w a p.
YCSWAP=0 indicates a luminance sample is the first sample
following the leading edge of HSYNC*. YC SWAP=1 indicates a
chroma sample (Cb or CR depending on CbSWAP) is the first
sample following the leading edge of HSYNC*. See
page 7.
This input w orks in conjunction with the MOD 0 input to select
NTSC, PAL, or Sleep mode functions. R efer to
Encoder Modes,” on page 6
Cb /Cr Sw a p.
When CbSWAP=0, the first chroma sample following the leading
edge of HSYNC* will be a Cb sample. When CbSWAP= 1, the first
chroma sample following the leading edge of HSYNC* will be a Cr
sampl e . See
Video Inpu t
These pins accept the YCrCb data in CCIR656 (4:2:2) digital
video format. The sequence of the Y, C b, Cr dat a is defined by
the YCSWAP and CbSWAP pins. For more details, please refer
to the timing diagram shown in
Y has a nom inal range of 16–235.
Cb & Cr have a nominal range of 16–240, w ith 128 equal to zero.
1
Internally pulled-up
Internally pulled-up
Internally pulled-up
Figure 5
on page 7
1
In put
REF
Internally pulled-up.
for details.
Figure 5
on page 7.
CH7202
Figure 5
Table 3 , “V ideo
on
Note:1.
required only if the crystal oscillation frequency cannot be controlled to the required accuracy. The capacitance value f or the tuning capacitor should be obtained from the crystal manufacturer. For further information, request a copy of
Outputs.”
P lease refer to crys tal manufacturer specificat ions f or p r oper l oad capaci tances. The opti onal v ariab l e tu ni ng capa citor is
Applica tion Note AN-19, “Tuning Cloc k
201-0000-030 R ev 2.0, 6/ 2/993
Page 4
CHRONTEL
Table 2. Pin Descriptions (continued)
CH7202
Pin
26InM/S*
19-25InNC
28InRSET
30OutC
31OutCVBS
32OutY
33, 34, 40, 44PowerGND
35In/OutHSYNC*
37In/OutVSYNC*
38InMOD0
39OutPCLK
41OutDCLK
43In/Out2XPCLK
Type
SymbolDescription
Master/Slave*
M/S*=1 then the CH7202 operates in master mode.
M/S*=0, then the CH7202 operates in slave mode.
No Connect
Reference Resistor
A 360 Ω resistor with s hort and w ide t races s hould be attached
between RSET and ground. No other connections should be
made to this pin.
C hrominanc e O ut put
A 75 Ω termination resistor with short traces should be attached
between C and ground for optimum perf ormance.
C om posit e O ut put
A 75 Ω termination resistor with short traces should be attached
between CVBS and ground for optimum performance.
Luminance Output
A 75 Ω termination resistor with short traces should be attached
between Y and ground for optimum perform ance.
Digital Ground
These pins provide the ground reference for the digital section of
the CH7202. These pins MUST be connected to the system
ground through
Ho rizo nta l S y nc Input /O utput
The horizontal sync output is generated by the CH7202 for master
mode operation. H SYNC* is an ac tive low signal. In slav e mode,
the horizontal sync becomes an input. For additional inf ormation,
please refer to the timing diagrams shown in
page 8.
Vertical Sync Input/Output
The vertical sync output is generated by the CH 7202 for master
mode operation. VSYNC* is an active low signal. In slave mode,
the vertical sync becomes an input. For additional information,
please refer to the timing diagrams shown in
page 8.
Mo de bit 0
This input w orks in conjunction with the MOD 1 input to select
NTSC, PAL, or Sleep Mode functions. R efer to
Encoder Modes,” on page 6
Video Pixel Clock Output
13.5 MHz clock output.
MPE G De coder Clock O ut put
40.5 MHz or 33.9 MHz clock output (selectable by FS).
Do uble P ixe l Clock Inpu t /O utput
27 MHz clock output. In slave mode, this pin becomes a 27 MHz
clock input.
Internally pulled-up.
independent
- internally pulled-up
ground vias.
for details.
Figures6
Figures6
and 7 on
and 7 on
Table 3 , “V ideo
4201-0000-030 Rev 2.0, 6/2/99
Page 5
CHRONTEL
CH7202
MPEG Decoder
and
System Controlle r
27 pF
14.318
27 pF2
8
2
MHz
11 - 18
25
41
43
39
37
35
10
38
1
7
9
3
4
M/S*
YC[7:0]
ACLK
DCLK
2XPCLK
PCLK
VSYNC*
HSYNC*
YCSWAP
CbSWAP
MOD1
MOD0
XO/FIN
XI
CH7202
CVBS
RSET
FS
360 Ω
1
S-Video
1
1
Connector
Composite
Connector
Ferrite Bead
32
Y
75 Ω
Ferrite Bead
30
C
75 Ω
Ferrite Bead
31
75 Ω
28
JUMPER
8
Note:1.
Note:2.
details of the cal culation.
Figure 3: CH7202 Interface Diagram
Please refer t o the Op tional Output Filter diagram below.
The proper value of these capacitors depends on the crystal manufacturer’s specifications. P lease refer to AN06 for the
47 pF
1.2 µH
Y, C , CV BS
75 Ω
1.2 µH
OUTPUT
270 pF 15 0 pF
Figure 4: Optional Output Filter
201-0000-030 R ev 2.0, 6/ 2/995
Page 6
CHRONTEL
CH7202
General Description
The CH72 02 is a fully integrated solution for conver ting 8-bit YCrCb (4:2:2) dig ital v ideo inputs into highquality NTSC o r PAL video s ignals wh ile ge nerating all essential clo ck signals for MPEG playbac k. All
essential circuitry for this conversion and clock generation (Dual PLL’s, linear interpolator, digital filters,
NTSC/PAL encoder, DAC ’s) are contained in the CH7202 making it an essential component of any low-cost
solution for video-CD playback machines. Refer to the Block Diagram on page 1 and the Int erface Diagr am on
page 5.
Fun cti ona l De s cription
The encoded lumin an ce (Y ) an d color-differe nc e (U,V) va lues are i nterpolated an d f iltered throug h digital
filters to minimiz e aliasing problems. The filtered signals go to the digital encoder where they are tran sformed
to composite and S-video out puts, an d then they ar e converted by the three 9-bit DACs to analog outputs.
8 -bit YCrCb (4:2:2) Input
Y data and Cr Cb data are multiplexed into the CH7202 through the YC[7:0] pins. The order of the multiplexed
data is determined by the YCSWAP and CbSWAP pins, and is re ferenced to the h oriz onta l sy nc pin. Refer to
Figure 5 on page 7.
Cloc k/ Da ta /S y nc hr oni z ati on Tim ing
The CH7202 can operate in eit her master or slave mode. In master mode, it supplies the necessary clocks (1X,
2X, video s ystem and audio) and sync hro ni zati on ( HSYNC* and VSYNC*) signals to othe r buildi ng blocks in
the video system. In slave mode, the 2X pixel clock, HSYNC* and VSYNC* become inputs to the CH7202,
and the remai ning clock signa ls are still output. The timing relationship s are shown in Figures 6
page 8.
and 7 on
Vide o Enc ode r Modes
Combinations of the two signals MOD0 and MOD1 select the v ario us TV signal format and power saving
mode s as s hown below .
VDD relative to GND- 0.57.0V
Input voltage of all digital pins
T
T
AMB
T
STOR
T
T
VPS
P
MAX
SC
J
Analog output short circuit durationIndefiniteSec
Ambient operating temperature- 55125°C
Storage temperature - 65150°C
Junction temperature150°C
V apor phase soldering (one minute)220°C
Maximum power dissipationTBDW
Note: Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are
stress rating s only. Functional operation of the device at these or any other conditions above those indicat ed under the normal
operating con ditions is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
The device is fabricated using high-performance CMOS technology. It should be handled as an ESD-sensitive device.
Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce destructive latchup.
Table 5 • Recommended Operating Conditions
1
GND - 0. 5VDD + 0.5V
SymbolDescriptionMinTypMaxUnits
A VD DAnalog supply voltage5.00
DVDDD igital supply voltage5.00
T
A
R
L
Table 6 • Electrical Characteristics (Operating Conditions: T
Ambient operating temperature 0 2570°C
Output load to DAC outputs37.5Ω
= 0°C – 70°C, VDD = 5V ± 5%)
A
SymbolDescriptionMinTypMaxUnit
Video D/A resolution999Bits
Full scale output current33.08mA
Video level error
using external reference
using internal reference
10
5
%
%
Total Current Consumption135mA
Note: A s a pp li e d to Ta bl e s 4, 5, and 6, R ec om me n de d Ope r atin g C on di tion s are us ed a s te s t c on di tion s un le s s other w ise spe cifie d .
RS E T = 36 0
and NTSC CCIR601 operation. Typical values are based on 25°C and +5V.
2XPCLK37ns
2XPCLK high t ime14.822. 2ns
Pixel/Sync setup time6ns
Pixel/Sync hold time3ns
Sync active delay time3ns
Sync inactive delay time17ns
HSYNC* to VSYNC* delay3030ns
HSYNC* to VSYNC* field detect15.6µS
HSYNC* to VSYNC*16.1µS
HSYNC* pulse width64 x t
1
VSYNC* pulse width2.0 Hor. lines
CH7202
ns
Tes t
Conditions:
Unless ot herwise specified, the testing conditions are t he same as in Tab le 5, “Recommen ded Operating Conditions,”
and
on page 14 . TTL input values are 0 – 3V, wi th input rise / fall times < 3 ns, measured between the
reference points at 50% for non-TTL inputs and outp uts. TTL reference poi nts at 1.5V for inputs and outputs. Analog
V
IL
V
IH
. Timi ng
output load < 10 pF.
Since t he CH720 2 do e s not ha ve a pix e l c lo c k in put, al l in pu t sign a l ti m ing i s c ho se n w it h r e sp e ct to t he outp ut cl oc k
timing of 2XPCLK and PCLK . PCLK can be used at the “Qualifying” clock for certain MPEG decoders.
201-0000-030 R ev 2.0, 6/ 2/9915
Page 16
CHRONTEL
CH7202
ORDERING INFORMATION
Part numberPackage typeNumber of pinsVolt age supply
CH7202
PLCC445V
Chrontel
2210 O’Toole Avenue
San J ose, CA 95131-1326
Tel: ( 408) 383-9328
Fax: (408) 383-9338
19 97 Ch rontel , Inc. All Righ ts Re s er v ed .
C hrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICAT I ONS WITHO UT TH E
SPEC IFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perf or m w hen us ed as dire cted c an r e asonabl y
e xpect to resu lt in per son al injur y or dea th. C hron te l reserv es t he rig ht t o make chan ges at any ti me witho ut no tic e to imp rov e an d su ppl y the be st po ssibl e pr od uct an d is n ot
re s pon sibl e and does no t assum e any li abi lit y fo r mi s app lica tion or us e o uts ide the li mits sp ec ifie d in t his do cum en t. We pr o vide no war r a nt y for t he us e of our pr o duct s and a s s um e no
liab ility for errors containe d in this do cument. Printed in the U.S.A.
16201-0000-030 Rev 2.0, 6/2/99
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