Datasheet CH7008A-V, CH7008A-T Datasheet (Chrontel Inc)

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CHRONTEL

Digital PC to TV Encoder Features

CH7008A

Features

• Support for low voltage interface to VGA controller

• Universal digital interface accepts YCrCb (CCIR656) or RGB (15, 16 or 24-bit multiplexed) video data in both non-interlaced and interlaced formats

• TrueScale operations for various graphic resolutions† ¥

• Enhanced text sharpness and adaptive flicker removal with up to 5-lines of filtering†

• Enhanced dot crawl control and area reduction

• Fully programmable through I2C port

• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D, G, H, I, M and N) TV formats

• Provides Composite, S-Video and SCART outputs

• Auto-detection of TV presence

• Programmable power management

• 9-bit video DAC outputs

• Complete Windows and DOS driver software

• Offered in 44-pin PLCC, 44-pin TQFP

rendering engine supports underscan

General Description

Chrontel’s CH7008 digital PC to TV encoder is a standalone integrated circuit which provides a PC 99 compliant solution for TV output on non-DVD enabled systems. Suggested application use with the Intel 810 chipset & Intel 810E chipset.* It provides a universal digital input port to accept a pixel data stream from a compatible VGA controller (or equivalent) and converts this directly into NTSC or PAL TV format.

This circuit integrates a digital NTSC/PAL encoder with 9-bit DAC interface, and new adaptive flicker filter, and high accuracy low-jitter phase locked loop to create outstanding quality video. Through its TrueScale scaling and deflickering engine, the CH7008 supports full vertical and horizontal underscan capability and operates in 5 different resolutions including 640x480 and 800x600.

A new universal digital interface along with full programmability make the CH7008 ideal for system-level PC solutions. All features are software programmable through a standard I2C port, to enable a complete PC solution using a TV as the primary display.

† Patent number 5,781,241 ¥ Patent number 5,914,753

D[11:0]

PIXEL DATA

GPIO[1:0]

DIGITAL

INPUT

INTERFACE

I2C REGISTER &

CONTROL BLOCK

SC SD

RGB-YUV

CONVERTER

RESET*

MEMORY

TRUE SCALE

SCALING &

DEFLICKERING

ENGINE

SYSTEM CLOCK

XCLK*

LINE

PLL

YUV-RGB CONVERTER

NTSC/PAL ENCODER & FILTERS

TIMING & SYNC

GENERATOR

XI/FIN

CSYNC

TRIPLE

P-OUT

DAC

DS/BCO

Y/R

C/G

CVBS/B

ISET

201-0000-027 Rev 2.2, 9/30/99 *Intel 810 and Intel 810E are Trademarks of Intel Corp 1

Figure 1: Functional Block Diagram

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CHRONTEL CH7008A

D0]

D[1]

XCLK*

XCLK

VREF

DVDD2

P-OUTHDGND

DS/BCO

AGND

39 D[2] D[3] D[4]

DVDD

D[5] DGND D[6]

D[7] D[8] D[9]

8 9 10 11 12 13 14 15 16 17

CHRONTEL

CH7008

D[10]

D[11]

GPIO[0]

DVDD

GPIO[1]

CSYNC

GND

DGND

CVBS

XI/FIN

AVDD

DVDD

RESET* 34 33

SC 32

SDDGND] 31

VDD 30

ISET 29

GND

Figure 2: 44-Pin PLCC

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CHRONTEL CH7008A

D0]

D[1]

XCLK*

XCLK

VREF

DVDD2

P-OUTHDGND

DS/BCO

AGND

XO D[2] D[3] D[4]

DVDD

D[5] DGND D[6]

D[7] D[8] D[9]

2 3 4 5 6 7 8 9 10 11

CHRONTEL

CH7008

D[10]

D[11]

GPIO[0]

DVDD

GPIO[1]

CSYNC

GND

DGND

CVBS

XI/FIN

AVDD

DVDD

RESET*

28 27

SDDGND]

VDD

ISET

GND

Figure 3: 44-Pin TQFP

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CHRONTEL CH7008A

Table 1. Pin Descriptions

44-Pin

PLCC

1 39

2 40 In XCLK

3 41 In XCLK*

4 42 In/Out H

5 43 In/Out V

6-10,12-

13,15-19

20-21 14-15 In/Out GPIO[0]

23 17 Out CSYNC

26 20 Out CVBS/B

27 21 Out C/G

28 22 Out Y/R

30 24 In ISET

44-Pin

TQFP

44,1-4,6-

7,9-13

Type Symbol Description

In/Out VREF

In D[0]-D[11]

GPIO[1]

Reference Voltage Input

The VREF pin inputs a reference voltage of DVDD2/2. The signal is derived externally through a resistor divider and decoupling capacitor, and will be used as a reference level for data and sync inputs.

External Clock Input This input along with XCLK* will form a differential clock input. For

applications where a differential clock is not available, the XCLK* pin should be connected to the VREF pin.

External Clock Input*

See XCLK description

Horizontal Sync Input/Output

When the SYO bit is low, this pin accepts a horizontal sync input. The level is 0 to DVDD2, with VREF as the threshold level.

When the SYO bit is high, the device will output a horizontal sync pulse. The output is driven from the DVDD supply.

Vertical Sync Input/Output

When the SYO bit is low, this pin accepts a vertical sync input. The level is 0 to DVDD2 with VREF as the threshold level.

When the SYO bit is high, the device will output a vertical sync pulse. The output is driven from the DVDD supply.

Data [0] through Data [11] Inputs

These pins accept 12 data inputs from the graphics controller. The level is 0 to DVDD2, with VREF as the threshold level.

General Purpose Input/Output [0-1] and Internal pull-up These pins provide general purpose I/O’s controlled via the IIC bus,

registers 1Bh and 1Ch, bits 7 and 6. The internal pull-up is to the DVDD supply.

Composite Sync Output

A 75 Ω termination resistor with short traces should be attached between CSYNC and ground for optimum performance. In SCART mode, this pin outputs the composite sync signal.

Composite Video Output/Blue Output

A 75 Ω termination resistor with short traces should be attached between CVBS and ground for optimum performance. In normal operating modes other than SCART, this pin outputs the composite video signal. In SCART mode, this pin outputs the blue signal.

Chroma Output/Green Output

A 75 Ω termination resistor with short traces should be attached between C and ground for optimum performance. In normal operating

modes other than SCART, this pin outputs the chroma video signal. In SCART mode, this pin outputs the green signal.

Luma Output / Red Output

A 75 Ω termination resistor with short traces should be attached between Y and ground for optimum performance. In normal operating

modes other than SCART, this pin outputs the luma video signal. In SCART mode, this pin outputs the red signal.

Current Set Resistor Input

This pin sets the DAC current. A 360 ohm resistor should be connected between this pin and GND using short and wide traces.

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CHRONTEL CH7008A

Table 1. Pin Descriptions

44-Pin

PLCC

32 26 In/Out SD

33 27 In SC

35 29 In RESET*

38 32 In XI/FIN

39 33 Out XO

41 35 In/Out DS/BCO

44-Pin

TQFP

Type Symbol Description

Serial Data Input/Output

This pin functions as the serial data pin of the I2C interface port, and uses the DVDD supply.

(see the I2C Port Operation section for details)

Serial Clock Input

This pin functions as the serial clock pin of the I2C interface port, and uses the DVDD supply.

(see the I2C Port Operation section for details)

Reset* Input

When this pin is low, the CH7008 is held in the power-on reset condition. When this pin is high, the device operates normally and reset is controlled through the I2C register.

Crystal Input/External Reference Input

A parallel resonance 14.31818MHz crystal should be attached between this pin and XO. However, an external CMOS clock can be attached to XI/FIN.

Crystal Output

A parallel resonance 14.31818MHz +20ppm crystal should be attached between this pin and XI/FIN. However, if an external CMOS clock is attached to XI/FIN, XO should not be connected.

Data start (input)/Buffered Clock (output)

In normal operating modes, when configured as an input, the rising edge of this signal identifies the first active pixel of data for each active line. The level is 0 to DVDD2, with VREF as the threshold level.

When configured as an output this pin provides a buffered clock output, driven by the DVDD supply. The output clock can be selected using the BCO register (17th) (see Registers and Programing).

43 37 Out P-OUT Pixel Clock Output

This pin provides a pixel clock signal to the VGA controller (adjustable as 1X, 2X and 3X) and is driven from the DVDD2 supply. This clock will only be provided in master clock modes, and will be tri-stated otherwise, (see the section on Digital Video Interface and Registers and Programming for more details). The capacitive loading on this pin should be kept to a minimum.

11,22,36 5,16,30 Power DVDD

14,24,34,428,18,28,36Power DGND

25,29 19,23 Power GND

31 25 Power VDD 37 31 Power AVDD 40 34 Power AGND 44 38 Power DVDD2

Digital Supply Voltage Digital Ground

DAC DAC Supply Voltage PLL Supply Voltage PLL Ground I/O SUPPLY VOLTAGE

Digital supply voltage for the P-OUT

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CHRONTEL CH7008A

Digital Video Interface

The CH7008 digital video interface provides a flexible digital interface between a computer graphics controller and the TV encoder IC forming the ideal quality/cost configuration for performing the TV-output function. This digital interface consists of up to 12 data signals and 4 control signals, all of which are subject to programmable control through the CH7008 register set. This interface can be configured as 8 or 12-bit inputs operating in multiplexed mode. It will also accept either YCrCb or RGB (15, 16 or 24-bit color depth) data formats and will accept both non-interlaced and interlaced data formats. A summary of the input data format modes is as follows:

Table 2. Input Data Formats

Bus

Width

8-bit 2X-multiplexed RGB 15-bit 5-5-5 over two bytes 8-bit 2X-multiplexed RGB 16-bit 5-6-5 over two bytes

8-bit 2X-multiplexed YCrCb (24-bit) Cb,Y0,Cr,Y1,(CCIR656 style) 12-bit 2X-multiplexed RGB 24 8-8-8 over two words - ‘C’ version 12-bit 2X-multiplexed RGB 24 8-8-8 over two words - ‘I’ version

The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode. The CH7008 can operate in either master (the CH7008 generates a pixel frequency which is either returned as a phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock). The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X or 3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7008 will automatically use both clock edges, if a multiplexed data format is selected.

Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be selected to be generated by the CH7008. In the case of CCIR656 style input (IDF = 9), embedded sync may also be used. In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, times the first value of the (Total Pixels/line x Total Lines/Frame) column of Table13 on page 29 (Display Mode Register 00H description). The leading edge of the horizontal sync is used to determine the start of each line. The Vertical sync signal must be able to be set to the second value in the (Total Pixels/Line x Total Lines/Frame) column of Table13 on page 29.

Transfer Mode Color Space and Depth Format Reference

Master Clock Mode: The CH7008 generates a clock signal (output at the P-OUT pin) which will be used by the VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity).

Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock signal will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the pixel data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC transmits back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet the specified setup and hold times with respect to the pixel clock.

Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after the leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count), plus horizontal sync width, will determine when the chip will begin to sample pixels.

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CHRONTEL CH7008A

Input Data Formats

The XCLK and XCLK* signals are used to latch data from the graphics chip. Data can be latched coincident with the rising edge of XCLK, falling edge of XCLK, or both edges, depending upon register settings of XCM and MCP. The input data format is shown in Figure4. The Pixel Data bus represents an 8 or 12-bit multiplexed data stream, which contains either RGB or YCrCb formatted data. In IDF settings of 4, 5, 7, 8 and 9, the input data rate is 2X pixel clock, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel, encoded as shown in the tables below. When the input is YCrCb, the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb0, Y0, Cr0, Y1 where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples — and the following Y1 byte refers to the next luminance sample, per CCIR656 standards.

However, the clock frequency is dependent upon the current mode, not 27MHz, as specified in CCIR656.

DS / BCO

XCLK

(XCM=01)

XCLK*

(XCM=01)

XCLK

(XCM=00)

XCLK*

(XCM=00)

D[11:0] P0b P1a P1b P2aP0a P2b

When DSEN=1(bit 4 of register 1Ch), SAV should be set to 11d.

SAV

(DSEN=0)

Figure 4: Non-multiplexed Data Transfers

Table 3. RGB 8-bit Multiplexed Mode

IDF#

Format

Pixel# P0a P0b P1a P1b P0a P0b P1a P1b Bus Data D[7] G0[2] R0[4] G1[2] R1[4] G0[2] x G1[2] x

D[6] G0[1] R0[3] G1[1] R1[3] G0[1] R0[4] G1[1] R1[4] D[5] G0[0] R0[2] G1[0] R1[2] G0[0] R0[3] G1[0] R1[3] D[4] B0[4] R0[1] B1[4] R1[1] B0[4] R0[2] B1[4] R1[2] D[3] B0[3] R0[0] B1[3] R1[0] B0[3] R0[1] B1[3] R1[1] D[2] B0[2] G0[5] B1[2] G1[5] B0[2] R0[0] B1[2] R1[0] D[1] B0[1] G0[4] B1[1] G1[4] B0[1] G0[4] B1[1] G1[4] D[0] B0[0] G0[3] B1[0] G1[3] B0[0] G0[3] B1[0] G1[3]

RGB 5-6-5

RGB 5-5-5

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CHRONTEL CH7008A

Table 4. RGB 12-bit Multiplexed Mode

IDF#

Format

Pixel# P0a P0b P1a P1b P0a P0b P1a P1b Bus Data D[11] G0[3] R0[7] G1[3] R1[7] G0[4] R0[7] G1[4] R1[7]

D[10] G0[2] R0[6] G1[2] R1[6] G0[3] R0[6] G1[3] R1[6] D[9] G0[1] R0[5] G1[1] R1[5] G0[2] R0[5] G1[2] R1[5] D[8] G0[0] R0[4] G1[0] R1[4] B0[7] R0[4] B1[7] R1[4] D[7] B0[7] R0[3] B1[7] R1[3] B0[6] R0[3] B1[6] R1[3] D[6] B0[6] R0[2] B1[6] R1[2] B0[5] G0[7] B1[7] G1[7] D[5] B0[5] R0[1] B1[5] R1[1] B0[4] G0[6] B1[4] G1[6] D[4] B0[4] R0[0] B1[4] R1[0] B0[3] G0[5] B1[3] G1[5] D[3] B0[3] G0[7] B1[3] G1[7] G0[0] R0[2] G1[0] R1[2] D[2] B0[2] G0[6] B1[2] G1[6] B0[2] R0[1] B1[2] R1[1] D[1] B0[1] G0[5] B1[1] G1[5] B0[1] R0[0] B1[1] R1[0] D[0] B0[0] G0[4] B1[0] G1[4] B0[0] G0[1] B1[0] G1[1]

12-bit RGB (12-12)

Table 5. YCrCb Multiplexed Mode

IDF#

Format

Pixel# P0a P0b P1a P1b P2a P2b P3a P3b Bus Data D[7] Cb0[7] Y0[7] Cr0[7] Y1[7] Cb2[7] Y2[7] Cr2[7] Y3[7]

D[6] Cb0[6] Y0[6] Cr0[6] Y1[6] Cb2[6] Y2[6] Cr2[6] Y3[6] D[5] Cb0[5] Y0[5] Cr0[5] Y1[5] Cb2[5] Y2[5] Cr2[5] Y3[5] D[4] Cb0[4] Y0[4] Cr0[4] Y1[4] Cb2[4] Y2[4] Cr2[4] Y3[4] D[3] Cb0[3] Y0[3] Cr0[3] Y1[3] Cb2[3] Y2[3] Cr2[3] Y3[3] D[2] Cb0[2] Y0[2] Cr0[2] Y1[2] Cb2[2] Y2[2] Cr2[2] Y3[2] D[1] Cb0[1] Y0[1] Cr0[1] Y1[1] Cb2[1] Y2[1] Cr2[1] Y3[1] D[0] Cb0[0] Y0[0] Cr0[0] Y1[0] Cb2[0] Y2[0] Cr2[0] Y3[0]

YCrCb 8-bit

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CHRONTEL CH7008A

When IDF = 9, (YCrCb 8-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the

embedded sync will be similar to the CCIR656 convention, and the first byte of the ‘video timing reference code’

will be assumed to occur when a Cb sample would occur – if the video stream was continuous. This is delineated in

Table6 shown below.

Table 6. YCrCb Multiplexed Mode with Embedded Syncs

IDF#

Format

Pixel# P0a P0b P1a P1b P2a P2b P3a P3b Bus Data D[7] 1 0 0 S[7] Cb2[7] Y2[7] Cr2[7] Y3[7]

D[6] 1 0 0 S[6] Cb2[6] Y2[6] Cr2[6] Y3[6] D[5] 1 0 0 S[5] Cb2[5] Y2[5] Cr2[5] Y3[5] D[4] 1 0 0 S[4] Cb2[4] Y2[4] Cr2[4] Y3[4] D[3] 1 0 0 S[3] Cb2[3] Y2[3] Cr2[3] Y3[3] D[2] 1 0 0 S[2] Cb2[2] Y2[2] Cr2[2] Y3[2] D[1] 1 0 0 S[1] Cb2[1] Y2[1] Cr2[1] Y3[1] D[0] 1 0 0 S[0] Cb2[0] Y2[0] Cr2[0] Y3[0]

YCrCb 8-bit

In this mode, the S[7:0] byte contains the following data:

S[6] = F = 1 during field 2, 0 during field 1

S[5] = V = 1 during field blanking, 0 elsewhere

S[4] = H = 1 during EAV (the synchronization reference at the end of active video)

0 during SAV (the synchronization reference at the start of active video)

Bits S[7] and S[3-0] are ignored.

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CHRONTEL CH7007A

Functional Description

The CH7008 is a TV-output companion chip to graphics controllers providing digital output in either YCrCb or RGB format. This solution involves both hardware and software elements which work together to produce an optimum TV screen image based on the original computer generated pixel data. All essential circuitry for this conversion are integrated on chip. On chip circuitry includes memory, memory control, scaling, PLL, DAC, filters and NTSC/PAL encoder. All internal signal processing, including NTSC/PAL encoding, is performed using digital techniques to ensure that the high-quality video signals are not affected by drift issues associated with analog components. No additional adjustment is required during manufacturing.

CH7008 is ideal for PC motherboards, web browsers or VGA add-in boards where a minimum of discrete support components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation.

Architectural Overview

The CH7008 is a complete TV output subsystem which uses both hardware and software elements to produce an image on TV which is virtually identical to the image that would be displayed on a monitor. Simply creating a compatible TV output from a VGA input involves a relatively straightforward process. This process includes a standard conversion from RGB to YUV color space, converting from a non-interlaced to an interlaced frame sequence, and encoding the pixel stream into NTSC or PAL compliant format. However, creating an optimum computer-generated image on a TV screen involves a highly sophisticated process of scaling, deflickering, and filtering. This results in a compatible TV output that displays a sharp and subtle image, of the right size, with minimal artifacts from the conversion process.

As a key part of the overall system solution, the CH7008 software establishes the correct framework for the VGA input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600), the CH7008 software may be invoked to establish the appropriate TV output display. The software then programs the various timing parameters of the VGA controller to create an output signal that will be compatible with the chosen resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates, total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7008 can render a superior TV image without the added cost of a full frame buffer memory – normally used to implement features such as scaling and full synchronization.

The CH7008 hardware accepts digital RGB or YCrCb inputs, which are latched in synchronization with the pixel clock. These inputs are then color-space converted into YUV in 4-2-2 format, and stored in a line buffer memory. The stored pixels are fed into a block where scan-rate conversion, underscan scaling and 2-line, 3-line, 4-line or 5line vertical flicker filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to either NTSC or PAL scan rates; the vertical flicker filter eliminates flicker at the output while the underscan scaling reduces the size of the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through digital filters to minimize aliasing problems. The digital encoder receives the filtered signals and transforms them to composite and S-Video outputs, which are converted by the three 9-bit DACs into analog outputs.

Color Burst Generation*

The CH7008 allows the subcarrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator, leaving the subcarrier frequency independent of the sampling rate. As a result, the CH7008 may be used with any VGA chip (with an appropriate digital interface) since the CH7008 subcarrier frequency can be generated without being dependent on the precise pixel rates of VGA controllers. This feature is a significant benefit, since even a

±0.01% subcarrier frequency variation may be enough to cause some television monitors to lose color lock.

In addition, the CH7008 has the capability to genlock the color burst signal to the VGA horizontal sync frequency, which enables a fully synchronous system between the graphics controller and the television. When genlocked, the CH7008 can also stop “dot crawl” motion (for composite mode operation in NTSC modes) to eliminate the annoyance of moving borders. Both of these features are under programmable control through the register set.

Display Modes

The CH7008 display mode is controlled by three independent factors: input resolution, TV format, and scale factor, which are programmed via the display mode register. It is designed to accept input resolutions of 640x480, 800x600, 640x400 (including 320x200 scan-doubled output), 720x400 and 512x384.

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CHRONTEL CH7008A

Display Modes (continued)

It is designed to support output to either NTSC or PAL television formats. The CH7008 provides interpolated

scaling with selectable factors of 5:4, 1:1, 7:8, 5:6, 3:4 and 7:10 in order to support adjustable overscan or underscan

operation when displayed on a TV. This combination of factors results in a matrix of useful operating modes which

are listed in detail in Table7.

Table 7. CH7008 Display Modes

TV Format

Standard

NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC

PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL

Input

(active)

Scale

Factor

Active

TV Lines

Percent (1)

Overscan

Pixel

Clock

Horizontal

Total

Vertical

Resolution

640x480 1:1 640x480 7:8 640x480 5:6 800x600 5:6 800x600 3:4 800x600 640x400 5:4 500 16% 21.147 840 420 640x400 1:1 400 (8%) 26.434 840 525 640x400 7:8 350 (19%) 30.210 840 600 720x400 5:4 500 16% 23.790 945 420 720x400 1:1 400 (8%) 29.455 936 525 512x384 5:4 480 10% 20.140 800 420 512x384 1:1 384 (11%) 24.671 784 525

640x480 5:4 600 14% 21.000 840 500 640x480 1:1 480 (8%) 26.250 840 625 640x480 5:6 400 (29%) 31.500 840 750 800x600 1:1 600 14% 29.500 944 625 800x600 5:6 500 (4%) 36.000 960 750 800x600 3:4 450 (15%) 39.000 936 836 640x400 5:4 500 (4%) 25.000 1000 500 640x400 1:1 400 (29%) 31.500 1008 625 720x400 5:4 500 (4%) 28.125 1125 500 720x400 1:1 400 (29%) 34.875 1116 625 512x384 5:4 480 (8%) 21.000 840 500 512x384 1:1 384 (35%) 26.250 840 625

7:10

480 420 400 500 450

420 (3%) 47.832 1064 750

10% (3%) (8%) 16%

24.671 784 525

28.196 784 600

30.210 800 630

39.273 1040 630

43.636 1040 700

Total

(1) Note: Percent underscan is a calculated value based on average viewable lines on each TV format, assuming an average TV overscan of 10%. (Negative values) indicate modes which are operating in underscan.

For NTSC: 480 active lines - 10% (overscan) = 432 viewable lines (average) For PAL: 576 active lines - 10% (overscan) = 518 viewable lines (average)

The inclusion of multiple levels of scaling for each resolution have been created to enable optimal use of the CH7008 for different application needs. In general, underscan (modes where percent overscan is negative) provides an image that is viewable in its entirety on screen; it should be used as the default for most applications (e.g., viewing text screens, operating games, running productivity applications and working within Windows). Overscanning provides an image that extends past the edges of the TV screen, exactly like normal television programs and movies appear on TV, and is only recommended for viewing movies or video clips coming from the computer. In addition to the above mode table, the CH7008 also support interlaced input modes, both in CCIR 656 and proprietary formats (see Display Mode Register section).

Flicker Filter and Text Enhancement

The CH7008 integrates an advanced 2-line, 3-line, 4-line and 5-line (depending on mode) vertical deflickering filter circuit to help eliminate the flicker associated with interlaced displays. This flicker circuit provides an adaptive filter algorithm for implementing flicker reduction with selections of high, medium or low flicker content for both luma and chroma channels (see register descriptions). In addition, a special text enhancement circuit incorporates

201-0000-027 Rev 2.2, 9/30/99 11

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CHRONTEL CH7008A

Display Modes (continued)

additional filtering for enhancing the readability of text. These modes are fully programmable via I2C under the flicker filter register.

Internal Voltage Reference

An on chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a reference resistor at pin ISET, and register controlled divider, sets the output ranges of the DACs. The CH7008 bandgap reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal for PAL or NTSC-J, which is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor from ISET to ground is 360 ohms (though this may be adjusted in order to achieve a different output level). The gain setting for

DAC output is 1/48th. Therefore, for each DAC, the current output per LSB step is determined by the following equation:

= V(ISET)/ISET reference resistor * 1/GAIN

LSB

For DACG=0, this is: I For DACG=1, this is: I

Power Management

The CH7008 supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off and Composite Off to provide optimal power consumption for the application involved. Using the programmable power down modes accessed over the I2C port, the CH7008 may be placed in either Normal state, or any of the four power managed states, as listed below (see “Power Management Register” under the Register Descriptions section for programming information). To support power management, a TV sensing function (see “Connection Detect Register” under the Register Descriptions section) is provided, which identifies whether a TV is connected to either S-Video or composite. This sensing function can then be used to enter into the appropriate operating state (e.g., if TV is sensed only on composite, the S-Video Off mode could be set by software).

= 1.235/360 * 1/48 = 71.4 µA (nominal)

LSB

= 1.317/360 * 1/48 = 76.2 µA (nominal)

LSB

Table 8. Power Management

Operating State Functional Description

Normal (On): In the normal operating state, all functions and pins are active. Power Down: In the power-down state, most pins and circuitry are disabled.The DS/BCO pin

S-Video Off: Power is shut off to the unused DACs associated with S-Video outputs. Composite Off: In Composite-off state, power is shut off to the unused DAC associated with

Full Power Down: In this power-down state, all but the I2C circuits are disabled. This places the

will continue to provide either the VCO divided by K3, or 14.318 MHz out when selected as an output, and the P-OUT pin will continue to output a clock reference when in master clock mode.

CVBS output.

CH7008 in its lowest power consumption mode.

Luminance and Chrominance Filter Options

The CH7008 contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and SVideo outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown, the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and chrominance video bandwidth output is shown in Table9.

12 201-0000-027 Rev 2.2, 9/30/99

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CHRONTEL CH7008A

Table 9. Video Bandwidth

Mode Chrominance Luminance Bandwidth with Sin(X) /X (MHz)

CVBS S-Video S-Video

CBW[1:0] YCV YSV[1:0], YPEAK = 0 YSV[1:0], YPEAK = 1

00 01 10 11 0 0.62 0.68 0.80 0.95 2.26 3.37 2.26 3.37 5.23 2.57 4.44 5.23 1 0.78 0.85 1.00 1.18 2.82 4.21 2.82 4.21 6.53 3.21 5.56 6.53 2 0.53 0.58 0.68 0.81 1.93 2.87 1.93 2.87 4.46 2.19 3.79 4.46 3 0.65 0.71 0.83 0.99 2.36 3.52 2.36 3.52 5.46 2.68 4.64 5.46 4 0.83 0.91 1.07 1.27 3.03 4.51 3.03 4.51 7.00 3.44 5.95 7.00 5 1.03 1.13 1.32 1.57 3.75 5.59 3.75 5.59 8.68 4.27 7.38 8.68 6 0.70 0.77 0.90 1.07 2.56 3.81 2.56 3.81 5.92 2.91 5.04 5.92 7 0.87 0.95 1.12 1.33 3.17 4.72 3.17 4.72 7.33 3.60 6.23 7.33 8 0.74 0.81 0.95 1.13 2.69 4.01 2.69 4.01 6.22 3.06 5.29 6.22 9 0.93 1.02 1.20 1.42 3.39 5.05 3.39 5.05 7.84 3.85 6.67 7.84 10 0.63 0.68 0.80 0.95 2.28 3.39 2.28 3.39 5.26 2.59 4.48 5.26 11 0.78 0.86 1.00 1.19 2.84 4.24 2.84 4.24 6.58 3.23 5.59 6.58 12 0.89 0.98 1.15 1.36 3.25 4.84 3.25 4.84 7.52 3.70 6.39 7.52 13 0.62 0.68 0.80 0.95 2.26 3.37 2.26 3.37 5.23 2.57 4.44 5.23 14 0.78 0.85 1.00 1.18 2.82 4.21 2.82 4.21 6.53 3.21 5.56 6.53 15 0.93 1.02 1.20 1.42 3.39 5.05 3.39 5.05 7.84 3.85 6.67 7.84 16 0.64 0.71 0.83 0.98 2.35 3.50 2.35 3.50 5.43 2.67 4.62 5.43 17 0.74 0.81 0.95 1.13 2.70 4.02 2.70 4.02 6.24 3.07 5.30 6.24 18 0.79 0.87 1.02 1.21 2.89 4.31 2.89 4.31 6.68 3.29 5.68 6.68 19 0.77 0.85 1.00 1.18 2.82 4.20 2.82 4.20 6.53 3.21 5.55 6.53 20 0.95 1.03 1.22 1.44 3.44 5.13 3.44 5.13 7.97 3.92 6.77 7.97

21 22

23 0.86 0.94 1.11 1.31 3.13 4.66 3.13 4.66 7.24 3.56 6.16 7.24 24 0.94 1.03 1.21 1.44 3.43 5.11 3.43 5.11 7.94 3.90 6.75 7.94 25 0.71 0.78 0.91 1.08 2.58 3.85 2.58 3.85 5.97 2.94 5.08 5.97 26 0.71 0.78 0.91 1.08 2.58 3.85 2.58 3.85 5.97 2.94 5.08 5.97

1.02 1.12 1.32 1.56 3.73 5.56 3.73 5.56 8.63 4.24 7.34 8.63

0.77 0.85 0.99 1.18 2.82 4.20 2.82 4.20 6.52 3.20 5.54 6.52

0 1

00 01 1X 00 01 1X

The composite luminance and chrominance frequency response is depicted in Figures 5 through 7.

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CHRONTEL CH7008A

Luminance and Chrominance Filter Options (continued)

-6

-12

-18

<i>

< >

YCVdB

)

-24

-36

-42

0 1 2 3 4 5 6 7 8 9 10 11 12

2 3

n,i

7 8

,n i

10 11 12

(YCVdB

YSVdB

(YSVdB

<i>

Figure 5: Composite Luminance Frequency Response (YCV = 0)

-6

-12

-18

< >

)

-24

-30

-36

-42 0

,n i 6

Figure 6: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = 0)

14 201-0000-027 Rev 2.2, 9/30/99

Page 15

CHRONTEL CH7008A

Luminance and Chrominance Filter Options (continued)

-6

-12

-18

< >

UVfirdB

(UVfirdB

<i>

)

-24

-30

-36

-42

0 1

0 1 2 3 4 5 6 7 8 9 10 11 12

5 6

n,i

,n i 6

7 8 9

Figure 7: Chrominance Frequency Response

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CHRONTEL CH7008A

NTSC and PAL Operation

Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to characterize these outputs are listed in Table10 and shown in Figure8. (See Figures 11 through 16 for illustrations of composite and S-Video output waveforms).

CCIR624-3 Compliance

The CH7008 is predominantly compliant with the recommendations called out in CCIR624-3. The following are the only exceptions to this compliance:

• The frequencies of Fsc, Fh, and Fv can only be guaranteed in master mode, not in slave mode when the graphics device generates these frequencies.

• It is assumed that gamma correction, if required, is performed in the graphics device which establishes the color reference signals.

• All modes provide the exact number of lines called out for NTSC and PAL modes respectively, except mode 21, which outputs 800x600 resolution, scaled by 3:4, to PAL format with a total of 627 lines (vs. 625).

• Chroma signal frequency response will fall within 10% of the exact recommended value.

• Pulse widths and rise/fall times for sync pulses, front/back porches, and equalizing pulses are designed to approximate CCIR624-3 requirements, but will fall into a range of values due to the variety of clock frequencies used to support multiple operating modes.

Table 10. NTSC/PAL Composite Output Timing Parameters (in mS)

Symbol Description

A B C D E F G H

Front Porch Horizontal Sync Breezeway Color Burst Back Porch Black Active Video Black

Level (mV) Duration (uS)

NTSC PAL NTSC PAL

287 300

0 0 287 300 287 300 287 300 340 300 340 300 340 300

For this table and all subsequent figures, key values are:

Note: 1. ISET = 360 ohms; V(ISET) = 1.235V; 75 ohms doubly terminated load.

2. Durations vary slightly in different modes due to the different clock frequencies used.

3. Active video and black (F, G, H) times vary greatly due to different scaling ratios used in different modes.

4. Black times (F and H) vary with position controls.

1.49 - 1.51 1.48 - 1.51

4.69 - 4.72 4.69 - 4.71

0.59 - 0.61 0.88 - 0.92

2.50 - 2.53 2.24 - 2.26

1.55 - 1.61 2.62 - 2.71

0.00 - 7.50 0.00 - 8.67

37.66 - 52.67 34.68 - 52.01

0.00 - 7.50 0.00 - 8.67

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CHRONTEL CH7008A

A B C D E F G H

Figure 8: NTSC / PAL Composite Output

START

VSYNC

ANALOG

Start of

field 1

FIELD 1

VSYNC

523 524

520 521 522 523 524 525 1 2 3 4 5 6 7

261

258 259 260 261 262 263 264 265 266 267 268 269 272

523

520 521 522 523 524 525 1 2 3 4 5 6 7

261 262

258 259 260 261 262 263 264 265 266 267 268 269 272

524

262

525

263 264

1 2

Reference

ANALOG

sub-carrier phase

FIELD 2

color field 1

263

264

Start of field 2

Reference

ANALOG

sub-carrier phase

FIELD 1

color field 2

Start of

field 3

Reference

ANALOG

sub-carrier phase

FIELD 2

color field 3

Start of

field 4

Pre-equalizing pulse interval

265

Vertical sync

pulse interval

Line vertical

interval

t1+V

267 268 269

266

START

VSYNC

t2+V

4 5

t3+V

266 267 268

6 7 8

Post-equalizing

pulse interval

270

7 8 9

269 270

8 9

271 272 273 274 275

271

272

270 271

273

270 271

8 9

274

275

Reference sub-carrier phase

color field 4

Figure 9: Interlaced NTSC Video Timing

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CHRONTEL CH7008A

START

VSYNC

ANALOG

ANALOG FIELD 1

FIELD 1

BURST

BLANKING

INTERVALS

621 622 623 624 625 1 2 3 4 5 6 7620

ANALOG

ANALOG FIELD 2

FIELD 2

309 310 311 312 313 314 315 316 317 318 319 320 323308 322

ANALOG

ANALOG FIELD 3

FIELD 3

621 622 623 624 625 1 2 3 4 5 6 7620

ANALOG

ANALOG FIELD 4

FIELD 4

309 310 311 312 313 314 315 316 317 318 319 320308

BURST PHASE = REFERENCE PHASE = 135 RELATIVE TO U

BURST PHASE = REFERENCE PHASE = 135 RELATIVE TO U PAL SWITCH = 0, +V COMPONENT

PAL SWITCH = 0, +V COMPONENT

3 2

8 9 10

321

8 9 10

323322321

BURST PHASE = REFERENCE PHASE + 90 = 225 RELATIVE TO U

BURST PHASE = REFERENCE PHASE + 90 = 225 RELATIVE TO U PAL SWITCH = 1, - V COMPONENT

PAL SWITCH = 1, - V COMPONENT

°°

Figure 10: Interlaced PAL Video Timing

18 201-0000-027 Rev 2.2, 9/30/99

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CHRONTEL CH7008A

Color/Level mA V

White 26.66 1.000 Yellow 24.66 0.925

Cyan 21.37 0.801 Green 19.37 0.726

Magenta 16.22 0.608 Red 14.22 0.533

Blue 11.08 0.415 Black 9.08 0.340

Blank 7.65 0.287

Sync 0.00 0.000

Figure 11: NTSC Y (Luminance) Output Waveform (DACG = 0)

Color/Level mA V

Color bars:

Yellow

White

Magenta

Green

Cyan

Yellow

White

Black

Blue

Red

Magenta

Green

Cyan

Black

Blue

Red

White 26.75 1.003 Yellow 24.62 0.923

Cyan 21.11 0.792 Green 18.98 0.712

Magenta 15.62 0.586 Red 13.49 0.506

Blue 10.14 0.380 Blank/ Black 8.00 0.300

Sync 0.00 0.000

Figure 12: PAL Y (Luminance) Video Output Waveform (DACG = 1)

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CHRONTEL CH7008A

Color/Level mA V

Cyan/Red 25.80 0.968 Green/Magenta 25.01 0.938

Yellow/Blue 22.44 0.842

Peak Burst 18.08 0.678 Blank 14.29 0.536

Peak Burst 10.51 0.394

Yellow/Blue 6.15 0.230

Green/Magenta 3.57 0.134 Cyan/Red 2.79 0.105

Figure 13: NTSC C (Chrominance) Video Output Waveform (DACG = 0)

Color bars:

3.579545 MHz Color Burst (9 cycles)

Yellow

White

Cyan

Magenta

Green

Red

Black

Blue

Color/Level mA V

Cyan/Red 27.51 1.032 Green/Magenta 26.68 1.000

Yellow/Blue 23.93 0.897

Peak Burst 19.21 0.720 Blank 15.24 0.572

Peak Burst 11.28 0.423

Yellow/Blue 6.56 0.246

Green/Magenta 3.81 0.143 Cyan/Red 2.97 0.111

Figure 14: PAL C (Chrominance) Video Output Waveform (DACG = 1)

Color bars:

4.433619 MHz Color Burst (10 cycles)

Yellow

White

Cyan

Magenta

Green

Blue

Red

Black

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CHRONTEL CH7008A

Color/Level mA V

Peak Chrome 32.88 1.233

White 26.66 1.000

Peak Burst 11.44 0.429

Black 9.08 0.340 Blank 7.65 0.281

Peak Burst 4.45 0.145

Sync 0.00 0.000

Figure 15: Composite NTSC Video Output Waveform (DACG = 0)

Color bars:

Yellow

White

3.579545 MHz Color Burst (9 cycles)

Magenta

Green

Cyan

Red

Black

Blue

Color/Level

Peak Chrome 33.31 1.249

White 26.75 1.003

Peak Burst 11.97 0.449

Blank/Black 8.00 0.300

Peak Burst 4.04 0.151

Sync 0.00 0.000

Figure 16: Composite PAL Video Output Waveform (DACG = 1)

Color bars:

Yellow

White

4.433619 MHz Color Burst (10 cycles)

Magenta

Green

Cyan

Red

Black

Blue

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CHRONTEL CH7008A

I2C Port Operation

The CH7008 contains a standard I2C control port, through which the control registers can be written and read. This port is comprised of a two-wire serial interface, pins SD (bidirectional) and SC, which can be connected directly to the SDB and SCB buses as shown in Figure17.

The Serial Clock line (SC) is input only and is driven by the output buffer of the master device (also shown in Figure17). The CH7008 acts as a slave, and generation of clock signals on the bus is always the responsibility of the master device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the bus can be transferred up to 400 kbit/s.

+DVDD

SDB (Serial Data Bus) SCB (Serial Clock Bus)

SCLK OUT FROM MASTER

DATAN2 OUT MASTER

DATA IN MASTER

BUS MASTER

SCLK IN1

DATAN2 OUT

SLAVE

DATA IN1

SCLK IN2

DATAN2 OUT

DATA IN2

SLAVE

Figure 17: Connection of Devices to the Bus

Electrical Characteristics for Bus Devices

The electrical specifications of the bus devices’ inputs and outputs and the characteristics of the bus lines connected to them are shown in Figure17. A pull-up resistor (RP) must be connected to a 3.3V ± 10% supply. The CH7008 is a device with input levels related to DVDD.

Maximum and minimum values of pull-up resistor (RP)

The value of RP depends on the following parameters:

• Supply voltage

• Bus capacitance

• Number of devices connected (input current + leakage current = I

The supply voltage limits the minimum value of resistor RP due to the specified minimum sink current of 2mA at VOL

= 0.4 V for the output stages:

max

RP >= (VDD – 0.4) / 2 (RP in kΩ)

input

)

The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of RP due to the specified rise time. The equation for RP is shown below:

RP <= 103/C (where: RP is in kΩ and C, the total capacitance, is in pF)

The maximum HIGH level input current of each input/output connection has a specified maximum value of 10 µA. Due to the desired noise margin of 0.2VDD for the HIGH level, this input current limits the maximum value of RP.

The RP limit depends on VDD and is shown below:

RP <= (100 x VDD)/ I

(where: RP is in kΩ and I

input

is in µA)

22 201-0000-027 Rev 2.2, 9/30/99

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CHRONTEL CH7008A

Transfer Protocol

Both read and write cycles can be executed in “Alternating” and “Auto-increment” modes. Alternating mode expects a register address prior to each read or write from that location (i.e., transfers alternate between address and data). Auto-increment mode allows you to establish the initial register location, then automatically increments the register address after each subsequent data access (i.e., transfers will be address, data...). A basic serial port transfer protocol is shown in Figure18 and described below.

I2C

CH7008

1 - 8

Start

Condition

Device ID8R/W*9ACK

CH7008

acknowledge

Data

ACK

CH7008

acknowledge

Data

ACK

CH7008

acknowledge

Stop

Condition

Figure 18: Serial Port Transfer Protocol

1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the “START” condition. Transitions of address and data bits can only occur while SC is low.

2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the “STOP” condition.

3. Upon receiving the first START condition, the CH7008 expects a Device Address Byte (DAB) from the master device. The value of the device address is shown in the DAB data format below.

4. After the DAB is received, the CH7008 expects a Register Address Byte (RAB) from the master. The format of the RAB is shown in the RAB data format below (note that B7 is not used).

Device Address Byte (DAB)

B7 B6 B5 B4 B3 B2 B1 B0

1 1 1 0 1 0 1 R/W

R/W Read/Write Indicator

“0”: master device will write to the CH7008 at the register location specified by the address

AR[5:0]

“1”: master device will read from the CH7008 at the register location specified by the

address AR[5:0].

B7 B6 B5 B4 B3 B2 B1

1 AutoInc AR[5] AR[4] AR[3] AR[2] AR[1] AR[0]

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CHRONTEL CH7008A

Transfer Protocols (continued)

AutoInc Register Address Auto-Increment - to facilitate sequential R/W of registers.

“1”: Auto-Increment enabled (auto-increment mode). Write: After writing data into a register, the Address Register will automatically be

incremented by one.

Read: Before loading data from a register to the on-chip temporary register (getting ready to

be serially read), the Address Register will automatically be incremented by one.

However, for the first read after an RAB, the Address Register will not be changed. “0”: Auto-Increment disabled (alternating mode). Write: After writing data into a register, the Address Register will remain unchanged until a

new RAB is written. Read: Before loading data from a register to the on-chip temporary register (getting ready to

be serially read), the Address Register will remain unchanged.

AR[5:0] Specifies the Address of the Register to be Accessed.

This register address is loaded into the Address Register of the CH7008. The R/W access, which follows, is directed to the register specified by the content stored in the Address Register.

The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and AutoInc = 0,1.

CH7008 Write Cycle Protocols (R/W = 0)

Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the mastertransmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slavereceiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the HIGH period of the clock pulse. The CH7008 always acknowledges for writes (see Figure19). Note that the resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.

SD Data Output

By Master-Transmitter

SD Data Output

By the CH7008

SC from

Master

1 8 9

Start

Condition

not acknowledge

acknowledge

clock pulse for

acknowledgment

Figure 19: Acknowledge on the Bus

Figure20 shows two consecutive alternating write cycles for AutoInc = 0 and R/W = 0. The byte of information,

following the Register Address Byte (RAB), is the data to be written into the register specified by AR[5:0]. If AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on.

24 201-0000-027 Rev 2.2, 9/30/99

Page 25

CHRONTEL CH7008A

Condition

Start

CH7008

acknowledge

I2C

1 - 7

Device ID8R/W*9ACK

CH7008

acknowledge

1 - 8

RAB9ACK

CH7008

acknowledge

1 - 8

Data9ACK

CH7008

acknowledge

1 - 8

RAB9ACK

CH7008

acknowledge

1 - 8

Data9ACK

Stop

Condition

Note: The acknowledge is from the CH7008 (slave).

Figure 20: Alternating Write Cycles

If AutoInc = 1, then the register address pointer will be incremented automatically and subsequent data bytes will be written into successive registers without providing an RAB between each data byte. An Auto-increment write cycle is shown in Figure21.

1 - 7

CH7008

acknowledge

I2C

1 - 8

CH7008

acknowledge

1 - 8

CH7008

acknowledge

1 - 8

CH7008

acknowledge

Start Stop

Device ID8R/W*9ACK

RAB

ACK

Data

ACK Data

n+1

ACK

ConditionCondition

Note: The acknowledge is from the CH7008 (slave).

Figure 21: Auto-Increment Write Cycle

When the auto-increment mode is enabled (AutoInc is set to 1), the register address pointer continues to increment for each write cycle until AR[5:0] = 3F (3F is the address of the Address Register). The next byte of information represents a new auto-sequencing “Starting address”, which is the address of the register to receive the next byte. The auto-sequencing then resumes based on this new “Starting address”. The auto-increment sequence can be terminated any time by either a “STOP” or “RESTART” condition. The write operation can be terminated with a “STOP” condition.

CH7008 Read Cycle Protocols (R/W = 1)

If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter CH7008 releases the data line to allow the master to generate the STOP condition or the RESTART condition.

To read the content of the registers, the master device starts by issuing a “START” condition (or a “RESTART” condition). The first byte of data, after the START condition, is a DAB with R/W = 0. The second byte is the RAB with AR[5:0], containing the address of the register that the master device intends to read from in AR[5:0]. The master device should then issue a “RESTART” condition (“RESTART” = “START”, without a previous “STOP” condition). The first byte of data, after this RESTART condition, is another DAB with R/W=1, indicating the master’s intention to read data hereafter. The master then reads the next byte of data (the content of the register specified in the RAB). If AutoInc = 0, then another RESTART condition, followed by another DAB with R/W = 0 and RAB, is expected from the master device. The master device then issues another RESTART, followed by another DAB. After that, the master may read another data byte, and so on. In summary, a RESTART condition, followed by a DAB, must be produced by the master before each of the RAB, and before each of the data read events. Two consecutive alternating read cycles are shown in Figure22.

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CHRONTEL CH7008A

Transfer Protocols (continued)

Condition

1 - 7

Start

Device ID8R/W*9ACK

1 - 7

Device ID8R/W*9ACK

CH7008

acknowledge

I2C I2C

CH7008

acknowledge

I2C I2C

RAB

1 - 8

RAB

1 - 8

CH7008

acknowledge

ACK Restart

CH7008

acknowledge

9 10

ACK Restart

9 10

Condition

CH7008

acknowledge

1 - 7

Device ID8R/W*9ACK

CH7008

acknowledge

1 - 7

Device ID8R/W*9ACK

1 - 8

Data

Master does not acknowledge

1 - 8

Data

Master

does not

acknowledge

ACK

Restart

Condition

Stop

Condition

Figure 22: Alternating Read Cycle

If AutoInc = 1, then the address register will be incremented automatically and subsequent data bytes can be read from successive registers, without providing a second RAB.

Master does not acknowledge

CH7008

acknowledge

CH7008

acknowledge

CH7008

acknowledge

Master

acknowledge

just before Stop condition

I2C

Condition

1 - 7

Start

Device ID8R/W*9ACK

1 - 8

RAB

9 10

ACK Restart

1 - 7

Device ID8R/W*9ACK

Condition

1 - 8

Data

1 - 8

ACK

Data

n+1

ACK

Stop

Condition

Figure 23: Auto-increment Read Cycle

When the auto-increment mode is enabled (AutoInc is set to 1), the Address Register will continue incrementing for each read cycle. When the content of the Address Register reaches 2A, it will wrap around and start from 00h again. The auto increment sequence can be terminated by either a “STOP” or “RESTART” condition. The read operation can be terminated with a “STOP” condition. Figure23 shows an auto-increment read cycle terminated by a STOP or RESTART condition.

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Registers and Programming

The CH7008 is a fully programmable device, providing for full functional control through a set of registers accessed from the I2C port. The CH7008 contains a total of 37 registers, which are listed in Table11 and described in detail under Register Descriptions. Detailed descriptions of operating modes and their effects are contained in the previous section, Functional Description. An addition (+) sign in the Bits column below signifies that the parameter contains more than 8 bits, and the remaining bits are located in another register.

Table 11. Register Map

Display Mode DMR 00H 8 Display mode selection Flicker Filter FFR 01H 6 Flicker filter mode selection Video Bandwidth VBW 03H 8 Luma and chroma filter bandwidth selection Input Data Format IDF 04H 6 Data format and bit-width selections Clock Mode CM 06H 8 Start Active Video SAV 07H 8+ Position Overflow PO 08H 3 Black Level BLR 09H 8 Black level adjustment input latch clock edge select

Horizontal Position

Vertical Position VPR 0BH 8+

Sync Polarity Power Management PMR 0EH 5 Enables power saving modes Connection Detect CDR 10H 4 Detection of TV presence Contrast Enhancement CE 11H 3 Contrast enhancement setting PLL M and N extra bits MNE 13H 5 Contains the MSB bits for the M and N PLL values PLL-M Value PLLM 14H 8+ Sets the PLL M value - bits (7:0) PLL-N Value PLLN 15H 8+ Sets the PLL N value - bits (7:0) Buffered Clock BCO 17H 6 Determines the clock output at pin 41 Subcarrier Frequency

Adjust PLL and Memory Control PLLC 20H 6 Controls for the PLL and memory sections CIV Control CIVC 21H 5 Control of CIV value Calculated Fsc Increment

Value Version ID VID 25H 8 Device version number Test TR 26H -

Address AR 3FH 6 Current register being addressed

HPR 0AH 8+ Enables horizontal movement of displayed image on

SPR 0DH 4 Determines the horizontal and vertical sync polarity

FSCI 18H -1FH 4 or 8

CIV 21H -

24H

29H

each

8 each Readable register containing the calculated

30 Reserved for test (details not included herein)

Sets the clock mode to be used Active video delay setting MSB bits of position values

TV Enables vertical movement of displayed image on

Determines the subcarrier frequency

subcarrier increment value

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Table 12. I

C Alternate Register Map

00H IR2 IR1 IRO VOS1 VOS0 SR2 SR1 SR0 01H FC1 FC0 FY1 FY0 FT1 FT0 02H 03H FLFF CVBW CBW1 CBW0 YPEAK YSV1 YSV0 YCV 04H DACG Reserved IDF3 IDF2 IDF1 IDF0 05H 06H CFRB M/S* Reserved MCP XCM1 XCM0 PCM1 PCM0 07H SAV7 SAV6 SAV5 SAV4 SAV3 SAV2 SAV1 SAV0 08H SAV8 HP8 VP8 09H BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0 0AH HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 0BH VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 0CH 0DH DES SYO VSP HSP 0EH SCART Reset* PD2 PD1 PD0 0FH 10H YT CT CVBST SENSE 11H CE2 CE1 CE0 12H 13H Reserved Reserved N9 N8 M8 14H M7 M6 M5 M4 M3 M2 M1 M0 15H N7 N6 N5 N4 N3 N2 N1 N0 16H 17H SHF2 SHF1 SHF0 SCO2 SCO1 SCO0 18H FSCI31 FSCI30 FSCI29 FSCI28 19H FSCI27 FSCI26 FSCI25 FSCI24 1AH FSCI23 FSCI22 FSCI21 FSCI20 1BH GPIOIN1 GPIOIN0 DVDD2 P-OUTP FSCI19 FSCl18 FSCl17 FSCl16 1CH GOENB1 GOENB0 DSM DSEN FSCI15 FSCl14 FSCl13 FSCI12 1DH FSCI11 FSCl10 FSCl9 FSCI8 1EH FSCI7 FSCI6 FSCI5 FSCI4 1FH FSCI3 FSCI2 FSCI1 FSCI0 20H PLLCPl PLLCAP PLLS PLL5VD PLL5VA MEM5V 21H CIV25 CIV24 ClVH1 ClVH0 AClV 22H CIV23 CIV22 CIV21 CIV20 CIV19 CIV18 CIV17 CIV16 23H CIV15 CIV14 CIV13 CIV12 CIV11 CIV10 CIV9 CIV8 24H CIV7 CIV6 CIV5 CIV4 CIV3 CIV2 CIV1 CIVO 25H VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 26H TS3 TS2 TS1 TS0 RSA BST NST TE 27H MS2 MS1 MSO MTD YLM8 CLM8 28H YLM7 YLM6 YLM5 YLM4 YLM3 YLM2 YLM1 YLM0 29H CLM7 CLM6 CLM5 CLM4 CLM3 CLM2 CLM1 CLM0 3FH Reserved Reserved AR5 AR4 AR3 AR2 AR1 AR0

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Display Mode Register Address: 00H

Bits: 8

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

This register provides programmable control of the CH7008 display mode, including input resolution (IR[2:0]), output TV standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according to the table below (default is 640x480 input, NTSC output, 7/8’s scaling).

Table 13. Display Modes

IR2 IR1 IR0 VOS1 VOS0 SR2 SR1 SR0 R/W R/W R/W R/W R/W R/W R/W R/W 0 1 1 0 1 0 1 0

Input Data Format

Mode IR[2:0]

0 000 00 000 512x384 840x500 PAL 5/4 21.000000 1 000 00 001 512x384 840x625 PAL 1/1 26.250000 2 000 01 000 512x384 800x420 NTSC 5/4 20.139860 3 000 01 001 512x384 784x525 NTSC 1/1 24.671329 4 001 00 000 720X400 1125X500 PAL 5/4 28.125000 5 001 00 001 720x400 1116x625 PAL 1/1 34.875000 6 001 01 000 720x400 945x420 NTSC 5/4 23.790210 7 001 01 001 720x400 936x525 NTSC 1/1 29.454545 8 010 00 010 640x400 1000x500 PAL 5/4 25.000000 9 010 00 001 640x400 1008x625 PAL 1/1 31.5000000 10 010 01 000 640x400 840x420 NTSC 5/4 21.146853 11 010 01 001 640x400 840x525 NTSC 1/1 26.433566 12 010 01 010 640x400 840x600 NTSC 7/8 30.209790 13 011 00 000 640x480 840x500 PAL 5/4 21.000000 14 011 00 001 640x480 840x625 PAL 1/1 26.250000 15 011 00 011 640x480 840x750 PAL 5/6 31.5000000 16 011 01 001 640x480 784x525 NTSC 1/1 24.671329 17 011 01 010 640x480 784x600 NTSC 7/8 28.195804 18 011 01 011 640x480 800x630 NTSC 5/6 30.209790 19 100 00 001 800x600 944x625 PAL 1/1 29.500000 20 100 00 011 800x600 960x750 PAL 5/6 36.0000000 21 100 00 100 800x600 936x836 PAL 3/4 39.000000 22 100 01 011 800x600 1040x630 NTSC 5/6 39.272727 23 100 01 100 800x600 1040x700 NTSC 3/4 43.636364 24 100 01 101 800x600 1064x750 NTSC 7/10 47.832168 25* 101 00 001 720x576 864x625 PAL 1/1 13.500000 26* 101 01 001 720x480 858x525 NTSC 1/1 13.500000 * Interlaced modes of operation. (For those modes, some functions will be bypassed. For details, please contact the

application department.)

VOS [1:0]

SR [2:0]

(Active Video)

Total Pixels/Line x Total Lines/Frame

Output Format Scaling

Pixel Clock (MHz)

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VOS[1:0] Output Format

00 01 10 11 PAL NTSC PAL-M NTSC-J

Flicker Filter Register Symbol: FFR

Address: 01H Bits: 6

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

The flicker filter register provides for adjusting the operation of the various filters used in rendering the on-screen image. Adjusting settings between minimal and maximal values enables optimization between sharpness and flicker content. The FC[1:0] bits determine the settings for the chroma channel. The FT[1:0] bits determine the settings for the text enhancement circuit. The FY[1:0] bits determine the settings for the luma channel. In addition, the Chroma channel filtering includes a setting to enable the chroma dot crawl reduction circuit.

Note: When writing to register O1H, FY[1:0] is bits 3:2. FT[1:0] is bits 1:0. When reading from the register O1H, FY

[1:0] is bits 1:0 and FT[1:0] is bits 3:2.

Table 14. Flicker Filter Settings

FC1 FC0 FY1 FY0 FT1 FT0 R/W R/W R/W R/W R/W R/W 1 1 0 0 1 0

FY[1:0] Settings for Luma Channel

00 Minimal Flicker Filtering 01 Slight Flicker Filtering 10 Maximum Flicker Filtering 11 Invalid

FT[1:0] Settings for Text Enhancement Circuit

00 Maximum Text Enhancement 01 Slight Text Enhancement 10 Minimum Text Enhancement 11 Invalid

FC[1:0] Settings for Chroma Channel

00 Minimal Flicker Filtering 01 Slight Flicker Filtering 10 Maximum Flicker Filtering 11 Enable Chroma DotCrawl Reduction

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Video Bandwidth Register

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

This register enables the selection of alternative filters for use in the luma and chroma channels. There are currently four filter options defined for the chroma channel, four filter options in the S-Video luma channel and two filter options in the composite luma channel. The Tables 15 and 16 below show the various settings.

Table 15. Luma Filter Bandwidth

YCV Luma Composite Video Filter Adjust

0 Low bandwidth 1 High bandwidth YSV[1:0] Luma S-Video Filter Adjust 00 Low bandwidth 01 Medium bandwidth 10 High bandwidth 11 Reserved

YPEAK Disables the Y-peaking circuit

0 Disables the peaking filter in luma s-video channel 1 Enables the peaking filter in luma s-video channel

FLFF CVBW CBW1 CBW0 YPEAK YSV1 YSV0 YCV R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0

Symbol: VBW Address: 03H

Bits: 8

Table 16. Chroma Filter Bandwidth

CBW[1:0] Chroma Filter Adjust

0 0 Low bandwidth 0 1 Medium bandwidth 1 0 Med-high bandwidth 1 1 High bandwidth

Bit 6 (CVBW) outputs the S-Video luma signal on both the S-Video luma output and the CVBS output. A 1 in this location enables the output of a black and white image on composite video, thereby eliminating the degrading effects of the color signal (such as dot crawl or false colors), which is useful for viewing text with high accuracy.

Bit 7 (FLFF) controls the flicker filter used in the 7/10’s scaling modes. In these scaling modes, setting FLFF to 1 causes a five line flicker filter to be used. The default setting of 0 uses a four line flicker filter.

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Input Data Format Register Symbol: IDF

Address: 04H Bits: 6

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

This register sets the variables required to define the incoming pixel data stream.

Table 17. Input Data Format

IDF[3:0] Description

0000 Not available 0001 Not available 0010 Not available 0011 Not available 0100 12-bit multiplexed RGB (24-bit color) input (“C” multiplex scheme) 0101 12-bit multiplexed RGB (24-bit color) input (“I” multiplex scheme) 0110 Not available 0111 8-bit multiplexed RGB (16-bit color, 565) input 1000 8-bit multiplexed RGB (15-bit color, 555) input 1001-1111 8-bit multiplexed YCrCb (24-bit color) input (Y, Cr and Cb are multiplexed)

DACG Reserved IDF3 IDF2 IDF1 IDF0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0

Reserved (bit 5): This bit should be set to 0. DACG (bit 6): This bit controls the gain of the D/A converters. When DACG=0, the nominal DAC current is 71

µA, which provides the correct levels for NTSC and PAL-M. When DACG=1, the nominal DAC current is 76µA,

which provides the correct levels for PAL and NTSC-J.

Clock Mode Register Symbol: CM

Address: 06H Bits: 8

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

The setting of the clock mode bits determines the clocking mechanism used in the CH7008. The clock modes are shown in the table below. PCM controls the frequency of the P-OUT clock, and XCM identifies the frequency of the XCLK input clock.

CFRB M/S* Reserved MCP XCM1 XCM0 PCM1 PCM0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 1 0 0 0 0

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Note: Although it is possible to set the XCM [1:0] and PCM[1:0] values independent of the input data format, there are only certain combinations of input data format, XCM and PCM, that will result in valid data being demultiplexed at the input of the device. Refer to the “Input Data Format Register” for these combinations.

Note: Display modes 25 and 26 must use a 2X multiplexed input data format and a 2X XCLK.

Table 18. Input Data Format Register

XCM[1:0] PCM[1:0] XCLK P-Out Input Data Modes Supported

00 00 1X 1X 4, 5, 7, 8, 9 00 01 1X 2X 4, 5, 7, 8, 9 00 1X 1X 3X 4, 5, 7, 8, 9 01 00 2X 1X 4, 5, 7, 8, 9 01 01 2X 2X 4, 5, 7, 8, 9 01 1X 2X 3X 4, 5, 7, 8, 9

The Clock Mode Register also contains the following bits:

• MCP (bit 4) determines which edge of the pixel clock output will be used to latch input data. Zero selects the negative edge, one selects the positive edge.

• M/S* (bit 6) determines whether the device operates in master or slave clock mode. In master mode (1), the

14.31818MHz clock is used as a frequency reference to the PLL. In slave mode (0) the XCLK input is used as a reference to the PLL, and is divided by the value specified by XCM[1:0]. The divide by N and M are forced to one.

• CFRB (bit 7) sets whether the chroma subcarrier free-runs, or is locked to the video signal. One causes the subcarrier to lock to the TV vertical rate, and should be used when the ACIV bit is set to zero. Zero causes the subcarrier to free-run, and should be used when the ACIV bit is set to one.

Start Active Video Register Symbol: SAV

Address: 07H Bits: 8

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

This register sets the delay in pixel increments from leading edge of horizontal sync, or the rising edge of data start, to the start of active video. The entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value contained in the position overflow register, bit SAV8. This is decoded as a whole number of pixels, which can be set anywhere between 0 and 511 pixels. Therefore, in any 2X clock mode, the number of 2X clocks from the leading edge of sync to the first active data must be a multiple of two clocks. In any 3X clock mode, the number of 3X clocks from the leading edge of sync to the first active data must be a multiple of three clocks. When using the DS/BCO pin as a data start input, this register should be set to decimal value 11.

SAV7 SAV6 SAV5 SAV4 SAV3 SAV2 SAV1 SAV0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0

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Position Overflow Register Symbol: PO

Address: 08H Bits: 3

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

This position overflow register contains the MSB values for the SAV, HP and VP values, as follows:

• VP8 (bit 0) is the MSB of the vertical position value (see explanation under “Vertical Position Register”).

• HP8 (bit 1) is the MSB of the horizontal position value (see explanation under “Horizontal Position Register”).

• SAV8 (bit 2) is the MSB of the start of active video value (see explanation under “Start Active Video Register”).

Black Level Register Symbol: BLR

SAV8 HP8 VP8 R/W R/W R/W 0 0 0

Address: 09H Bits: 8

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0 R/W R/W R/W R/W R/W R/W R/W R/W 0 1 1 1 1 1 1 1

This register sets the black level. The luminance data is added to this black level, which must be set between 90 and 208, with the default value being 127. Recommended values for NTSC and PAL-M are 127, 105 for PAL and 100 for NTSC-J.

Horizontal Position Register Symbol: HPR

Address: 0AH Bits: 8

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

The horizontal position register is used to shift the displayed TV image in a horizontal direction (left or right) to achieve a horizontally centered image on screen. The entire bit field, HP[8:0] is comprised of this register HP[7:0] plus the MSB value contained in the position overflow register, bit HP8. Increasing this value moves the displayed image position RIGHT; decreasing this value moves the displayed image position LEFT. Each increment moves the image position by 4 input pixels.

HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0

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Vertical Position Register Symbol: VPR

Address: 0BH Bits: 8

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

This register is used to shift the displayed TV image in a vertical direction (up or down) to achieve a vertically centered image on screen. This bit field, VP[8:0] represents the TV line number (relative to the VGA vertical sync) used to initiate the generation and insertion of the TV vertical interval (i.e., the first sequence of equalizing pulses). Increasing values delay the output of the TV vertical sync, causing the image position to move UP on the TV screen. Decreasing values, therefore, move the image position DOWN. Each increment moves the image position by one TV lines (approximately 4 input lines). The maximum value that should be programmed into the VP[8:0] value is the number of TV lines minus one, divided by two (262, 312 or 313). When panning the image up, the number should be increased until (TVLPF-1) /2 is reached; the next step should be to reset the register to zero. When panning the image down the screen, the VP[8:0] value should be decremented until the value zero is reached. The next step should set the register to (TVLPF-1) /2, and then decrementing can continue. If this value is programmed to a number greater than (TV lines per frame-1) /2, a TV vertical SYNC will not be generated.

VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0

Sync Polarity Register Symbol: SPR

Address: 0DH Bits: 4

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

0 0 0 0

This register provides selection of the synchronization signal input to, or output from, the CH7008.

• HSP (bit 0) is Horizontal Sync Polarity - an HSP value of zero means the horizontal sync is active low and a value of one means the horizontal sync is active high.

• VSP (bit 1) is Vertical Sync Polarity - a VSP value of zero means the vertical sync is active low and a value of one means the vertical sync is active high.

• SYO (bit 2) is Sync Direction - a SYO value of zero means that H and V sync are input to the CH7008. A value of one means that H and V sync are output from the CH7008.

• DES (bit 3) is Detect Embedded Sync - a DES value of zero means that H and V sync will be obtained from the direct pin inputs. A DES value of one means that H and V sync will be detected from the embedded codes on the pixel input stream. Note that this will only be valid for the YCrCb input modes.

Note: When sync direction is set to be an output, horizontal sync will use a fixed pulse width of 64 pixels and vertical sync will use a fixed pulse width of 1 line.

DES SYO VSP HSP R/W R/W R/W R/W

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Power Management Register Symbol: PMR

Address: 0EH Bits: 5

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

0 1 1 0 1

This register provides control of the power management functions, a software reset (Reset*) and the SCART output enable. The CH7008 provides programmable control of its operating states, as described in the table below.

Table 19. Power Management

PD[2:0] Operating State Functional Description

000 Composite Off CVBS DAC is powered down. 001 Power Down Most pins and circuitry are disabled (except for the buffered clock outputs

010 S-Video Off S-Video DACs are powered down. 011 Normal (On) All circuits and pins are active. 1XX Full Power Down All circuitry is powered down except I2C circuit.

which are limited to the 14MHz output and VCO divided outputs).

SCART Reset* PD2 PD1 PD0 R/W R/W R/W R/W R/W

Reset* (bit 3) is soft reset. Setting this bit will reset all circuitry requiring a power on reset, except for this bit itself and the I2C state machines.

SCART (bit 4) is the SCART enable. Setting SCART = 0 means the CH7008 will operate normally, outputting Y/C and CVBS from the three DACs. SCART=1 enables SCART output, which will cause R, G and B to be output from the DACs and composite sync from the CSYNC pin.

Note: For complete details regarding the operation of these modes, see the Power Management in Functional Description sections.

Connection Detect Register Symbol: CDR

Address: 10H Bits: 4

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

0 0 0 0

R R R W

The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or Composite video outputs. The status bits, YT, CT, and CVBST correspond to the DAC outputs for S-Video (Y and C outputs) and Composite video (CVBS), respectively. However, the values contained in these status bits are NOT VALID until a sensing procedure is performed. Use of this register requires a sequence of events to enable the sensing of outputs, then reading out the applicable status bits. The detection sequence works as follows:

YT CT CVBST SENSE

1. Ensure the power management register bits 2-0 are set to 011 (normal mode).

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2. Ensure that the XCLK and XCLK* input pins are receiving clock signals (alternatively, XCLK* can be connected to the VREF pin).

3. Set the SENSE bit to a 1. This forces a constant current output onto the Y, C, and CVBS outputs. Note that during SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted.

4. Reset the SENSE bit to 0. This triggers a comparison between the voltage sensed on these analog outputs and the reference value expected (V

threshold

value, it is considered connected, if it is above this voltage it is considered unconnected. During this step, each of the three status bits corresponding to individual analog outputs will be set if they are NOT connected.

5. Read the status bits. The status bits Y, C and CVBST (corresponding to S-Video Y and C outputs and composite video) now contain valid information which can be read to determine which outputs are connected to a TV. Again, a “0” indicates a valid connection, a “1” indicates an unconnected output.

Contrast Enhancement Register Symbol: CE

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

0 1 1

= 1.235V). If the measured voltage is below this threshold

Address: 11H Bits: 3

CE2 CE1 CE0

R/W R/W R/W

This register provides control of the contrast enhancement feature of the CH7008, according to the table below. At a setting of 000, the video signal will be pulled towards the maximum black level. As the value of CE[2:0] is increased, the amount that the signal is pulled towards black is decreased until unity gain is reached at a setting of

011. From this point on, the video signal is pulled towards the white direction, with the effect increasing with

increasing settings of CE[2:0].

Table 20. Contrast Enhancement Function

CE[2:0] Description (all gains limited to 0-255)

000 Contrast enhancement gain 3 Y 001 Contrast enhancement gain 2 Y 010 Contrast enhancement gain 1 Y 011 Normal mode Y 100 Contrast enhancement gain 1 Y 101 Contrast enhancement gain 2 Y 110 Contrast enhancement gain 3 Y 111 Contrast enhancement gain 4 Y

= (1/1)*(Yin-0) = Normal Contrast

out

= (5/4)*(Yin-102) = Enhances Black

out

= (9/8)*(Yin-57)

out

= (17/16)*(Yin-30)

out

= (17/16)*(Yin-0)

out

= (9/8)*(Yin-0)

out

= (5/4)*(Yin-0)

out

= (3/2)*(Yin-0) = Enhances White

out

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256

224

192

160

128

0 32 64 96 128 160 192 224 256

Figure 24: Luma Transfer Function at different contrast enhancement settings.

PLL Overflow Register Symbol: MNE

Address: 13H Bits: 5

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

0 0 0 0 0

Reserved Reserved N9 N8 M8 R/W R/W R/W R/W R/W

The PLL Overflow Register contains the MSB bits for the’M’ and ’N’ values, which will be described in the PLL-M and PLL-N registers, respectively. The reserved bits should not be written to.

PLL M Value Register Symbol: PLLM

Address: 14H Bits: 8

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

The PLL M value register determines the division factor applied to the frequency reference clock before it is input to the PLL phase detector when the CH7008 is operating in master mode. In slave mode, an external pixel clock is used instead of the frequency reference, and the division factor is determined by the XCM[3:0] value. This register contains the lower 8 bits of the complete 9-bit M value.

M7 M6 M5 M4 M3 M2 M1 M0 R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 0 0 0 0 1

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PLL N Value Register Symbol: PLLN

Address: 15H Bits: 8

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL phase detector, when the CH7008 is operating in master mode. In slave mode, the value of ‘N’ is always 1. This register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a master mode and is calculated according to the equation below:

When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table below

Table 21. M and N Values for Each Mode

N7 N6 N5 N4 N3 N2 N1 N0 R/W R/W R/W R/W R/W R/W R/W R/W 1 0 0 0 0 0 0 0

Fpixel = Fref* [(N+2) / (M+2)]

Mode VGA Resolution, TV

Standard, Scaling Ratio

0 512x384, PAL, 5:4 20 13 1 512x384, PAL, 1:1 9 2 512X384, NTSC, 5:4 126 3 512X384, NTSC, 1:1 110 4 720X400, PAL, 5:4 53 5 720X400, PAL, 1:1 339 6 720X400, NTSC, 5:4 106 7 720X400, NTSC, 1:1 70 8 640X400, PAL, 5:4 108

9 640X400, PAL, 1:1 9 10 640X400, NTSC, 5:4 94 11 640x400, NTSC, 1:1 22 12 640X400, NTSC, 7:8 190 13 640X480, PAL, 5:4 20

N 10-

bits

M 9-

bits

Mode VGA Resolution, TV

Standard, Scaling Ratio

14 640x480, PAL, 1:1 9 4

4 15 640X480, PAL, 5:6 9 3 89 16 640X480, NTSC, 1:1 110 63 63 17 640X480, NTSC, 7:8 126 63 26 18 640X480, NTSC, 5:6 190 89

138 19 800X600, PAL, 1:1 647 313

63 20 800X600, PAL, 5:6 86 33 33 21 800X600, PAL, 3:4 284 103 61 22 800X600, NTSC, 5:6 94 33

3 23 800X600, NTSC, 3:4 62 19 63 24 800X600, NTSC, 7:10 302 89 11 25 720X576, PAL, 1:1 31 33 89 26 720X480, NTSC, 1:1 31 33 13

N 10-

bits

Buffered Clock Output Register Symbol: BCO

Address: 17H Bits: 6

M 9-

bits

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

SHF2 SHF1 SHF0 SCO2 SCO1 SCO0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0

When this pin is selected to be an output, the buffered clock output register determines which clock is selected to be output at the DS/BCO clock output pin and what frequency value is output when a VCO derived signal is output. The tables below show the possible outputs.

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Table 22. Clock Output Selection

SCO[2:0] Buffered Clock Output

000 14MHz crystal 001 (for test use only) 010 VCO divided by K3 (see Table23) 011 Field ID signal 100 (for test use only) 101 (for test use only) 110 TV horizontal sync (for test use only) 111 TV vertical sync (for test use only)

Table 23. K3 Selection

SHF[2:0] K3

000 2.5 010 3.5 011 4 100 4.5 101 5 110 6 111 7

Subcarrier Value Registers Symbol: FSCI

Address: 18H - 1FH Bits: 4 or 8 each

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

The lower four bits of registers 18H through 1FH contain a 32-bit value which is used as an increment value for the ROM address generation circuitry. The bit locations are specified as the following:

18H FSCI[31:28] 19H FSCI[27:24] 1AH FSCI[23:20] 1BH FSCI[19:16] 1CH FSCI[15:12] 1DH FSCI[11:8] 1EH FSCI[7:4] 1FH FSCI[3:0]

FSCI# FSCI# FSCI# FSCI# R/W R/W R/W R/W

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When the CH7008 is operating in the master clock mode, the tables below should be used to set the FSCI registers. When using these values, the ACIV bit in register 21H should be set to “0” and the CFRB bit in register 06H should be set to “1”.

Table 24. FSCI Values (525-Line Modes)

Mode

2 763,363,328 763,366,524 762,524,467 3 623,153,737 623,156,346 622,468,953 6 574,429,782 574,432,187 573,798,541

7 463,962,517 463,964,459 463,452,668 10 646,233,505 646,236,211 645,523,358 11 516,986,804 5165,988,968 516,418,687 12 452,363,454 452,365,347 451,866,351 16 623,153,737 623,156,346 622,468,953 17 545,259,520 545,261,803 544,660,334 18 508,908,885 508,911,016 508,349,645 22 521,957,831 521,960,016 521,384,251 23 469,762,048 469,764,015 469,245,826 24 428,554,851 438,556,645 428,083,911 26 569,408,543 569,410,927 568,782,819

NTSC

“Normal Dot Crawl”

NTSC

“No Dot Crawl”

“Normal Dot Crawl”

Table 25. FSCI Values (625-Line Modes)

Mode

0 806,021,060 651,209,077

1 644,816,848 520,967,262

4 601,829,058 486,236,111

5 485,346,014 392,125,896

8 677,057,690 547,015,625

9 537,347,373 434,139,385 13 806,021,060 651,209,077 14 644,816,848 520,967,262 15 537,347,373 434,139,385 19 645,499,916 521,519,134 20 528,951,320 427,355,957 21 488,262,757* 394,482,422 25 705,268,427 569,807,942

PAL

“Normal Dot Crawl”

PAL-N

“Normal Dot Crawl”

PAL-M

When the CH7008 is operating in the slave clock mode, the ACIV bit in register 21H should be set to “1” and the CFRB bit in register 06H should be set to “0”.

*Note: For reduced cross-color and cross-luminance artifacts, a value of 488,265,597 can be used with CFRB = "0" & ACIV = "0".

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Symbol: Address: 1BH Bits: 8

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

Register 1BH, bit 4 (P-OUTP) controls the polarity of the P-OUT pin. Register 1BH, bit 5 controls the P-OUT drive level, and should be set to 0 when DVDD2 is 1.8V, and set

to 1 when DVDD2 is 3.3V. Register 1BH, bits 7 and 6 control the GPIO pins. When the corresponding GOENB bits are low, these

registers values are driven out of the GPIO pins. When the corresponding GOENB bits are high, these registers values can be read to determine the level forced into the GPIO pins.

GPIOIN1 GPIOIN0 DVDD2 P-OUTP FSCI19 FSCI18 FSCI17 FSCI16 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0

Symbol: Address: 1CH Bits: 6

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

GOENB1 GOENB0 DSM DSEN FSCI15 FSCI14 FSCI13 FSCI12 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 0 0 0 0

Register 1CH, bit 4 controls whether the Data Start pin or the Horizontal Sync pin is used to determine the start of active video. When this bit is low, the pin continues to operate as the BCO pin described in the BCO register section. When this bit is high the pin becomes an input for the Data Start signal. A value of 0 is recommended.

Register 1CH, bit 5 determines how the Data Start input is used. A value of 1 is recommended. Register 1CH, bits 7and 6 control the GPIO pins direction. When a GOENB bit is low, the corresponding

GPIO pin is an output pin. When a GOENB bit is high, the corresponding GPIO pin can be read to determine the level forced into it.

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CHRONTEL CH7008A

PLL Control Register Symbol: PLLC

Address: 20H Bits: 6

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

The following PLL and memory controls are available through the PLL control register: MEM5V MEM5V should be set to 0 when DVDD is 3.3 volts, and 1 when DVDD is 5 volts. PLL5VA PLL5VA is set to 1 when AVDD is 5 volts. PLL5VD PLL5VD is set to 1 when DVDD is 5 volts. A value of 0 is used when DVDD is 3.3 volts (default). PPLLS When the PLL5VA is 1 PLLS should be 1. When PLL5VA is 0 PLLS should be 0. PLLCAP PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs

PLLCPI PLLCAP PLLS PLL5VD PLL5VA MEM5V R/W R/W R/W R/W R/W R/W 0 0 1 0 1 0

Mode is shown below.

PLLCPI The default value should be used.

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Table 26. PLL Capacitor Setting

Mode

0 1 1 1 2 1 3 0 4 1 5 0 6 1 7 1 8 0

9 1 10 1 11 1 12 0 13 1 14 1 15 1 16 0 17 0 18 0 19 0 20 1 21 0 22 1 23 1 24 0 25 1 26 1

PLLCAP

Value

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CIV Control Register Symbol: CIVC

Address: 21H Bits: 5

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

The following controls are available through the CIV control register: ACIV When the automatic calculated increment value is 1, the number calculated and present at the CIV

CIVH[1:0] These bits control the hysteresis circuit which is used to calculate the CIV value. CIV[25:24] See descriptions in the next section.

Calculated Increment Value Register Symbol: CIV

CIV25 CIV24 CIVH1 CIVH0 ACIV R R R/W R/W R/W 0 0 0 0 1

registers will automatically be used as the increment value for subcarrier generation, removing the need for the user to read the CIV value and write in a new FSCI value. Whenever this bit is set to 1, the subcarrier generation must be forced to free-run mode (CFRB = 0).

Address: 22H - 24H Bits: 8

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

CIV# CIV# CIV# CIV# CIV# CIV# CIV# CIV# R R R R R R R R 0 0 0 0 0 0 0 0

The CIV registers 22H through 24H contain a 26-bit value, which is the calculated increment value that should be used as the upper 26 bits of FSCI. This value is determined by a comparison of the pixel clock and the 14MHz clock. The bit locations and calculation of CIV are specified as the following:

21H CIV[25:24] 22H CIV[23:16] 23H CIV[15:8] 24H CIV[7:0]

Version ID Register Symbol: VID

Address: 25H Bits: 8

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 R R R R R R R R 0 1 0 0 0 0 0 0

This read-only register contains a 8-bit value indicating the identification number assigned to this version of the CH7008. The default value shown is pre-programmed into this chip and is useful for checking for the correct version of this chip, before proceeding with its programming.

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CHRONTEL CH7008A

Address Register Symbol: AR

Address: 3FH Bits: 6

Bit: 7 6 5 4 3 2 1 0 Symbol: Type: Default:

The Address Register points to the register currently being accessed.

Reserved Reserved AR5 AR4 AR3 AR2 AR1 AR0 R/W R/W R/W R/W R/W R/W X X X X X X

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Electrical Specifications

Table 27. Absolute Maximum Ratings

Symbol Description Min Typ Max Units

VDD relative to GND

AMB

TSTOR

TVPS

Input voltage of all digital pins Analog output short circuit duration Ambient operating temperature Storage temperature Junction temperature Vapor phase soldering (one minute)

Notes:

1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated under the normal operating condition of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods my affect reliability.

2. The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive device. Voltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can induce destructive latch.

- 0.5 7.0 V

GND - 0.5 VDD + 0.5 V

Indefinite Sec

- 55 85 °C

- 65 150 °C 150 °C 220 °C

Table 28. Recommended Operating Conditions

Symbol Description Min Typ Max Units

VDD AVDD DVDD

DVDD2

DAC power supply voltage 4.75 5.00 5.25 V Analog supply voltage 4.75 5.00 5.25 Digital supply voltage 3.1 3.3 3.6 Digital supply voltage (P-OUT pin) VGA controller

interface = 1.8V Digital supply voltage (P-OUT pin) VGA controller

interface = 3.3V Output load to DAC outputs 37.5

1.7 1.8 1.9

3.1 3.3 3.6

Ω

Table 29. Electrical Characteristics (Operating Conditions: TA = 0oC - 70oC, VDD = 5V ± 5%)

Video D/A resolution Full scale output current Video level error VDD & AVDD (5V) current (simultaneous S-Video

& composite outputs) DVDD (3.3V) current DVDD2 (1.8V) current (15pF load)

9 9 9 Bits

33.89 mA 10 %

105 mA

45 mA

4 mA

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CHRONTEL CH7008A

Timing Information

P-OUT

XCLK

XCLK*

D[11:0]

t37

64 P-OUT

t36

t37

t38 t39

t39

P0a P0b P1a P1b

t40

t37(2 setup, 2 hold times)

P2a P2b

t40

DVDD

1 VGA

Line

t40t40

(Internal Clock)

DGND

DVDD

CKB

(Internal Clock)

DGND

DVDD

PCLKX

(Internal Clock)

Symbol Parameter Min Max Unit

t36 t37 t38 t39 t40 DVDD2

DGND

Output High level of interface signals DVDD2 - 0.2 DVDD2 + 0.2 V Output Low level of interface signals -0.2 0.2 V P-OUT = VREF to XCLK = XCLK* Delay 2 9 nS XCLK = XCLK* to D[11:0], H, V & DS = VREF Setup and Hold 3 nS XCLK = XCLK* rise/fall time w/15pF load nS P-OUT rise/fall time w/15pF load nS D[11:0], H, V & DW rise/fall time w/15pF load nS Digital I/O Supply Voltage 1.7 3.6 V

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Table 30. Digital Inputs / Outputs

Symbol Description Test Condition Min Typ Max Unit

P-OUTOH

Note:

SDOL

IICIH

IICIL

DATAIH

DATAIL

P-OUTOL

SD Output Low Voltage

SD Input High Voltage

SD Input Low Voltage D[0-11] Input High Voltage D[0-11] Input Low Voltage

P-OUT Output High Voltage

P-OUT Output Low Voltage

IOL = 2.0 mA 0.4 V

2.7 VDD + 0.5 V

GND-0.5 1.4 V

2.5 DVDD+0.5 V

GND-0.5 0.8 V

IOL = - 400 µA 2.8 V

IOL = 3.2 mA 0.2 V

V V VSD - refers to I2C pin SD as an output. V

-refers to I2C pins SD and SC.

IIC

- refers to all digital pixel and clock inputs.

DATA

- refers to pixel data output Time - Graphics.

P-OUT

Part number Package type Number of pins Voltage supply CH7008A-V PLCC 44 3V/5V CH7008A-T TQFP 44 3V/5V

ORDERING INFORMATION

Chrontel

2210 O’Toole Avenue

San Jose, CA 95131-1326

Tel: (408) 383-9328 Fax: (408) 383-9338

www.chrontel.com

E-mail: sales@chrontel.com

SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. Printed in the U.S.A.

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Datasheet CH7008A-V, CH7008A-T Datasheet (Chrontel Inc)

Specifications and Main Features

Frequently Asked Questions

User Manual