Datasheet CH7001C-V Datasheet (Chrontel Inc)

Page 1
CHRONTEL
VGA to NTSC/PAL Encoder
CH7001C
Features
• Enhanced bandwidth and signal-to-noise ratio for higher video performance
• 3-line digital vertical filtering with pin­programmable characteristics for optimum anti­flicker and resolution
• On-chip phase-locked loop generates sampling clock from VGA horizontal sync
• Enhanced power management for selective circuit power-down
• Simultaneous composite/S-video output
• Horizontal and vertical position control
• Pin-programmable underscan/overscan mode
• On-chip reference generation and loop filter
• CMOS technology in 44-pin PLCC
• 5V supply
Description
Chrontel’s CH7001C VGA to NTSC/PAL encoder is a stand-alone integrated circuit that converts analog VGA inputs directly into 525-line (M) NTSC or 625-line (B,D, G, H, I) PAL composite video and S-video outputs.
This circuit integrates a digital NTSC/PAL encoder with 8-bit ADC and DAC interfaces, a 3-line vertical filter and low-jitter phase-locked loop to create outstanding quality video with 24-bits-per-pixel proces­sing throughout the entire signal path.
A high level of integration and performance makes the CH7001C ideal for a variety of stand-alone and system­level integration solutions, including notebook computers and PC add-on graphics cards.
HORIZONTAL, VERTICAL
POSITION CONTROL
MS[1:0]
R
G
B
H V
ADC
ADC
ADC
STROBE CLKOUT DVDD
BLANKING
H,V SYNC
GENERATOR
VERTICAL SCAN-RATE
PLL
CONVERTERFILTER
SYSTEM CLOCKS
COLOR SPACE
CONVERTER
PD[1:0]NTSC/PAL*CLKEN*
Y
FILTER
U
FILTER
V
FILTER
BLANKING COLOR-BURST
CONTROL
M U X
M U X
M U X
RSETAVDDVDD
RSET
X
X
SIN + COSINE
GENERATOR
VREF1 VREF2
VREF
Σ
Σ
OSC
DAC
DAC
DAC
Y
CVBS
C
Figure 1: Functional Block Diagram
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CHRONTEL CH7001C
STROBE
CLKEN*
AGND
6
5
7
AVDD
G
AGND
B
AVDDRAGND
4
3
2
1
44
43
VREF1
AGND
42
41
40
VREF2
39
CLKOUT
DVDD
DGND
MS0
8 9 10 11
CHRONTEL
MS1 V
DVDD
XO/FIN
PDI
XI
12 13 14 15 16 17
CH7001C
18
19
20
21
22
Y
VDD
GND
RSET
CVBS
24
23
C
25
26
27
UP
VDD
GND
DOWN
AVDD
38 37
PD0 TEST*
36
H
35 34
UNDERSCAN
33
DVDDDGND
32
DGND
31
NTSC/PAL*
30
RIGHT
29
28
LEFT
Figure 2: 44-pin PLCC
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CHRONTEL CH7001C
Table 1 • Pin Description
Pin Type Symbol Description
Analog ground
1, 5, 40, 42 Power AGND
2, 4, 44 In G, R, B
3, 38, 43 Power AVDD
6 In STROBE
7 In CLKEN*
8 Out CLKOUT
9, 13, 32 Power DVDD
10, 14, 31 Power DGND
11, 12 In MS0, MS1
15 In XI
16 In XO/FIN
These pins provide the ground reference for the analog section of CH7001C, and MUST be connected to the system ground to prevent latchup. Please refer to Application Note AN-11 for information on proper supply decoupling.
VGA Inputs
1
These pins should be terminated with 75 resistors and isolated from switching digital signals and video output pins.
Analog Supply Voltage
These pins supply the 5V power to the analog section of the CH7001C. For information on proper supply decoupling, please refer to Application Note AN-11.
Strobe Input (active high, internal pull-up)
A logical HIGH input to this pin keeps chip mode pins (CLKEN*, UNDERSCAN, MS[1:0], UP, DOWN, LEFT, and RIGHT) active. These input signals are internally sampled on the high-to-low transition of the STROBE signal. This allows the chip state to be maintained while rendering these mode pins inactive.
Clock Enable (active low, internal pull-up)
A logical LOW input to this pin enables CLKOUT. CLKEN* should be hardwired to ground to enable CLKOUT. Otherwise, CLKEN* should be left unconnected or connected to VDD.
Clock Output
This pin defaults to 14.31818 MHz upon power-up. Further toggling of the CLKEN* pin causes CLKOUT to output other internal test clocks. When disabled (i.e., CLKEN*=1), this output is a logic LOW. Setting the PD* pin low also causes CLKOUT to be logic LOW.
Digital Supply Voltage
These pins supply the 5V power to the digital section of CH7001C. For information on proper supply decoupling, please refer to
Application Note AN-11. Digital Ground
These pins provide the ground reference for the digital section of CH7001C, and MUST be connected to the system ground to prevent latchup. For information on proper supply decoupling, please refer to Application Note AN-11.
Anti-flicker Mode Select Pins
These two pins are used to select one of four possible anti-flicker vertical filter modes.
Crystal Input
2
A 14.31818 MHz parallel resonance (± 50 ppm) crystal should be attached between XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI should be connected to ground.
Crystal Output or External FREF Input
2
A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN and XI. An external CMOS compatible clock can be connected to XO/FIN as an alternative.
Note: 1 The Typical Connection Diagram (Figure 4 on page 6) shows the VGA input configured for applications that do not require
RGB buffering before the monitor. In this configuration, 75 input termination must be guaranteed either by termination by the monitor connection, by discrete 75 resistors on the PCB, or by a dummy 75 termination connector. The total RGB trace on the PCB must be kept as short as possible to avoid cable reflection problems. For further information, request a copy of
Application Note AN-11, “PC Board Layout Considerations for CH7001C.
2 Please refer to crystal manufacturer specifications for proper load capacitances. The optional variable tuning capacitor is
required only if the crystal oscillation frequency cannot be controlled to the required accuracy. The capacitance value for the tuning capacitor should be obtained from the crystal manufacturer. For further information, request a copy of Application Note AN-19, “Tuning Clock Outputs.
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CHRONTEL CH7001C
Table 1 • Pin Description (continued)
Pin Type Symbol Description
17, 37 In PDI, PD0
18, 25 Power VDD
19 In RSET
20, 24 Power GND
21 Out Y
22 Out CVBS
23 Out C
26 In UP
27 In DOWN
28 In LEFT
29 In RIGHT
30 In NTSC / PAL*
Power Down Inputs (active low, internal pull-up)
Asserting these signals place CH7001C into different power-down states. (Refer to section on Power Management). Note: Use of these pins is optional. Leaving these two pins floating will maintain normal operating mode.
DAC Power Supply
These pins supply power to CH7001C’s internal DACs. Please refer to Application Note AN-11 for information on proper supply decoupling.
Reference Resistor
A 330 resistor with short and wide traces should be attached between RSET and ground. No other connections should be made to this pin.
DAC Ground
These pins provide the ground reference for CH7001C’s internal DACs. For information on proper supply decoupling, please refer to
Application Note AN-11. Luminance Output
A 75 termination resistor with short traces should be attached between Y and ground for optimum performance. An optional low pass filter circuit, shown in Figure3 on page 5, may be used as an alternative to the ferrite bead shown in Figure 4 on page 6.
Composite Output
A 75 termination resistor with short traces should be attached between CVBS and ground for optimum performance. An optional low pass filter circuit shown in Figure3 on page 5, may be used as an alternative to the ferrite bead shown in Figure 4 on page 6.
Chrominance Output
A 75 termination resistor with short traces should be attached between C and ground for optimum performance. An optional low pass filter circuit shown in Figure3 on page 5, may be used as an alternative to the ferrite bead shown on Figure 4 on page 6.
Up Position Control (active low, internal pull-up)
UP allows the screen display position to be moved up incrementally for every toggle of this pin to ground. An internal schmitt trigger minimizes switch bounce problems. UP may be connected directly to the power supply or ground.
Down Position Control (active low, internal pull-up)
DOWN allows the screen display position to be moved down incrementally for every toggle of this pin to ground. An internal schmitt trigger minimizes switch bounce problems. DOWN may be connected directly to the power supply or ground.
Left Position Control (active low, internal pull-up)
LEFT allows the screen display position to be moved to the left incrementally for every toggle of this pin to ground. An internal schmitt trigger minimizes switch bounce problems. LEFT may be connected directly to the power supply or ground.
Right Position Control (active low, internal pull-up)
RIGHT allows the screen display position to be moved to the right incrementally for every toggle of this pin to ground. An internal schmitt trigger minimizes switch bounce problems. RIGHT may be connected directly to the power supply or ground.
NTSC/PAL Mode Select Input (internal pull-up)
A logical HIGH input NTSC/PAL* pin selects NTSC operation. A logical LOW input to NTSC/PAL* selects PAL operation. NTSC/PAL* accepts CMOS logic level inputs and may be connected directly to the power supply or ground.
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CHRONTEL CH7001C
Table 1 Pin Description (continued)
Pin Type Symbol Description
Underscan Enable Pin (active high, internal pull-up)
33 In UNDERSCAN
34 In V
35 In H
36 TEST*
39 In VREF2
41 In VREF1
A logical HIGH input to UNDERSCAN results to an output screen that has approximately 12.5% horizontal underscan. This pin may be connected directly to the power supply or ground.
Vertical Sync Input This pin accepts the vertical sync output from the VGA card. The
capacitive loading on this pin should kept to a minimum.
Horizontal Sync Input
This pin accepts the horizontal sync output from the VGA card. The capacitive loading on this pin should kept to a minimum. Please refer to Application Note 11 “PC Board Layout Considerations
for CH7001C. Test Pin (active low, internal pull-up)
Connect a capacitor in the range of 2.2uF - 4.7uF from this pin to GND to ensure proper functionality of the UNDERSCAN/ OVERSCAN feature.
Internal Voltage Reference
VREF2 provides a typical 2.5V reference that is used as an internal bias to the ADCs. A 0.1 µF decoupling capacitor should be connected between VREF2 and ground.
ADC Voltage Reference Input / Output
VREF1 provides a typical 1.235V reference that sets the RGB input full scale at 0.75V. A 0.1 µF decoupling capacitor should be connected between VREF1 and ground. VREF1 may also be forced by external reference.
Y,C, CVBS
75 Ohms
Optional Output Filter
47pF
1.2uH
150pF 270pF
1.2uH
1
Figure 3: Optional Output Filter
OUTPUT
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CHRONTEL CH7001C
CONNECTOR
COMPOSITE
CONNECTOR
Ferrite Bead
+5V
Ferrite BeadFerrite Bead
0.1uF
VGA
Card
To MONITOR or
TERMINATION
RESISTORS
(1)
2.2uF-4.7uF (2)
74047404
75 Ohms
75 Ohms
Switch
Switch
14.31818 MHz
+10uF
35
34
44
75 Ohms
26
27 28
29
12, 11
33
30
37,17
6
36
16
15
0.1uF
H
V
4
R
2
G
B
UP
DOWN
LEFT
RIGHT
MS [1:0]
UNDERSCAN
NTSC/PAL*
7
CLKEN*
PD [0:1]
STROBE TEST*
XO/FIN
XI
0.1uF 0.1uF 0.1uF
3 38 43 18 25 9 13 32
AVDD AVDD AVDD
CH7001C
(PLCC pinout)
AGND GND DGND
1 5 40 42 20 24 10 14 31
Figure 4: CH7001C Typical Connection Diagram
0.1uF 0.1uF 0.1uF 0.1uF
VDD VDD DVDD DVDD DVDD
VREF1
VREF2
CLKOUT
CVBS
RSET
41
39
8
Ferrite Bead
21
Y
75 Ohms
Ferrite Bead
23
C
75 Ohms
Ferrite Bead
22
75 Ohms
19
0.1uF
0.1uF
S-VIDEO
330 Ohms
Note: 1 If the CLKOUT signal is not used, either connect CLKEN* to VDD, or leave it unconnected. Note: 2 An external pull-up resistor should not be connected to the TEST* pin.
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CHRONTEL CH7001C
General Description
The CH7001C is a fully integrated solution for converting analog RGB and synchronization signals from a standard VGA source into high-quality NTSC or PAL video signals. All essential circuitry for this conversion (memory, memory control, PLL, ADC, DAC, digital filters, digital NTSC/PAL encoder) are present in this IC. All internal signal processing, including NTSC/PAL encoding, is performed using digital techniques to ensure that the high­quality video signals are not affected by drift issues associated with analog components. No additional adjustment is required during manufacturing.
CH7001C is ideal for stand-alone VGA to NTSC/PAL applications, where a minimum of discrete support components (passive components, 14.31818 MHz crystal) are required for full operation. The CH7001C easily integrates into notebook computers and PC add-on graphics cards.
Functional Description
The analog RGB inputs are digitized on a pixel-by-pixel basis by three 8-bit video A/D converters. The digitized RGB inputs are fed to a block where scan-rate conversion and programmable 3-line vertical filtering are performed. The vertical filter eliminates flicker at the output, while the scan-rate converter transforms the VGA horizontal scan­rate to either NTSC or PAL scan-rates.
The digitized RGB inputs are encoded into luminance (Y) and color-difference (U,V) signals through the color space converter. The resulting YUV signals are filtered through digital filters to minimize aliasing problems (the frequency response is shown in Figure 5 on page 8). The digital encoder receives the filtered signals and transforms them to composite and S-video outputs, which are converted by the three 8-bit DACs into analog outputs. High­quality video is ensured by using 24 bits per pixel processing throughout the entire signal path.
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CHRONTEL CH7001C
General Description (continued)
Figure 5: U,V, and Y Filter Response
CH7001C Detailed Frequency Response
-0
Y_SV Y_CV
UV
-2
-4
dB
-6
-8
-10
0 1 2 3 4 5 6
Freq (MHz)
CH7001C Frequency Response
-0
-10
-20
dB
-30
-40
-50 0 1 2 3
4 5 6 7 8 9 10 11 12
Freq (MHz)
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CHRONTEL CH7001C
General Description (continued)
Clock Generation and Video Timing
All clock signals of the CH7001C are generated from the VGA synchronization inputs by a low-jitter, PLL circuit. The VGA input and sync timing are illustrated in Figures 6 and 7 below. The VGA pixel clock is generated internally, using the VGA horizontal sync signal, and is used for sampling the RGB inputs pixel-by-pixel, which aids in preventing aliasing artifacts.
All synchronization and color burst envelope pulses are internally generated using only the timing signals provided by the VGA synchronization inputs.
31.78 µs
H
25.42 µs
R,G,B DATA
3.81 µs
ACTIVE VIDEO
1.91 µs 0.64 µs
Note: The timing diagram shown is for 640 x 480, 60 Hz VGA mode
Figure 6: Typical VGA Input Timing
31.78 µs
H
63.56 µs
V *
(ACTIVE LOW)
Figure 7: VGA Horizontal and Vertical Sync Timing
Internal Voltage Reference
The on-chip generated ADC voltage references are brought out to pins VREF1 and VREF2 for decoupling purposes. VREF1 and VREF2 should each have a 0.1 µF decoupling capacitor between each pin and ground. VREF2 provides a typical 2.5V reference, used for setting the internal bias to the ADCs, and VREF1 provides a typical
1.235V reference, used for setting the RGB input full scale at 0.75V. VREF1 can be forced by an external voltage reference in order to accommodate different RGB input ranges. An additional on-chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a reference resistor at pin RSET, sets the output ranges of the DACs.
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CHRONTEL CH7001C
General Description (continued)
Strobing
The CH7001C programmable pins (MS[1:0], UNDERSCAN, NTSC/PAL*, LEFT, RIGHT, UP, and DOWN) may be connected to shared signal lines and then strobed in using the STROBE pin. By asserting the STROBE pin high, the state of the programmable pins is internally sampled during the STROBE signal’s high-to-low transition. A logical low input to the STROBE pin allows the chip state to be maintained, while rendering the programmable pins inactive.
Power Management
The CH7001C supports four operating states including Normal (On), Power Down, S-Video Off, and Composite Off) in order to provide optimal power consumption for the application involved. Using pins PD0 and PD1, the CH7001C ay be placed in either Normal state or any of the three power managed states as listed below:
PD1 PD0 Operating State Functional Description 1 1 Normal (On) All functions and pins are active (default state with inputs floating.) 0 1 Power Down Most pins and cicruitry are disabled. This reduces power to only 1%
of normal operating power.
1 0 S-Video Off Power is shut off to the unused DACs associated with Y and C outputs.
This reduces power to 81% of normal operating power.
0 0 Composite Off Power is shut off to the unused DAC associated with CVBS output.
This reduces power to 89% of normal operating power.
Color Burst Accuracy*
The CH7001C employs a proprietary technique for generating the color sub-carrier frequency. This method allows the sub-carrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator, leaving the accuracy of the sub-carrier frequency independent of the sampling rate. As a result, the CH7001C is compatible with any VGA card, since the CH7001C sub-carrier frequency is not dependent on the pixel rates of VGA card manufacturers. This feature is a significant benefit, since even a ± 0.01% sub-carrier frequency variation may be enough to cause some television monitors to lose color lock.
10 *Patent number 5,874,846 201-0000-028 Rev 3.0, 6/2/99
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CHRONTEL CH7001C
Programmability
All operational modes of the CH7001C are accessed directly through the package pins, making the CH7001C programmable without the use of an additional microcontroller. Some of the programmable features are: horizontal overscan/underscan control, NTSC or PAL operation, selectable anti-flicker filter modes, and adjustable horizontal and vertical display positioning capabilities.
Horizontal Overscan/Underscan
Horizontal underscan mode is enabled via the UNDERSCAN pin. By setting this pin high, the resulting output screen experiences a 12.5% horizontal underscan.
The CH7001C also implements an overscan/underscan mode that is controllable through the PC. Software control is available only when the underscan input is inactive (i.e., UNDERSCAN = 0) and is accomplished by programming the length (in VGA line periods) of the vertical sync pulse.
When the CH7001C detects the vertical sync pulse as having fewer than eight VGA line periods, the device operates in overscan mode; when it detects the vertical sync pulse as having more than eight VGA line periods, it operates in underscan mode. The CH7001C determines the number of VGA line periods through an internal circuitry that continuously analyzes the width of the VGA vertical sync input.
Software control is overridden if the underscan input is set high.
NTSC or PAL Operation
Composite and S-video outputs are supported in either NTSC or PAL format, as shown in Figures 8 through 10. These outputs can be conveniently switched to either format via the NTSC/PAL* pin. If the NTSC/PAL* pin is set low, PAL output format is selected. If the NTSC/PAL* is set high, NTSC output format is selected. See Figures 11 through 16 on pages 14 through 16 for illustrations of the composite and S-video output waveforms.
A B C D E F G H
Figure 8: NTSC / PAL Composite Output
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CHRONTEL CH7001C
General Description (continued)
Table 2 • NTSC/PAL Composite Output Timing Parameters (in µS)
Symbol Description
A Front Porch 1.35 1.20 1.35 1.20 B Horizontal Sync 4.69 4.70 4.69 4.70 C Breezeway 0.64 0.57 0.56 0.49 D Color Burst 2.66 2.37 2.39 2.12 E Back Porch 1.47 1.31 1.83 1.63 F Black 2.38 5.10 2.37 5.11 G Active Video 50.51 45.19 50.51 45.19 H Black 0.00 3.12 0.00 3.12
520 521 522 523 524 525 1 2 3 4 5 6 7
OVERSCAN UNDERSCAN OVERSCAN UNDERSCAN
ANALOG FIELD 1
NTSC PAL
START
OF
VSYNC
8 9
ANALOG FIELD 2
258 259 260 261 262 263 264 265 266 267 268 269 272
LINE RATE = HALF THE VGA LINE RATE IN MODES 11 & 12 (640 x 480) FIELD RATE = VGA VERTICAL REFRESH RATE IN MODES 11 & 12 (640 x 480)
270 271
Figure 9: Interlaced NTSC Video Timing
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CHRONTEL CH7001C
General Description (continued)
START
OF
VSYNC
ANALOG FIELD 1
621 622 623 624 625 1 2 3 4 5 6 7620
ANALOG FIELD 2
309 310 311 312 313 314 315 316 317 318 319 320 323308 322
ANALOG FIELD 3
621 622 623 624 625 1 2 3 4 5 6 7620
ANALOG FIELD 4
309 310 311 312 313 314 315 316 317 318 319 320308
8 9 10
321
8 9 10
323322321
Figure 10: Interlaced PAL Video Timing
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CHRONTEL CH7001C
Color / Level mA V
White Yellow
Cyan Green
Magenta Red
Blue Black Blank
Sync
24.60
27.48
22.85
25.41
19.85
22.08
18.11
20.01
15.23
16.99
13.49
14.93
10.49
11.59
8.74
9.69
8.26
7.49
0.50
0.640
0.922
1.030
0.857
0.953
0.745
0.828
0.679
0.750
0.571
0.637
0.506
0.560
0.393
0.435
0.327
0.363
0.281
0.310
0.019
0.024
COLOR BARS :
Note: 100% amplitude, 100% saturation color bars are shown Note: VREF1 = 1.235V, RSET = 330, 75 doubly terminated load.
Figure 11: NTSC Y (Luminance) Output Waveform
WHITE
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
Color / Level mA V
White Yellow
Cyan Green
Magenta Red
Blue Black Blank
Blank
Sync
26.05
24.60
24.00
22.85
20.67
19.85
18.59
18.11
15.57
15.23
13.52
13.49
10.19
10.49
8.74
7.49
8.26
0.50
0.640
0.922
0.857
0.745
0.679
0.571
0.506
0.393
0.327
0.281
0.019
0.977
0.900
0.775
0.697
0.584
0.507
0.382
0.310
0.024
COLOR BARS :
Note: 100% amplitude, 100% saturation color bars are shown Note: VREF1 = 1.235V, RSET = 330, 75 doubly terminated load.
Figure 12: PAL Y (Luminance) Video Output Waveform
WHITE
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
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CHRONTEL CH7001C
General Description (continued)
Color / Level mA V
Cyan / Red Green / Magenta
Yellow / Blue
Peak Burst
Blank
Peak Burst
Yellow / Blue
Green / Magenta Cyan / Red
mA
22.60
26.51/26.66
21.85
25.89/25.89
19.61
23.39/23.39
15.98
19.34
12.49
15.59
11.85
8.99
5.37
7.8/7.8
5.3/5.3
3.12
2.37
4.68/4.52
0.994/1.000
0.848
0.819
0.971/0.971
0.735
0.877/0.877
0.599
0.468
0.337
0.201
0.292/0.292
0.117
0.199/0.199
0.089
0.175/0.170
V
0.725
0.585
0.444
COLOR BARS :
3.579545 MHz Color Burst (9 cycles)
Note: 1 100% amplitude, 100% saturation color bars are shown Note: 2 VREF1 = 1.235V, RSET = 330, 75 doubly terminated load.
Figure 13: NTSC C (Chrominance) Video Output Waveform
WHITE
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
Color / Level mA V
Cyan / Red Green / Magenta
Yellow / Blue
Peak Burst
Blank
Peak Burst
Yellow / Blue
Green / Magenta Cyan / Red
mA
22.60
26.51/26.66
25.89/25.89
21.85
23.39/23.39
19.61
16.23
19.34
12.49
15.59
11.85
8.74
5.37
7.8/7.8
5.3/5.3
3.12
2.37
4.68/4.52
0.994/1.000
0.848
0.971/0.971
0.819
0.877/0.877
0.735
0.609
0.468
0.328
0.201
0.292/0.292
0.117
0.199/0.199
0.089
0.175/0.170
V
0.725
0.585
0.444
COLOR BARS :
4.433619 MHz Color Burst (10 cycles)
WHITE
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
Note: 1 100% amplitude, 100% saturation color bars are shown
Figure 14: PAL C (Chrominance) Video Output Waveform
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CHRONTEL CH7001C
BLACK
BLACK
General Description (continued)
Color / Level mA V
Peak Chroma
White
Peak Burst Black Blank 8.16 0.306
Peak Burst
Sync
33.89
33.23
27.37
27.47
12.00
12.03
9.68
9.62
8.27
4.32
4.53
0.50
0.640
1.271
1.246
1.026
1.030
0.450
0.451
0.363
0.360
0.310
0.162
0.170
0.019
0.024
COLOR BARS :
3.579545 MHz Color Burst
(9 Cycles)
Note: VREF1=1.235V, RSET=330Ω, 75Ω, doubly terminated load.
Figure 15: Composite NTSC Video Output Waveform
WHITE
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
Color / Level mA V
Peak Chroma
White
Peak Burst
Blank/Black 8.64 0.324
Peak Burst
Sync
33.89
31.81
27.37
26.05
12.00
12.03
8.26
4.53
4.58
0.643
0.50
1.271
1.193
1.026
0.977
0.450
0.451
0.310
0.171
0.170
0.019
0.024
COLOR BARS :
4.433619 MHz Color Burst (10 Cycles)
WHITE
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
Note: VREF1=1.235V, RSET=330W, 75W, doubly terminated load.
Figure 16: Composite PAL Video Output Waveform
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CHRONTEL CH7001C
General Description (continued)
Anti-Flicker Filter Modes
The CH7001C integrates a 3-line vertical filter circuitry to help eliminate the flicker associated with interlaced displays. The CH7001C provides four anti-flicker filter modes programmable via the anti-flicker mode select pins MS[1:0]. For a list of the filter modes available, please refer to Table3 below.
Table 3 • Anti-Flicker Filter Modes
MS1 MS0 Filter Modes
0 0 0:1:0 averaging 0 1 1:3:1 averaging 1 0 1:2:1 averaging 1 1 1:1:1 averaging
Programmability
Display Position Control
UP, DOWN, LEFT, and RIGHT are dedicated inut pins controlling the NTSC or PAL display position. Upon power up, the internal position registers for a typical VGA input center the display on the television screen. With each toggle of any position pin to ground, the display will shift four pixels in the respective direction. For example, if the LEFT pin is toggled to ground once, the screen display will move four pixels to the left. Similarly, if the RIGHT pin is toggled to ground once, the screen display will move four pixels to the right. The shift of the display occurs during the low-to-high transition of the position pin. Toggling conflicting pins, such as the LEFT and RIGHT pins for example, simultaneously is not allowed. The minimum time required for the display position pins to be held low is 40 ns.Electrical Specifications
Table 4 • Absolute Maximum Ratings
Symbol Description Min Typ Max Units
VDD relative to GND - 0.5 7.0 V Input voltage of all digital pins
T
SC
T
AMB
TSTOR Storage temperature - 65 150 °C
TJ Junction temperature 150 °C TVPS Vapor phase soldering (one minute) 220 °C P
MAX
Note: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are
Analog output short circuit duration Indefinite Sec Ambient operating temperature - 55 125 °C
Maximum Power dissipation TBD W
stress ratings only. Functional operation of device at these or any other conditions above those indicated under the normal operating conditions section of this specification is not recommended, Exposure to absolute maximum rating conditions for extended periods may affect relaibility.
The device is fabricated using high-performance CMOS technology. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce destructive latchup.
1
GND - 0.5 VDD + 0.5 V
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CHRONTEL CH7001C
Table 5 • Recommended Operating Conditions
Symbol Description Min Typ Max Units
VDD DAC power supply voltage 4.75 5.00 5.25 V AVDD Analog supply voltage 5.00 DVDD Digital supply voltage 5.00
TA Ambient operating temperature 0 25 70 °C
RL Output load to DAC outputs 37.5 VREF1 ADC voltage reference input/output 1.20 1.235 1.32 V VREF2 Internal voltage reference 2.5 V
Table 6 • Electrical Characteristics (Operating Conditions: T A = 0 – 70°C, VDD = 5V ± 5%)
Symbol Description Min Typ Max Unit
Video D/A resolution 8 8 8 Bits Full scale output current 33.89 mA Video level error
using external reference using internal reference
IREF1 VREF1 input current (VREF1 = 1.235V) 10 µA
Total Current Consumption (both S-video & composite outputs are On)
340 mA
10
5
% %
Note: As applied to Tables 4, 5, and 6, Recommended Operating Conditions are used as test conditions unless otherwise specified.
Table 7 • Digital Inputs / Outputs
Symbol Description Test Condition @ TA = 25 Min Typ Max Units
VOH Output high voltage IOH = - 400 µA 2.4 V
VOL Output low voltage IOL = 3.2 mA 0.4 V
VIH Input high voltage 2.0 VDD + 0.5 V VIL Input low voltage GND - 0.5 0.8 V IPU Input internal pull-up current 5 25 µA
ILK Input leakage current -10 10 µA
CDIN Input capacitance f = 1 MHz, VIN = 2.4V 7 pF
CDOUT Output capacitance 10 pF
ORDERING INFORMATION
Part number Package type Number of pins Voltage supply
CH7001C-V PLCC 44 5V
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