Page 1
CED93A3/CEU93A3
N-Channel Enhancement Mode Field Effect Transistor
FEATURES
30V, 125A, R
R
Super high dense cell design for extremely low R
High power and current handing capability.
Lead free product is acquired.
TO-251 & TO-252 package.
ABSOLUTE MAXIMUM RATINGS T
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
Drain Current-Pulsed
Maximum Power Dissipation @ TC = 25 C
Single Pulsed Avalanche Energy
Single Pulsed Avalanche Current
Operating and Store Temperature Range TJ,T
= 3.2mΩ @VGS = 10V.
DS(ON)
= 6.2mΩ @VGS = 4.5V.
DS(ON)
G
S
CEU SERIES
TO-252(D-PAK)
Parameter
a
- Derate above 25 C
.
DS(ON)
D
G
D
S
CED SERIES
TO-251(I-PAK)
= 25 C unless otherwise noted
c
G
Symbol
V
DS
V
GS
I
D
I
DM
P
D
d
d
E
AS
I
AS
stg
PRELIMINARY
D
S
Limit
Units
30
±20
125
500
57
0.46
506
45
-55 to 150 C
W/ C
mJ
V
V
A
A
W
A
Thermal Characteristics
Parameter Symbol Limit Units
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Details are subject to change without notice .
C/W
C/W
RθJA
2.2RθJC
50
Rev 4. 2011.Aug.
http://www.cetsemi.com
1
Page 2
CED93A3/CEU93A3
Electrical Characteristics T
= 25 C unless otherwise noted
c
Parameter Symbol Min Units
Off Characteristics
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics
b
Gate Threshold Voltage
Static Drain-Source
On-Resistance
Dynamic Characteristics
c
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
c
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
R
BV
C
C
C
t
d(on)
t
d(off)
Q
Q
DSS
I
DSS
I
GSSF
IGSSR
GS(th)
DS(on)
g
FS
iss
oss
rss
t
r
t
f
Q
g
gs
gd
Drain-Source Diode Characteristics and Maximun Ratings
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
c.Guaranteed by design, not subject to production testing.
d.L = 0.5mH, IAS = 45A, VDD = 24V, RG = 25Ω, Starting TJ = 25 C
b
I
S
V
SD
Test Condition
VGS = 0V, ID = 250µA
Typ Max
30
VDS = 30V, VGS = 0V
VGS = 20V, VDS = 0V
VGS = -20V, VDS = 0V
VGS = VDS, ID = 250µA
VGS = 10V, ID = 30A
1 3
2.5
VGS = 4.5V, ID = 30A 4.2
VDS = 10V, ID = 15A
VDS = 15V, VGS = 0V,
f = 1.0 MHz
50
4100
980
600
24
VDD = 15V, ID = 1A,
VGS = 10V, R
GEN
= 6Ω
19
128
72
VDS = 15V, ID = 16A,
VGS = 5V
60
12
25
VGS = 0V, IS = 20A
1
100
-100
3.2
6.2
115
1.5
V
µA
nA
nA
V
mΩ
mΩ
S
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
A
V
2
Page 3
CED93A3/CEU93A3
120
100
80
60
40
ID, Drain Current (A)
20
0
0 1 2 4 6
VGS=10,9,8,7V
VDS, Drain-to-Source Voltage (V)
Figure 1. Output Characteristics
6000
5000
4000
3000
2000
C, Capacitance (pF)
1000
0
0 5 10 15 20 25
C
iss
C
oss
C
rss
VDS, Drain-to-Source Voltage (V)
200
V
=4V
GS
V
=3V
GS
53
160
120
80
ID, Drain Current (A)
40
TJ=125 C
0
0 1.5 3 4.5
25 C
-55 C
7.56
VGS, Gate-to-Source Voltage (V)
Figure 2. Transfer Characteristics
2.2
ID=30A
VGS=10V
1.9
1.6
1.3
1.0
RDS(ON), Normalized
0.7
RDS(ON), On-Resistance(Ohms)
0.4
-100 -50 0 50 100 150 200
TJ, Junction Temperature( C)
Figure 3. Capacitance
1.3
VDS=V
GS
ID=250µA
1.2
1.1
1.0
0.9
0.8
VTH, Normalized
0.7
Gate-Source Threshold Voltage
0.6
-50 -25 0 25 50 75 100 125 150
TJ, Junction Temperature( C)
Figure 5. Gate Threshold Variation
with Temperature
Figure 4. On-Resistance Variation
with Temperature
V
=0
V
GS
2
10
1
10
IS, Source-drain current (A)
0
10
0.4 0.6 0.8 1.0
1.2
1.4
VSD, Body Diode Forward Voltage (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
Page 4
CED93A3/CEU93A3
5
VDS=15V
ID=16A
4
3
2
1
VGS, Gate to Source Voltage (V)
0
0 12 24 36 6048
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
IN
V
V
GS
GEN
R
G
3
10
R
Limit
DS(ON)
DC
1ms
10ms
100ms
10
1
2
10
10
10
ID, Drain Current (A)
10
2
1
TC=25 C
TJ=150 C
Single Pulse
0
-1
10
0
10
VDS, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
DD
V
on
t
d(off)
t
r
t
90%
10% 10%
INVERTED
50% 50%
V
V
t
d(on)
OUT
IN
10%
R
L
D
OUT
V
S
90%
t
off
f
t
90%
PULSE WIDTH
Figure 9. Switching Test Circuit
0
10
D=0.5
0.2
-1
0.1
10
0.05
0.02
10
-2
-5
10
0.01
Single Pulse
-4
10
r(t),Normalized Effective
Transient Thermal Impedance
Figure 11. Normalized Thermal Transient Impedance Curve
Figure 10. Switching Waveforms
-3
10
-2
10
Square Wave Pulse Duration (sec)
4
PDM
t1
t2
1. RθJC (t)=r (t) * RθJC
2. RθJC=See Datasheet
3. TJM-TC = P* RθJC (t)
4. Duty Cycle, D=t1/t2
-1
10
0
10
1
10
Loading...