Datasheet ceu84a4_ced84a4 Datasheet

CED84A4/CEU84A4

N-Channel Enhancement Mode Field Effect Transistor

FEATURES

40V, 80A, R

Super high dense cell design for extremely low R

= 5.1mΩ @VGS = 10V.

DS(ON)

R

= 7.8mΩ @VGS = 4.5V.

DS(ON)

DS(ON)

.

High power and current handing capability.

Lead free product is acquired.

TO-251 & TO-252 package.

D

G

S
CEU SERIES
TO-252(D-PAK)

ABSOLUTE MAXIMUM RATINGS T

G

D

S

CED SERIES
TO-251(I-PAK)

= 25 C unless otherwise noted

c

Parameter

Drain-Source Voltage

Gate-Source Voltage

Drain Current-Continuous @ TC = 25 C

@ TC = 100 C

Drain Current-Pulsed

a

Maximum Power Dissipation @ TC = 25 C

- Derate above 25 C

Operating and Store Temperature Range TJ,T

Symbol

V

DS

V

GS

I

D

I

DM

P

D

stg

D

G

S

Limit

40

±20

80

56

320

57.7

0.38

-55 to 175 C

Units

V

V

A

A

A

W

W/ C

Thermal Characteristics

Parameter Symbol Limit Units

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient

Details are subject to change without notice .

C/W

C/W

RθJA

2.6RθJC

50

Rev 1. 2011.Mar

http://www.cetsemi.com

1

CED84A4/CEU84A4

Electrical Characteristics T

= 25 C unless otherwise noted

A

Parameter Symbol Min Units

Off Characteristics

Drain-Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate Body Leakage Current, Forward

Gate Body Leakage Current, Reverse

On Characteristics

c

Gate Threshold Voltage

Static Drain-Source

On-Resistance

Dynamic Characteristics

d

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Switching Characteristics

d

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

BV

I

IGSSR

V

GS(th)

R

DS(on)

C

C

C

t

d(on)

t

d(off)

Q

Q

DSS

I

DSS

GSSF

iss

oss

rss

t

r

t

f

Q

g

gs

gd

Drain-Source Diode Characteristics and Maximun Ratings

Drain-Source Diode Forward Current

Drain-Source Diode Forward Voltage

Notes :

a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Surface Mounted on FR4 Board, t < 10 sec.
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
d.Guaranteed by design, not subject to production testing.

b

c

I

S

V

SD

Test Condition

VGS = 0V, ID = 250µA

VDS = 40V, VGS = 0V

VGS = 20V, VDS = 0V

VGS = -20V, VDS = 0V

VGS = VDS, ID = 250µA

VGS = 10V, ID = 30A

VGS = 4.5V, ID =20A

VDS = 15V, VGS = 0V,
f = 1.0 MHz

VDD = 15V, ID = 1A,
VGS = 10V, R

GEN

= 6Ω

VDS = 15V, ID = 16A,
VGS = 4.5V

VGS = 0V, IS = 20A

40

1

Typ Max

100

-100

5.14

7.85.8 mΩ

3070

385

285

19

38

10

20

84

168

22

44

67

87

10

12

80

1.2

V

1

µA

nA

nA

V

3

mΩ

pF

pF

pF

ns

ns

ns

ns

nC

nC

nC

A

V

2

CED84A4/CEU84A4

75

60

45

30

ID, Drain Current (A)

15

0

0 1

VGS=10,8,6V

V

GS

2

VDS, Drain-to-Source Voltage (V)

Figure 1. Output Characteristics

3600

3000

2400

1800

1200

C, Capacitance (pF)

600

C

rss

0

0 5 10 15 20 25

VDS, Drain-to-Source Voltage (V)

C

C

=3V

iss

oss

100

80

60

40

ID, Drain Current (A)

20

TJ=125 C

0

3

4

0 2 4 6 8

25 C

-55 C

VGS, Gate-to-Source Voltage (V)

Figure 2. Transfer Characteristics

2.2
ID=20A

VGS=10V

1.9

1.6

1.3

1.0

RDS(ON), Normalized

0.7

RDS(ON), On-Resistance(Ohms)

0.4

-100 -50 0 50 100 150 200

TJ, Junction Temperature( C)

Figure 3. Capacitance

1.3
VDS=V

GS

ID=250µA

1.2

1.1

1.0

0.9

0.8

VTH, Normalized

0.7

Gate-Source Threshold Voltage

0.6

-50 -25 0 25 50 75 100 125 150

TJ, Junction Temperature( C)

Figure 5. Gate Threshold Variation

with Temperature

Figure 4. On-Resistance Variation

with Temperature

V

=0

V

GS

2

10

1

10

IS, Source-drain current (A)

0

10

0.4 0.6 0.8 1.0

1.41.2

VSD, Body Diode Forward Voltage (V)

Figure 6. Body Diode Forward Voltage

Variation with Source Current

3

CED84A4/CEU84A4

3

10

VDS=15V
ID=16A

8

6

4

2

VGS, Gate to Source Voltage (V)

0

0

15 30 45 7560

Qg, Total Gate Charge (nC)

10

R

Limit

DS(ON)

1ms

100ms

10

10ms

1

2

10

2

10

1

10

ID, Drain Current (A)

0

10

TC=25 C
TJ=175 C

Single Pulse

-1

10

DC

0

10

VDS, Drain-Source Voltage (V)

Figure 7. Gate Charge

IN

V

D

V

GS

GEN

R

G

S

Figure 9. Switching Test Circuit

0

10

D=0.5

0.2

0.1

-1

10

0.05

0.02

10

-2

-4

10

0.01

Single Pulse

-3

10

r(t),Normalized Effective

Transient Thermal Impedance

DD

V

R

L

OUT

V

-2

10

Square Wave Pulse Duration (sec)

Figure 8. Maximum Safe

on

t

r

t

V

V

d(on)

OUT

IN

10%

t

90%

10% 10%

INVERTED

50% 50%

PULSE WIDTH

Figure 10. Switching Waveforms

PDM

-1

10

0

10

Operating Area

t

off

d(off)

t

90%

90%

t1

t2

1. RθJC (t)=r (t) * RθJC

2. RθJC=See Datasheet

3. TJM-TC = P* RθJC (t)

4. Duty Cycle, D=t1/t2

1

10

f

t

2

10

Figure 11. Normalized Thermal Transient Impedance Curve

4