Page 1
CED840A/CEU840A
N-Channel Enhancement Mode Field Effect Transistor
FEATURES
500V, 7.5A, R
Super high dense cell design for extremely low R
High power and current handing capability.
Lead free product is acquired.
TO-251 & TO-252 package.
ABSOLUTE MAXIMUM RATINGS T
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous @ TC = 25 C
@ TC = 100 C
Drain Current-Pulsed
Maximum Power Dissipation @ TC = 25 C
Single Pulsed Avalanche Energy
Single Pulsed Avalanche Current
Operating and Store Temperature Range TJ,T
= 0.85Ω @VGS = 10V.
DS(ON)
G
S
CEU SERIES
TO-252(D-PAK)
Parameter
a
- Derate above 25 C
.
DS(ON)
D
G
D
S
CED SERIES
TO-251(I-PAK)
= 25 C unless otherwise noted
c
G
Symbol
V
DS
V
GS
I
D
I
DM
P
D
e
e
E
AS
I
AS
stg
PRELIMINARY
D
S
Limit
Units
500
±30
7.5
7.5
4.7
30
107
0.85
196
7.5
-55 to 150 C
W/ C
mJ
V
V
A
A
A
W
A
Thermal Characteristics
Parameter Symbol Limit Units
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Details are subject to change without notice .
C/W
C/W
RθJA
1.4RθJC
50
Rev 1. 2011.JulyThis is preliminary information on a new product in development now .
http://www.cetsemi.com
1
Page 2
CED840A/CEU840A
Electrical Characteristics T
= 25 C unless otherwise noted
c
Parameter Symbol Min Units
Off Characteristics
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics
b
Gate Threshold Voltage
Static Drain-Source
On-Resistance
Dynamic Characteristics
c
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
c
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
R
BV
C
C
C
t
d(on)
t
d(off)
Q
Q
DSS
I
DSS
I
GSSF
IGSSR
GS(th)
DS(on)
iss
oss
rss
t
r
t
f
Q
g
gs
gd
Drain-Source Diode Characteristics and Maximun Ratings
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Device Mounted on FR4 Board, t < 10 sec.
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
d.Guaranteed by design, not subject to production testing
e.L = 7mH, IAS =7.5A, VDD = 50V, RG = 25Ω, Starting TJ = 25 C
b
IS
V
SD
Test Condition
VGS = 0V, ID = 250µA
VDS = 500V, VGS = 0V
VGS = 30V, VDS = 0V
VGS = -30V, VDS = 0V
VGS = VDS, ID = 250µA
VGS = 10V, ID = 3.8A
VDS = 25V, VGS = 0V,
f = 1.0 MHz
VDD = 250V, ID = 7A,
VGS = 10V,R
GEN
= 9.1Ω
VDS = 400V, ID = 7A,
VGS = 10V
VGS = 0V, IS = 7A
Typ Max
500
2 4
1580
125
15
25
5
6
1
100
-100
0.850.68
4020
105
7638
84
33.3
7
1.5
V
µA
nA
nA
V
Ω
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
A
V
2
Page 3
CED840A/CEU840A
6
5
4
3
2
VGS=10,9,8,7V
ID, Drain Current (A)
1
0
0 1 2 4 6
VDS, Drain-to-Source Voltage (V)
Figure 1. Output Characteristics
1800
1500
1200
900
600
C, Capacitance (pF)
300
C
rss
0
0 5 10 15 20 25
C
iss
C
oss
VDS, Drain-to-Source Voltage (V)
18
15
V
=5V
GS
53
12
9
6
ID, Drain Current (A)
TJ=125C
3
0
0 2 4 6 108
25 C
-55 C
VGS, Gate-to-Source Voltage (V)
Figure 2. Transfer Characteristics
2.2
ID=4.8A
VGS=10V
1.9
1.6
1.3
1.0
RDS(ON), Normalized
0.7
RDS(ON), On-Resistance(Ohms)
0.4
-100 -50 0 50 100 150 200
TJ, Junction Temperature( C)
Figure 3. Capacitance
1.3
VDS=V
GS
ID=250µA
1.2
1.1
1.0
0.9
0.8
VTH, Normalized
0.7
Gate-Source Threshold Voltage
0.6
-50 -25 0 25 50 75 100 125 150
TJ, Junction Temperature( C)
Figure 5. Gate Threshold Variation
with Temperature
Figure 4. On-Resistance Variation
with Temperature
V
=0
V
GS
0
10
-1
10
IS, Source-drain current (A)
-2
10
0.4 0.6 0.8 1.0
1.41.2
VSD, Body Diode Forward Voltage (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
Page 4
CED840A/CEU840A
10
VDS=400V
ID=7A
8
6
4
2
VGS, Gate to Source Voltage (V)
0
0 5 10 15 25
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
DD
V
IN
V
R
D
V
GS
GEN
R
G
S
R
Limit
DS(ON)
1
10
0
10
ID, Drain Current (A)
TC=25 C
TJ=150 C
Single Pulse
-1
10
0
20
10
1
10
10ms
DC
1ms
10
100ms
2
3
10
VDS, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
on
t
d(off)
t
r
d(on)
V
V
t
OUT
IN
10%
L
OUT
V
t
90%
10% 10%
INVERTED
50% 50%
90%
t
off
f
t
90%
PULSE WIDTH
Figure 9. Switching Test Circuit
0
10
D=0.5
0.2
0.1
-1
10
0.05
r(t),Normalized Effective
Transient Thermal Impedance
0.02
0.01
Single Pulse
-2
10
-5
10
10
Figure 11. Normalized Thermal Transient Impedance Curve
Figure 10. Switching Waveforms
PDM
t1
t2
1. RθJC (t)=r (t) * RθJC
2. RθJC=See Datasheet
3. TJM-TC = P* RθJC (t)
4. Duty Cycle, D=t1/t2
-4
-3
10
-2
10
-1
10
0 10
10
1
Square Wave Pulse Duration (sec)
4
Loading...