Datasheet ceu655_ced655 Datasheet

CED655/CEU655

N-Channel Enhancement Mode Field Effect Transistor

FEATURES

150V, 6.4A, R

Super high dense cell design for extremely low R

High power and current handing capability.

Lead free product is acquired.

TO-251 & TO-252 package.

ABSOLUTE MAXIMUM RATINGS T

Drain-Source Voltage

Gate-Source Voltage

Drain Current-Continuous

Drain Current-Pulsed

Maximum Power Dissipation @ TC = 25 C

Operating and Store Temperature Range TJ,Tstg -55 to 175

= 0.45Ω @VGS = 10V.

DS(ON)

G

S
CEU SERIES
TO-252(D-PAK)

Parameter

a

- Derate above 25 C

.

DS(ON)

D

G

D

S

CED SERIES
TO-251(I-PAK)

= 25 C unless otherwise noted

c

Symbol

V

DS

V

GS

I

D

I

DM

P

D

G

Limit

±20

25.6

0.29

150

6.4

43

PRELIMINARY

D

S

Units

V

V

A

A

W

W/ C

C

Thermal Characteristics

Parameter Symbol Limit Units

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient

This is preliminary information on a new product in development now .

RθJA

1

3.5RθJC

50

Rev 1. 2011.Aug

http://www.cetsemi.comDetails are subject to change without notice .

C/W

C/W

CED655/CEU655

Electrical Characteristics T

= 25 C unless otherwise noted

c

Parameter Symbol Min Units

Off Characteristics

Drain-Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate Body Leakage Current, Forward

Gate Body Leakage Current, Reverse

On Characteristics

b

Gate Threshold Voltage

Static Drain-Source

On-Resistance

Dynamic Characteristics

c

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Switching Characteristics

c

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

V

R

BV

C

C

C

t

d(on)

t

d(off)

Q

Q

DSS

I

DSS

I

GSSF

IGSSR

GS(th)

DS(on)

iss

oss

rss

t

r

t

f

Q

g

gs

gd

Drain-Source Diode Characteristics and Maximun Ratings

Drain-Source Diode Forward Current

Drain-Source Diode Forward Voltage

Notes :

a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Device Mounted on FR4 Board, t < 10 sec.
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
d.Guaranteed by design, not subject to production testing.

b

IS

V

SD

Test Condition

VGS = 0V, ID = 250µA

VDS = 150V, VGS = 0V

VGS = 20V, VDS = 0V

VGS = -20V, VDS = 0V

VGS = VDS, ID = 250µA

VGS = 10V, ID = 2.5A

VDS = 25V, VGS = 0V,
f = 1.0 MHz

VDD = 80V, ID = 1A,
VGS = 10V,R

GEN

= 6Ω

VDS = 80V, ID = 1A,
VGS = 10V

VGS = 0V, IS = 5A

Typ Max

150

2 4

435

85

25

10

1.8

3.2

1

100

-100

0.450.37

2010

63

4623

105

13.3

5

1.2

V

µA

nA

nA

V

Ω

pF

pF

pF

ns

ns

ns

ns

nC

nC

nC

A

V

2

CED655/CEU655

6

5

4

3

2

ID, Drain Current (A)

1

0

0 1 2 43 5 6

VGS=10,9,8,7V

V

VDS, Drain-to-Source Voltage (V)

Figure 1. Output Characteristics

600

500

400

300

200

C, Capacitance (pF)

100

0

0 5 10 15 20 25

C

iss

C

oss

C

rss

VDS, Drain-to-Source Voltage (V)

12

10

8

6

4

=4V

GS

ID, Drain Current (A)

2

0

0 2 4 6

TJ=125C

25 C

-55 C

108

VGS, Gate-to-Source Voltage (V)

Figure 2. Transfer Characteristics

3.0
ID=2.5A

VGS=10V

2.5

2.0

1.5

1.0

RDS(ON), Normalized

0.5

RDS(ON), On-Resistance(Ohms)

0.0

-100 -50 0 50 100 150 200

TJ, Junction Temperature( C)

Figure 3. Capacitance

1.3
VDS=V

GS

ID=250µA

1.2

1.1

1.0

0.9

0.8

VTH, Normalized

0.7

Gate-Source Threshold Voltage

0.6

-50 -25 0 25 50 75 100 125 150

TJ, Junction Temperature( C)

Figure 5. Gate Threshold Variation

with Temperature

Figure 4. On-Resistance Variation

with Temperature

V

=0

V

GS

1

10

0

10

IS, Source-drain current (A)

-1

10

0.4 0.7 1.0 1.3

1.6 1.9

VSD, Body Diode Forward Voltage (V)

Figure 6. Body Diode Forward Voltage

Variation with Source Current

3

CED655/CEU655

10

VDS=80V
ID=1A

8

6

4

2

VGS, Gate to Source Voltage (V)

0

0 2.5 5 7.5 10

Qg, Total Gate Charge (nC)

Figure 7. Gate Charge

DD

V

IN

V

D

V

GS

GEN

R

G

S

2

10

R

Limit

DS(ON)

ID, Drain Current (A)

1

10

0

10

-1

10

TC=25 C
TJ=175 C

Single Pulse

0

10

10

100ms

1ms

10ms

DC

1

2

10

3

10

VDS, Drain-Source Voltage (V)

Figure 8. Maximum Safe

Operating Area

on

t

d(off)

t

r

t

90%

10% 10%

INVERTED

50% 50%

V

V

t

d(on)

OUT

IN

10%

R

L

OUT

V

90%

t

off

f

t

90%

PULSE WIDTH

Figure 9. Switching Test Circuit

0

10

D=0.5

0.2

-1

0.1

10

0.05

10

-2

-5

10

0.02

0.01

Single Pulse

10

r(t),Normalized Effective

Transient Thermal Impedance

Figure 11. Normalized Thermal Transient Impedance Curve

Figure 10. Switching Waveforms

PDM

t1

t2

1. RθJA (t)=r (t) * RθJA

2. RθJA=See Datasheet

3. TJM-TA = P* RθJC (t)

4. Duty Cycle, D=t1/t2

-4

-3

10

-2

10

-1

10

0

10

1

10

Square Wave Pulse Duration (sec)

4