Datasheet cep84a4_ceb84a4 Datasheet

CEP84A4/CEB84A4

N-Channel Enhancement Mode Field Effect Transistor

FEATURES

40V, 90A, R

R

Super high dense cell design for extremely low R

High power and current handing capability.

Lead free product is acquired.

TO-220 & TO-263 package.

ABSOLUTE MAXIMUM RATINGS T

Drain-Source Voltage

Gate-Source Voltage

Drain Current-Continuous@ TC = 25 C

@ TC = 100 C

Drain Current-Pulsed

Maximum Power Dissipation @ TC = 25 C

Operating and Store Temperature Range TJ,T

= 5.1mΩ @VGS = 10V.

DS(ON)

= 7.8mΩ @VGS = 4.5V.

DS(ON)

G

S

CEB SERIES
TO-263(DD-PAK)

Parameter

a

- Derate above 25 C

.

DS(ON)

D

G

G

D

S

CEP SERIES
TO-220

= 25 C unless otherwise noted

c

Symbol

V

DS

V

GS

I

D

I

DM

P

D

stg

D

S

Limit

40

±20

90 A

62

360

71

0.47

-55 to 175 C

Units

W/ C

V

V

A

A

W

Thermal Characteristics

Parameter Symbol Limit Units

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient

Details are subject to change without notice .

C/W

C/W

RθJA

2.1RθJC

62.5

Rev 1. 2010.Oct.

http://www.cetsemi.com

1

CEP84A4/CEB84A4

Electrical Characteristics T

= 25 C unless otherwise noted

c

Parameter Symbol Min Units

Off Characteristics

Drain-Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate Body Leakage Current, Forward

Gate Body Leakage Current, Reverse

On Characteristics

b

Gate Threshold Voltage

Static Drain-Source

On-Resistance

Dynamic Characteristics

c

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Switching Characteristics

c

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

V

R

BV

C

C

C

t

d(on)

t

d(off)

Q

Q

DSS

I

DSS

I

GSSF

IGSSR

GS(th)

DS(on)

iss

oss

rss

t

r

t

f

Q

g

gs

gd

Drain-Source Diode Characteristics and Maximun Ratings

Drain-Source Diode Forward Current

Drain-Source Diode Forward Voltage

Notes :

a.Repetitive Rating : Pulse width limited by maximum junction temperature
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
c.Guaranteed by des ign, not subject to production testing .

b

I

S

V

SD

Test Condition

VGS = 0V, ID = 250µA

VDS = 40V, VGS = 0V

VGS = 20V, VDS = 0V

VGS = -20V, VDS = 0V

VGS = VDS, ID = 250µA

VGS = 10V, ID = 30A

VGS = 4.5V, ID = 20A

VDS = 15V, VGS = 0V,
f = 1.0 MHz

VDD = 15V, ID = 1A, 
VGS = 10V, R

GEN

= 6Ω

VDS = 15V, ID = 16A,
VGS = 10V

VGS = 0V, IS = 20A

Typ Max

40

1 3

3.9

5.6

3070

385

285

19

10

84

22

67

10

12

1

µA

80

-80

nA

nA

5.1 mΩ

7.8

mΩ

pF

pF

pF

38

20

168

44

81

nC

nC

nC

90

1.5

V

V

ns

ns

ns

ns

A

V

2

CEP84A4/CEB84A4

60

VGS=10,9,8,7V

50

40

30

20

ID, Drain Current (A)

10

0

0 1 2 43

VDS, Drain-to-Source Voltage (V)

Figure 1. Output Characteristics

6000

5000

4000

3000

2000

C, Capacitance (pF)

1000

0

0 5 10 15 20 25

C

C

rss

oss

C

iss

VDS, Drain-to-Source Voltage (V)

V

GS

=3V

5 6

150

120

90

60

ID, Drain Current (A)

30

0

0 1 2 3

TJ=125 C

25 C

VGS, Gate-to-Source Voltage (V)

Figure 2. Transfer Characteristics

2.2
ID=30A

VGS=10V

1.9

1.6

1.3

1.0

RDS(ON), Normalized

0.7

RDS(ON), On-Resistance(Ohms)

0.4

-100 -50 0 50 100 150 200

TJ, Junction Temperature( C)

-55 C

54

Figure 3. Capacitance

1.3
VDS=V

GS

ID=250µA

1.2

1.1

1.0

0.9

0.8

VTH, Normalized

0.7

Gate-Source Threshold Voltage

0.6

-50 -25 0 25 50 75 100 125 150

TJ, Junction Temperature( C)

Figure 5. Gate Threshold Variation

with Temperature

Figure 4. On-Resistance Variation

with Temperature

V

=0

V

GS

2

10

1

10

IS, Source-drain current (A)

0

10

0.4 0.6 0.8 1.0

1.2

1.4

VSD, Body Diode Forward Voltage (V)

Figure 6. Body Diode Forward Voltage

Variation with Source Current

3

10

VDS=15V
ID=16A

8

6

4

2

VGS, Gate to Source Voltage (V)

0

0 15 30 45 7560

Qg, Total Gate Charge (nC)

CEP84A4/CEB84A4

3

10

R

Limit

DS(ON)

2

10

1

10

ID, Drain Current (A)

0

10

TC=25 C
TJ=150 C

Single Pulse

-1

10

10

VDS, Drain-Source Voltage (V)

100ms

1ms

10ms

DC

0

1

10

2

10

Figure 7. Gate Charge

IN

V

D

V

GS

GEN

R

G

S

Figure 9. Switching Test Circuit

0

10

D=0.5

0.2

-1

0.1

10

0.05

0.02

10

-2

-5

10

0.01

Single Pulse

-4

10

r(t),Normalized Effective

Transient Thermal Impedance

DD

V

R

L

OUT

V

-3

10

Square Wave Pulse Duration (sec)

Figure 8. Maximum Safe

on

t

r

t

V

V

d(on)

OUT

IN

10%

t

90%

10% 10%

INVERTED

50% 50%

PULSE WIDTH

Figure 10. Switching Waveforms

PDM

-2

10

-1

10

Operating Area

t

off

d(off)

t

90%

90%

t1

t2

1. RθJC (t)=r (t) * RθJC

2. RθJC=See Datasheet

3. TJM-TC = P* RθJC (t)

4. Duty Cycle, D=t1/t2

0

10

f

t

1

10

Figure 11. Normalized Thermal Transient Impedance Curve

4