Datasheet cep3100 Datasheet

CEP3100

N-Channel Enhancement Mode Field Effect Transistor

FEATURES

30V, 47A,R

R

Super high dense cell design for extremely low R

High power and current handing capability.

Lead-free plating ; RoHS compliant.

TO-220 package.

ABSOLUTE MAXIMUM RATINGS T

Drain-Source Voltage

Gate-Source Voltage

Drain Current-Continuous@ TC = 25 C

@ TC = 100 C

Drain Current-Pulsed

Maximum Power Dissipation @ TC = 25 C

Operating and Store Temperature Range TJ,Tstg -55 to 175

= 12mΩ @VGS = 10V.

DS(ON)

= 21mΩ @VGS = 4.5V.

DS(ON)

Parameter

a

- Derate above 25 C

G

D

S

CEP SERIES
TO-220

.

DS(ON)

= 25 C unless otherwise noted

c

Symbol

V

DS

V

GS

I

D

I

DM

P

D

G

Limit

±20

0.32

30

47

33

188

48

PRELIMINARY

D

S

Units

V

V

A

A

A

W

W/ C

C

Thermal Characteristics

Parameter Symbol Limit Units

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient

This is preliminary information on a new product in development now .
Details are subject to change without notice .

RθJA

1

3.1RθJC

62.5

C/W

C/W

Rev 1. 2012.Mar

http://www.cetsemi.com

CEP3100

Electrical Characteristics T

= 25 C unless otherwise noted

A

Parameter Symbol Min Units

Off Characteristics

Drain-Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate Body Leakage Current, Forward

Gate Body Leakage Current, Reverse

On Characteristics

c

Gate Threshold Voltage

Static Drain-Source

On-Resistance

Dynamic Characteristics

d

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Switching Characteristics

d

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

BV

I

IGSSR

V

GS(th)

R

DS(on)

C

C

C

t

d(on)

t

d(off)

Q

Q

DSS

I

DSS

GSSF

iss

oss

rss

t

r

t

f

Q

g

gs

gd

Drain-Source Diode Characteristics and Maximun Ratings

Drain-Source Diode Forward Current

Drain-Source Diode Forward Voltage

Notes :

a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Surface Mounted on FR4 Board, t < 10 sec.
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
d.Guaranteed by design, not subject to production testing.

b

c

I

S

V

SD

Test Condition

VGS = 0V, ID = 250µA

VDS = 30V, VGS = 0V

VGS = 20V, VDS = 0V

VGS = -20V, VDS = 0V

VGS = VDS, ID = 250µA

VGS = 10V, ID = 23A

VGS = 4.5V, ID =11A

VDS = 15V, VGS = 0V,
f = 1.0 MHz

VDD = 15V, ID = 10A,
VGS = 10V, R

GEN

= 3Ω

VDS = 15V, ID = 10A,
VGS = 10V

VGS = 0V, IS = 40A

30

1

Typ Max

1

100

-100

3

129

2116 mΩ

895

215

160

11

22

7

14

31

62

5

10

13.3

27

2.7

1.1

40

1.2

V

µA

nA

nA

V

mΩ

pF

pF

pF

ns

ns

ns

ns

nC

nC

nC

A

V

2

CEP3100

40

32

24

16

ID, Drain Current (A)

8

0

VGS=10,8,6V

0 1

2

VDS, Drain-to-Source Voltage (V)

Figure 1. Output Characteristics

1260

1050

840

630

420

C, Capacitance (pF)

210

0

0 5 10 15 20 25

VDS, Drain-to-Source Voltage (V)

75

60

45

30

ID, Drain Current (A)

TJ=125 C

15

V

=3V

GS

0

3

4

0 2 4 6 8

25 C

-55 C

VGS, Gate-to-Source Voltage (V)

Figure 2. Transfer Characteristics

2.2
ID=23A

VGS=10V

C

iss

C

oss

C

rss

1.9

1.6

1.3

1.0

RDS(ON), Normalized

0.7

RDS(ON), On-Resistance(Ohms)

0.4

-100 -50 0 50 100 150 200

TJ, Junction Temperature( C)

Figure 3. Capacitance

1.3
VDS=V

GS

ID=250µA

1.2

1.1

1.0

0.9

0.8

VTH, Normalized

0.7

Gate-Source Threshold Voltage

0.6

-50 -25 0 25 50 75 100 125 150

TJ, Junction Temperature( C)

Figure 5. Gate Threshold Variation

with Temperature

Figure 4. On-Resistance Variation

with Temperature

V

=0

V

GS

2

10

1

10

IS, Source-drain current (A)

0

10

0.4 0.6 0.8 1.0

1.41.2

VSD, Body Diode Forward Voltage (V)

Figure 6. Body Diode Forward Voltage

Variation with Source Current

3

CEP3100

10

VDS=15V
ID=10A

8

6

4

2

VGS, Gate to Source Voltage (V)

0

0

3 6 9 1512

Qg, Total Gate Charge (nC)

Figure 7. Gate Charge

3

10

R

Limit

DS(ON)

2

10

1

10

ID, Drain Current (A)

0

10

TC=25 C
TJ=175 C

Single Pulse

-1

10

0

10

10ms

DC

1ms

100ms

1

10

2

10

VDS, Drain-Source Voltage (V)

Figure 8. Maximum Safe

Operating Area

DD

V

on

t

d(off)

t

r

t

90%

10% 10%

INVERTED

50% 50%

V

V

t

d(on)

OUT

IN

10%

R

IN

V

V

GS

GEN

R

G

L

D

OUT

V

S

90%

t

off

f

t

90%

PULSE WIDTH

Figure 9. Switching Test Circuit

0

10

D=0.5

0.2

-1

0.1

10

0.05

r(t),Normalized Effective

Transient Thermal Impedance

0.02

0.01
Single Pulse

-2

10

-5

10

-4

10

Figure 11. Normalized Thermal Transient Impedance Curve

Figure 10. Switching Waveforms

-3

10

-2

10

Square Wave Pulse Duration (sec)

4

PDM

t1

t2

1. RθJC (t)=r (t) * RθJC

2. RθJC=See Datasheet

3. TJM-TC = P* RθJC (t)

4. Duty Cycle, D=t1/t2

-1

10

0

10

1

10