Datasheet cep3060_ceb3060 Datasheet

CEP3060/CEB3060

N-Channel Enhancement Mode Field Effect Transistor

FEATURES

30V, 105A,R

R

Super high dense cell design for extremely low R

= 6mΩ @VGS = 10V.

DS(ON)

= 8mΩ @VGS = 4.5V.

DS(ON)

DS(ON)

.

High power and current handing capability.

Lead free product is acquired.

TO-220 & TO-263 package.

D

G

G

S

CEB SERIES
TO-263(DD-PAK)

ABSOLUTE MAXIMUM RATINGS T

Parameter

Drain-Source Voltage

Gate-Source Voltage

Drain Current-Continuous

Drain Current-Pulsed

Maximum Power Dissipation @ TC = 25 C

a

- Derate above 25 C

G

D

S

CEP SERIES
TO-220

= 25 C unless otherwise noted

c

Symbol

V

DS

V

GS

I

D

I

DM

P

D

Limit

±20

0.83

Operating and Store Temperature Range TJ,Tstg -55 to 175

30

105

420

125

D

S

Units

V

V

A

A

W

W/ C

C

Thermal Characteristics

Parameter Symbol Limit Units

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient

Details are subject to change without notice .

C/W

C/W

RθJA

1.2RθJC

62.5

Rev 2. 2007.Oct

http://www.cetsemi.com

1

CEP3060/CEB3060

Electrical Characteristics T

= 25 C unless otherwise noted

A

Parameter Symbol Min Units

Off Characteristics

Drain-Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate Body Leakage Current, Forward

Gate Body Leakage Current, Reverse

On Characteristics

c

Gate Threshold Voltage

Static Drain-Source

On-Resistance

Dynamic Characteristics

d

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Switching Characteristics

d

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

BV

I

IGSSR

V

GS(th)

R

DS(on)

C

C

C

t

d(on)

t

d(off)

Q

Q

DSS

I

DSS

GSSF

iss

oss

rss

t

r

t

f

Q

g

gs

gd

Drain-Source Diode Characteristics and Maximun Ratings

Drain-Source Diode Forward Current

Drain-Source Diode Forward Voltage

Notes :

a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Surface Mounted on FR4 Board, t < 10 sec.
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
d.Guaranteed by design, not subject to production testing.

b

c

I

S

V

SD

Test Condition

VGS = 0V, ID = 250µA

VDS = 30V, VGS = 0V

VGS = 20V, VDS = 0V

VGS = -20V, VDS = 0V

VGS = VDS, ID = 250µA

VGS = 10V, ID = 35A

VGS = 4.5V, ID =28A

VDS = 15V, VGS = 0V,
f = 1.0 MHz

VDD = 15V, ID = 1A,
VGS = 10V, R

GEN

= 6Ω

VDS = 15V, ID = 16A,
VGS = 5V

VGS = 0V, IS = 35A

30

1

Typ Max

100

-100

2475

320

180

16

32

6

12

49

98

11

22

15.8

21

4.8

2.8

105

1.3

V

1

µA

nA

nA

V

3

65

mΩ

86.5 mΩ

pF

pF

pF

ns

ns

ns

ns

nC

nC

nC

A

V

2

CEP3060/CEB3060

100

VGS=10,8,6V

80

60

40

ID, Drain Current (A)

20

0

0 0.5

1

VDS, Drain-to-Source Voltage (V)

Figure 1. Output Characteristics

3600

3000

2400

1800

1200

C, Capacitance (pF)

600

C

rss

0

0 5 10 15 20 25

C

iss

C

oss

VDS, Drain-to-Source Voltage (V)

1.5

150

120

V

=4V

GS

2

ID, Drain Current (A)

90

60

30

TJ=125 C

0

1 2

25 C

3

-55 C

4

VGS, Gate-to-Source Voltage (V)

Figure 2. Transfer Characteristics

2.2
ID=35A

VGS=10V

1.9

1.6

1.3

1.0

RDS(ON), Normalized

0.7

RDS(ON), On-Resistance(Ohms)

0.4

-100 -50 0 50 100 150 200

TJ, Junction Temperature( C)

Figure 3. Capacitance

1.3
VDS=V

GS

ID=250µA

1.2

1.1

1.0

0.9

0.8

VTH, Normalized

0.7

Gate-Source Threshold Voltage

0.6

-50 -25 0 25 50 75 100 125 150

TJ, Junction Temperature( C)

Figure 5. Gate Threshold Variation

with Temperature

Figure 4. On-Resistance Variation

with Temperature

V

=0

V

GS

2

10

1

10

IS, Source-drain current (A)

0

10

0.6 0.8 1.0 1.2

1.61.4

VSD, Body Diode Forward Voltage (V)

Figure 6. Body Diode Forward Voltage

Variation with Source Current

3

10

VDS=15V

ID=16A

8

6

4

2

VGS, Gate to Source Voltage (V)

0

0 6 12 18 24 30

Qg, Total Gate Charge (nC)

CEP3060/CEB3060

3

10

R

Limit

DS(ON)

2

10

1

10

ID, Drain Current (A)

0

10

TC=25 C
TJ=175 C

Single Pulse

-1

10

10

VDS, Drain-Source Voltage (V)

100ms

1ms

10ms
DC

0

1

10

2

10

Figure 7. Gate Charge

IN

V

D

V

GS

GEN

R

G

S

Figure 9. Switching Test Circuit

0

10

D=0.5

0.2

-1

0.1

10

0.05

r(t),Normalized Effective

Transient Thermal Impedance

0.02

0.01
Single Pulse

-2

10

-5

10

-4

10

DD

V

R

L

OUT

V

-3

10

Square Wave Pulse Duration (sec)

Figure 8. Maximum Safe

on

t

r

t

90%

10% 10%

INVERTED

50% 50%

V

V

t

d(on)

OUT

IN

10%

PULSE WIDTH

Figure 10. Switching Waveforms

-2

10

-1

10

Operating Area

t

d(off)

t

90%

PDM

t1

t2

1. RθJC (t)=r (t) * RθJC

2. RθJC=See Datasheet

3. TJM-TC = P* RθJC (t)

4. Duty Cycle, D=t1/t2

0

10

off

f

t

90%

1

10

Figure 11. Normalized Thermal Transient Impedance Curve

4