Datasheet cem4435a Datasheet

CEM4435A

P-Channel Enhancement Mode Field Effect Transistor

FEATURES

-30V, -8A, R

R

Super high dense cell design for extremely low R

High power and current handing capability.

Lead free product is acquired.

Surface mount Package.

ABSOLUTE MAXIMUM RATINGS T

Drain-Source Voltage

Gate-Source Voltage

Drain Current-Continuous

Drain Current-Pulsed

Maximum Power Dissipation

Operating and Store Temperature Range TJ,Tstg -55 to 150

= 20mΩ @VGS = -10V.

DS(ON)

= 33mΩ @VGS = -4.5V.

DS(ON)

Parameter

a

SO-8

.

DS(ON)

1

= 25 C unless otherwise noted

A

Symbol

V

DS

V

GS

I

D

I

DM

P

D

D D D D

8 7 6 5

1 2 3 4

S S S G

Limit

-30

±20

-8

-32

2.5

Units

V

V

A

A

W

C

Thermal Characteristics

Parameter Symbol Limit Units

Thermal Resistance, Junction-to-Ambient

Specification and data are subject to change without notice .

b

C/W50RθJA

Rev 2. 2010.July

http://www.cetsemi.com

CEM4435A

Electrical Characteristics T

= 25 C unless otherwise noted

A

Parameter Symbol Min Units

Off Characteristics

Drain-Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate Body Leakage Current, Forward

Gate Body Leakage Current, Reverse

On Characteristics

c

Gate Threshold Voltage

Static Drain-Source

On-Resistance

Forward Transconductance

Dynamic Characteristics

d

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Switching Characteristics

d

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

V

R

BV

C

C

C

t

d(on)

t

d(off)

Q

Q

DSS

I

DSS

I

GSSF

IGSSR

GS(th)

DS(on)

g

FS

iss

oss

rss

t

r

t

f

Q

g

gs

gd

Drain-Source Diode Characteristics and Maximun Ratings

Drain-Source Diode Forward Current

Drain-Source Diode Forward Voltage

Notes :

a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Surface Mounted on FR4 Board, t < 10 sec.
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
d.Guaranteed by design, not subject to production testing.


b

c

I

S

V

SD

Test Condition

VGS = 0V, ID = -250µA

VDS = -24V, VGS = 0V

VGS = 20V, VDS = 0V

VGS = -20V, VDS = 0V

VGS = VDS, ID = -250µA

VGS = -10V, ID = -8A

VGS = -4.5V, ID = -5A

VDS = -15V, ID = -8A

VDS = -15V, VGS = 0V,
f = 1.0 MHz

VDD = -10V, ID = -1A,
VGS = -10V, R

GEN

= 6Ω

VDS = -15V, ID = -7A,
VGS = -4.5V

VGS = 0V, IS = -2.1A

Typ Max

-30

-1 -3

13

1690

285

210

15

9

60

20

19

5

7

-1

100

-100

2017

3325 mΩ

30

18

120

40

25

-2.1

-1.2

V

µA

nA

nA

V

mΩ

S

pF

pF

pF

ns

ns

ns

ns

nC

nC

nC

A

V

5

CEM4435A

25

-VGS=10,8,7,6,5V

20

15

10

-ID, Drain Current (A)

5

0

0.0 0.5 2.0

-VDS, Drain-to-Source Voltage (V)

Figure 1. Output Characteristics

2400

2000

1600

1200

800

C, Capacitance (pF)

400

C

rss

0

0 5 10 15 20 25

-VDS, Drain-to-Source Voltage (V)

30

24

25 C

-V

=4V

GS

-V

=3V

GS

2.51.51.0

18

12

-ID, Drain Current (A)

6

TJ=125 C

0

0 2 4 61 3 5

-55 C

-VGS, Gate-to-Source Voltage (V)

Figure 2. Transfer Characteristics

2.2
ID=-8A

VGS=-10V

C

iss

C

oss

1.9

1.6

1.3

1.0

RDS(ON), Normalized

0.7

RDS(ON), On-Resistance(Ohms)

0.4

-100 -50 0 50 100 150 200

TJ, Junction Temperature( C)

Figure 3. Capacitance

1.3
VDS=V

GS

ID=-250µA

1.2

1.1

1.0

0.9

0.8

VTH, Normalized

0.7

Gate-Source Threshold Voltage

0.6

-50 -25 0 25 50 75 100 125 150

TJ, Junction Temperature( C)

Figure 5. Gate Threshold Variation

with Temperature

Figure 4. On-Resistance Variation

with Temperature

V

=0

V

GS

1

10

0

10

-IS, Source-drain current (A)

-1

10

0.4 0.6 0.8 1.0

-VSD, Body Diode Forward Voltage (V)

Figure 6. Body Diode Forward Voltage

Variation with Source Current

1.41.2

5

VDS=-15V

ID=-7A

4

3

2

1

-VGS, Gate to Source Voltage (V)

0

0 4 8 20 2412 16

Qg, Total Gate Charge (nC)

CEM4435A

2

10

R

Limit

DS(ON)

1

10

0

10

-1

10

-ID, Drain Current (A)

-2

10

10

TA=25 C
TJ=150 C

Single Pulse

-2

10

DC

-1

10

-VDS, Drain-Source Voltage (V)

100ms

1s

0

10ms

1ms

10

1

2

10

Figure 7. Gate Charge

IN

V

D

V

GS

GEN

R

G

S

Figure 9. Switching Test Circuit

0

10

D=0.5

0.2

-1

0.1

10

0.05

0.02

0.01

-2

10

r(t),Normalized Effective

Single Pulse

Transient Thermal Impedance

-3

10

-4

10

-3

10

DD

V

R

L

OUT

V

-2

10

Square Wave Pulse Duration (sec)

Figure 8. Maximum Safe

on

t

r

t

90%

10% 10%

INVERTED

50% 50%

V

V

d(on)

t

OUT

IN

10%

PULSE WIDTH

Figure 10. Switching Waveforms

PDM

-1

10

0

10

Operating Area

t

off

d(off)

t

90%

90%

t1

t2

1. RθJA (t)=r (t) * RθJA

2. RθJA=See Datasheet

3. TJM-TA = P* RθJA (t)

4. Duty Cycle, D=t1/t2

1

10

f

t

2

10

Figure 11. Normalized Thermal Transient Impedance Curve