Datasheet cem3252 Datasheet

Page 1
N-Channel Enhancement Mode Field Effect Transistor
FEATURES
CEM3252
30V, 7.5A, R
Super high dense cell design for extremely low R
High power and current handing capability.
Lead free product is acquired.
Surface mount Package.
ABSOLUTE MAXIMUM RATINGS T
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
Drain Current-Pulsed
Maximum Power Dissipation
Operating and Store Temperature Range TJ,Tstg -55 to 150
= 28mΩ @VGS = 10V.
DS(ON)
= 40mΩ @VGS = 4.5V.
DS(ON)
Parameter
a
SO-8
.
DS(ON)
1
= 25 C unless otherwise noted
A
Symbol Limit
V
DS
V
GS
I
D
I
DM
P
D
D D D D
8 7 6 5
1 2 3 4
S S S G
30
±20
7.5
25
2.5
Units
V
V
A
A
W
C
Thermal Characteristics
Parameter Symbol Limit Units
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case C/W25RθJC
Details are subject to change without notice .
b
C/W50RθJA
Rev 3. 2011.Sep
http://www.cetsemi.com
1
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CEM3252
Electrical Characteristics T
Parameter Symbol Min Units
= 25 C unless otherwise noted
A
Test Condition
Off Characteristics
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
BV
I
DSS
I
GSSF
IGSSR
DSS
VGS = 0V, ID = 250µA
VDS = 30V, VGS = 0V
VGS = 20V, VDS = 0V
VGS = -20V, VDS = 0V
On Characteristics
Gate Threshold Voltage
Static Drain-Source
On-Resistance
Dynamic Characteristics
d
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
d
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
GS(th)
R
DS(on)
t
d(on)
t
d(off)
Q
Q
VGS = VDS, ID = 250µA
VGS = 10V, ID = 7A
VGS = 4.5V, ID = 3.5A
C
iss
C
oss
C
rss
t
r
t
f
Q
g
gs
gd
VDS = 15V, VGS = 0V, f = 1.0 MHz
VDD = 15V, ID = 7A, VGS = 10V, R
VDS = 15V, ID = 7A, VGS = 10V
Drain-Source Diode Characteristics and Maximun Ratings
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Surface Mounted on FR4 Board, t < 10 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing. 
e.R
θJA
is the sum of junction-to-case-ambient thermal resistance where the case tmermal reference is defined
as the solder mounting surface of the drain pins. R
.
the user's board design
b
c
I
S
V
SD
θJc
is guaranteed by design while R
VGS = 0V, IS = 2.3A
= 3Ω
GEN
θJA
is determined by
Typ Max
30
100
-100
1.0 3.0
2822
4030 mΩ
575
135
105
10
25
13.8
20
5
10
50
5
10
18
1.4
3.2
2.3
1.2
V
1
µA
nA
nA
V
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
A
V
1. 50CW when mounted
2
on a 1in
pad of 2 oz
copper
Scale 1 : 1 on letter size paper
f.Pulse Test : Pluse Width < 300us,Duty cycle <2%
2. 105CW when mounted on a 0.4in
2
pad of 2 oz
copper
2
3. 125CW when mounted on a minimun pad
Page 3
CEM3252
8
VGS=10,9,8,7,6V
6
4
2
ID, Drain Current (A)
0
0 0.4 0.8 2.01.2 1.6
VDS, Drain-to-Source Voltage (V)
Figure 1. Output Characteristics
900
750
600
450
300
C, Capacitance (pF)
150
0
0 3 6 9 12 15
C
iss
C
oss
C
rss
VDS, Drain-to-Source Voltage (V)
12
9
6
V
=3V
GS
3
ID, Drain Current (A)
TJ=125 C
0
1.5 2.5 3.5 4.52.0 3.0 4.0
25 C
-55 C
VGS, Gate-to-Source Voltage (V)
Figure 2. Transfer Characteristics
2.2 ID=7A
VGS=10V
1.9
1.6
1.3
1.0
RDS(ON), Normalized
0.7
RDS(ON), On-Resistance(Ohms)
0.4
-100 -50 0 50 100 150 200
TJ, Junction Temperature( C)
Figure 3. Capacitance
1.3 VDS=V
GS
ID=250µA
1.2
1.1
1.0
0.9
0.8
VTH, Normalized
0.7
Gate-Source Threshold Voltage
0.6
-50 -25 0 25 50 75 100 125 150
TJ, Junction Temperature( C)
Figure 5. Gate Threshold Variation
with Temperature
Figure 4. On-Resistance Variation
with Temperature
V
=0
V
GS
1
10
0
10
IS, Source-drain current (A)
-1
10
0.4 0.6 0.8 1.0 1.41.2
VSD, Body Diode Forward Voltage (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
Page 4
10
VDS=15V
ID=7A
8
6
4
2
VGS, Gate to Source Voltage (V)
0
0 3 6 9 1512
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
CEM3252
2
10
R
Limit
DS(ON)
1
10
0
10
-1
10
ID, Drain Current (A)
-2
10
TA=25 C TJ=150 C
Single Pulse
-2
10
-1
10
10
VDS, Drain-Source Voltage (V)
1ms
10ms
100ms
1s
DC
0
1
10
2
10
IN
V
D
V
GS
GEN
R
G
S
Figure 9. Switching Test Circuit
0
10
D=0.5
0.2
-1
0.1
10
0.05
0.02
0.01
-2
10
r(t),Normalized Effective
Single Pulse
Transient Thermal Impedance
-3
10
-4
10
-3
10
DD
V
R
L
OUT
V
-2
10
Square Wave Pulse Duration (sec)
Figure 8. Maximum Safe
on
t
r
t
90%
10% 10%
INVERTED
50% 50%
V
V
d(on)
t
OUT
IN
10%
PULSE WIDTH
Figure 10. Switching Waveforms
PDM
-1
10
0
10
Operating Area
t
off
d(off)
t
90%
90%
t1
t2
1. RθJA (t)=r (t) * RθJA
2. RθJA=See Datasheet
3. TJM-TA = P* RθJA (t)
4. Duty Cycle, D=t1/t2
1
10
f
t
2
10
Figure 11. Normalized Thermal Transient Impedance Curve
4
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