Datasheet ceh2321a Datasheet

CEH2321A

P-Channel Enhancement Mode Field Effect Transistor

FEATURES

-20V, -4.8A, R

R

High dense cell design for extremely low R

Rugged and reliable.

Lead-free plating ; RoHS compliant.

TSOP-6 package.

ABSOLUTE MAXIMUM RATINGS T

Drain-Source Voltage

Gate-Source Voltage

Drain Current-Continuous

Drain Current-Pulsed

Maximum Power Dissipation

Operating and Store Temperature Range TJ,Tstg -55 to 150

= 55mΩ @VGS = -4.5V.

DS(ON)

= 62mΩ @VGS = -2.5V.

DS(ON)

Parameter

a

DS(ON)

6

.

4

5

3

2

1

TSOP-6

= 25 C unless otherwise noted

A

Symbol

V

DS

V

GS

I

D

I

DM

P

D

G(3)

Limit

-19.2

-20

±12

-4.8

2.0

PRELIMINARY

D(1,2,5,6,)

S(4)

Units

V

V

A

A

W

C

Thermal Characteristics

Parameter Symbol Limit Units

Thermal Resistance, Junction-to-Ambient

This is preliminary information on a new product in development now .
Details are subject to change without notice

b

1

C/W62.5RθJA

Rev 1.

http://www.cetsemi.com

2012.Feb

CEH2321A

Electrical Characteristics T

= 25 C unless otherwise noted

A

Parameter Symbol Min Units

Off Characteristics

Drain-Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate Body Leakage Current, Forward

Gate Body Leakage Current, Reverse

On Characteristics

c

Gate Threshold Voltage

Static Drain-Source

On-Resistance

Dynamic Characteristics

d

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Switching Characteristics

d

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

BV

I

IGSSR

V

GS(th)

R

DS(on)

C

C

C

t

d(on)

t

d(off)

Q

Q

DSS

I

DSS

GSSF

iss

oss

rss

t

r

t

f

Q

g

gs

gd

Drain-Source Diode Characteristics and Maximun Ratings

Drain-Source Diode Forward Current

Drain-Source Diode Forward Voltage

Notes :

a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Surface Mounted on FR4 Board, t < 5 sec.
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
d.Guaranteed by design, not subject to production testing.


b

c

I

S

V

SD

Test Condition

VGS = 0V, ID = -250µA

VDS = -16V, VGS = 0V

VGS = 12V, VDS = 0V

VGS = -12V, VDS = 0V

VGS = VDS, ID = -250µA

VGS = -4.5V, ID = -4.5A

VGS = -2.5V, ID = -3.6A

VDS = -10V, VGS = 0V,
f = 1.0 MHz

VDD = -10V, ID = -3.8A,
VGS = -4.5V, R

GEN

= 3Ω

VDS = -10V, ID = -3.8A,
VGS = -4.5V

VGS = 0V, IS = -1.3A

-20

-0.6

Typ Max

-1

100

-100

-1.5

5539

6247 mΩ

840

140

105

11

22

5

10

33

66

8

16

9

12

1

2

-1.3

-1.2

V

µA

nA

nA

V

mΩ

pF

pF

pF

ns

ns

ns

ns

nC

nC

nC

A

V

2

CEH2321A

2.5

-VGS=4.5,3.0,2.5V

2.0

1.5

1.0

-ID, Drain Current (A)

0.5

0

0.0 0.5 2.0 2.51.51.0

-VDS, Drain-to-Source Voltage (V)

Figure 1. Output Characteristics

1200

1000

800

600

400

C, Capacitance (pF)

200

0

0 2 4 6 8 10

C

iss

C

oss

C

rss

-VDS, Drain-to-Source Voltage (V)

10

8

6

4

-ID, Drain Current (A)

-V

=1V

GS

2

TJ=125 C

0

0.0 1.0 2.0 3.00.5 1.5 2.5

25 C

-55 C

-VGS, Gate-to-Source Voltage (V)

Figure 2. Transfer Characteristics

2.2
ID=-4.5A

VGS=-4.5V

1.9

1.6

1.3

1.0

RDS(ON), Normalized

0.7

RDS(ON), On-Resistance(Ohms)

0.4

-100 -50 0 50 100 150 200

TJ, Junction Temperature( C)

Figure 3. Capacitance

1.3
VDS=V

GS

ID=-250µA

1.2

1.1

1.0

0.9

0.8

VTH, Normalized

0.7

Gate-Source Threshold Voltage

0.6

-50 -25 0 25 50 75 100 125 150

TJ, Junction Temperature( C)

Figure 5. Gate Threshold Variation

with Temperature

Figure 4. On-Resistance Variation

with Temperature

V

=0

V

GS

1

10

0

10

-IS, Source-drain current (A)

-1

10

0.2 0.4 0.6 0.8

1.21.0

-VSD, Body Diode Forward Voltage (V)

Figure 6. Body Diode Forward Voltage

Variation with Source Current

3

5

VDS=-10V

ID=-3.8A

4

3

2

1

-VGS, Gate to Source Voltage (V)

0

0 2.5 5 7.5 10

Qg, Total Gate Charge (nC)

CEH2321A

2

10

R

Limit

DS(ON)

1

10

0

10

-1

10

-ID, Drain Current (A)

-2

10

TA=25 C
TJ=150 C

Single Pulse

-1

10

10

-VDS, Drain-Source Voltage (V)

10ms

100ms

1s

DC

0

1

10

2

10

Figure 7. Gate Charge

IN

V

D

V

GS

GEN

R

G

S

Figure 9. Switching Test Circuit

0

10

D=0.5

0.2

-1

0.1

10

0.05

0.02

0.01

-2

10

r(t),Normalized Effective

Single Pulse

Transient Thermal Impedance

-3

10

-4

10

-3

10

DD

V

R

L

OUT

V

-2

10

Square Wave Pulse Duration (sec)

Figure 8. Maximum Safe

on

t

r

t

90%

10% 10%

INVERTED

50% 50%

V

V

d(on)

t

OUT

IN

10%

PULSE WIDTH

Figure 10. Switching Waveforms

PDM

-1

10

0

10

Operating Area

t

off

d(off)

t

90%

90%

t1

t2

1. RθJA (t)=r (t) * RθJA

2. RθJA=See Datasheet

3. TJM-TA = P* RθJA (t)

4. Duty Cycle, D=t1/t2

1

10

f

t

2

10

Figure 11. Normalized Thermal Transient Impedance Curve

4