Datasheet ceg8205a Datasheet

CEG8205A

Dual N-Channel Enhancement Mode Field Effect Transistor

FEATURES

20V, 6A, R

R

Super High dense cell design for extremely low R

= 25mΩ @VGS = 4.5V.

DS(ON)

= 35mΩ @VGS = 2.5V.

DS(ON)

DS(ON)

.

High power and current handing capability.

1

Lead free product is acquired.

TSSOP-8 for Surface Mount Package.

G2

S2

S2

D

TSSOP-8

ABSOLUTE MAXIMUM RATINGS T

Parameter

Drain-Source Voltage

Gate-Source Voltage

Drain Current-Continuous

Drain Current-Pulsed

Maximum Power Dissipation

a

G1

S1

S1

D

= 25 C unless otherwise noted

A

Symbol

V

DS

V

GS

I

D

I

DM

P

D

2

S1

3

S1

4

G1

Limit

D

Operating and Store Temperature Range TJ,Tstg -55 to 150

20

±12

6

25

1.5

8

7

6

5

D

S2

S2

G2

Units

V

V

A

A

W

C

Thermal Characteristics

Parameter Symbol Limit Units

Thermal Resistance, Junction-to-Ambient

Details are subject to change without notice .

b

C/W83RθJA

Rev 2. 2010.Dec

http://www.cetsemi.com

1

CEG8205A

Electrical Characteristics T

= 25 C unless otherwise noted

A

Parameter Symbol Min Units

Off Characteristics

Drain-Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate Body Leakage Current, Forward

Gate Body Leakage Current, Reverse

On Characteristics

c

Gate Threshold Voltage

Static Drain-Source

On-Resistance

Dynamic Characteristics

d

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Switching Characteristics

d

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

V

R

BV

C

C

C

t

d(on)

t

d(off)

Q

Q

DSS

I

DSS

I

GSSF

IGSSR

GS(th)

DS(on)

iss

oss

rss

t

r

t

f

Q

g

gs

gd

Drain-Source Diode Characteristics and Maximun Ratings

Drain-Source Diode Forward Current

Drain-Source Diode Forward Voltage

Notes :

a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Surface Mounted on FR4 Board, t < 10 sec.
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
d.Guaranteed by design, not subject to production testing.


b

c

I

S

V

SD

Test Condition

VGS = 0V, ID = 250µA

VDS = 18V, VGS = 0V

VGS = 12V, VDS = 0V

VGS = -12V, VDS = 0V

VGS = VDS, ID = 250µA

VGS = 4.5V, ID = 4.5A

VGS = 2.5V, ID = 3.5A

VDS = 8V, VGS = 0V, 
f = 1.0 MHz

VDD = 10V, ID = 1A,
VGS = 4.5V, R

GEN

= 6Ω

VDS = 10V, ID = 6A,
VGS = 4.5V

VGS = 0V, IS = 1.7A

Typ Max

20

100

-100

0.5 1.2

2521

3527 mΩ

720

130

95

10

34

6.8

20

7

14

68

6

12

8.8

0.5

1.8

1.7

1.2

V

1

µA

nA

nA

V

mΩ

pF

pF

pF

ns

ns

ns

ns

nC

nC

nC

A

V

2

CEG8205A

10

ID, Drain Current (A)

VGS=4.5,3.5,2.5V

8

6

4

2

0

0 1 2 3

VDS, Drain-to-Source Voltage (V)

Figure 1. Output Characteristics

900

750

600

450

300

C, Capacitance (pF)

150

0

0 2 4 6 8 10

VDS, Drain-to-Source Voltage (V)

C

iss

C

oss

C

rss

VGS=2.0V

VGS=1.5V

30

24

18

12

ID, Drain Current (A)

6

TJ=125 C

0

0 1 2 32.0

25 C

VGS, Gate-to-Source Voltage (V)

Figure 2. Transfer Characteristics

1.8
ID=4.5A

VGS=4.5V

1.6

1.4

1.2

1.0

RDS(ON), Normalized

0.8

RDS(ON), On-Resistance(Ohms)

0.6

-100 -50 0 50 100 150 200

TJ, Junction Temperature( C)

-55 C

Figure 3. Capacitance

1.3
VDS=V

GS

ID=250µA

1.2

1.1

1.0

0.9

0.8

VTH, Normalized

0.7

Gate-Source Threshold Voltage

0.6

-50 -25 0 25 50 75 100 125 150

TJ, Junction Temperature( C)

Figure 5. Gate Threshold Variation

with Temperature

Figure 4. On-Resistance Variation

with Temperature

V

=0

V

GS

1

10

0

10

IS, Source-drain current (A)

-1

10

0.4 0.6 0.8 1.0

1.41.2

VSD, Body Diode Forward Voltage (V)

Figure 6. Body Diode Forward Voltage

Variation with Source Current

3

CEG8205A

5

VDS=10V

ID=4.5A

4

3

2

1

VGS, Gate to Source Voltage (V)

0

0 2 4 6 8

Qg, Total Gate Charge (nC)

Figure 7. Gate Charge

DD

V

IN

V

D

V

GS

GEN

R

G

S

2

10

R

Limit

DS(ON)

1

10

0

10

-1

10

ID, Drain Current (A)

-2

10

TA=25 C
TJ=150 C

Single Pulse

-2

10

DC

-1

10

10

100ms

1s

0

10ms

1ms

10

1

2

10

VDS, Drain-Source Voltage (V)

Figure 8. Maximum Safe

Operating Area

on

t

d(off)

t

r

t

90%

10% 10%

INVERTED

50% 50%

V

V

d(on)

t

OUT

IN

10%

R

L

OUT

V

90%

t

off

f

t

90%

PULSE WIDTH

Figure 9. Switching Test Circuit

0

10

D=0.5

0.2

-1

0.1

10

0.05

0.02

0.01

-2

10

r(t),Normalized Effective

Single Pulse

Transient Thermal Impedance

-3

10

-4

10

-3

10

Figure 11. Normalized Thermal Transient Impedance Curve

Figure 10. Switching Waveforms

-2

10

-1

10

Square Wave Pulse Duration (sec)

4

PDM

t1

t2

1. RθJA (t)=r (t) * RθJA

2. RθJA=See Datasheet

3. TJM-TA = P* RθJA (t)

4. Duty Cycle, D=t1/t2

0

10

1

10

2

10