Datasheet cef05n6 Datasheet

CEF05N6

N-Channel Enhancement Mode Field Effect Transistor

FEATURES

650V, 5A, R

Super high dense cell design for extremely low R

High power and current handing capability.

Lead free product is acquired.

TO-220F full-pak for through hole.

ABSOLUTE MAXIMUM RATINGS T

Drain-Source Voltage

Gate-Source Voltage

Drain Current-Continuous

Drain Current-Pulsed

Maximum Power Dissipation @ TC = 25 C

Operating and Store Temperature Range TJ,Tstg -55 to 150

= 2.4Ω @VGS = 10V.

DS(ON)

Parameter

a

- Derate above 25 C

.

DS(ON)

G

D

S

CEF SERIES
TO-220F

= 25 C unless otherwise noted

c

Symbol

V

DS

V

GS

I

D

I

DM

P

D

G

Limit

±30

0.28

650

5

20

35

PRELIMINARY

D

S

Units

V

V

A

A

W

W/ C

C

Thermal Characteristics

Parameter Symbol Limit Units

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient

This is preliminary information on a new product in development now .
Details are subject to change without notice .

RθJA

1

3.6RθJC

65

Rev 3. 2009.Jun.

http://www.cetsemi.com

C/W

C/W

CEF05N6

Electrical Characteristics T

= 25 C unless otherwise noted

c

Parameter Symbol Min Units

Off Characteristics

Drain-Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate Body Leakage Current, Forward

Gate Body Leakage Current, Reverse

On Characteristics

b

Gate Threshold Voltage

Static Drain-Source

On-Resistance

Dynamic Characteristics

c

Forward Transconductance

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Switching Characteristics

c

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

V

R

BV

C

C

C

t

d(on)

t

d(off)

Q

Q

DSS

I

DSS

I

GSSF

IGSSR

GS(th)

DS(on)

g

FS

iss

oss

rss

t

r

t

f

Q

g

gs

gd

Drain-Source Diode Characteristics and Maximun Ratings

Drain-Source Diode Forward Current

Drain-Source Diode Forward Voltage

Notes :

a.Repetitive Rating : Pulse width limited by maximum junction temperature.
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.
c.Guaranteed by design, not subject to production testing.

b

I

S

V

SD

Test Condition

VGS = 0V, ID = 250µA

VDS = 600V, VGS = 0V

VGS = 30V, VDS = 0V

VGS = -30V, VDS = 0V

VGS = VDS, ID = 250µA

VGS = 10V, ID = 2A

VDS = 40V, ID = 2A

VDS = 25V, VGS = 0V,
f = 1.0 MHz

VDD = 300V, ID = 3A,
VGS = 10V, R

GEN

= 25Ω

VDS = 480V, ID = 3A,
VGS = 10V

VGS = 0V, IS = 3A

Typ Max

650

100

-100

2.5 4.5

2

19

555

80

15

21

10

34

13

10

13.3

2.4

3.9

25

2.4

42

20

68

26

1.5

4

V

µA

nA

nA

V

Ω

S

pF

pF

pF

ns

ns

ns

ns

nC

nC

nC

5

A

V

2

CEF05N6



18

15

12

9

6

ID, Drain Current (A)

3

0

0.0 20 40 8060 100 120

VGS=10,8,7V

V

=5V

GS

V

=4V

GS

VDS, Drain-to-Source Voltage (V)

Figure 1. Output Characteristics

1200

1000

800

C

600

400

C, Capacitance (pF)

200

0

0 5 10 15 20 25

iss

C

oss

C

rss

VDS, Drain-to-Source Voltage (V)

6

5

4

3

2

ID, Drain Current (A)

1

0

TJ=125C

1 2 3 4 65

25 C

VGS, Gate-to-Source Voltage (V)

Figure 2. Transfer Characteristics

2.2
ID=2A

VGS=10V

1.9

1.6

1.3

1.0

RDS(ON), Normalized

0.7

RDS(ON), On-Resistance(Ohms)

0.4

-100 -50 0 50 100 150 200

TJ, Junction Temperature( C)

-55 C

Figure 3. Capacitance

1.3
VDS=V

GS

ID=250µA

1.2

1.1

1.0

0.9

0.8

VTH, Normalized

0.7

Gate-Source Threshold Voltage

0.6

-50 -25 0 25 50 75 100 125 150

TJ, Junction Temperature( C)

Figure 5. Gate Threshold Variation

with Temperature

Figure 4. On-Resistance Variation

with Temperature

V

=0

V

GS

1

10

0

10

IS, Source-drain current (A)

10-1

0.4 0.7 1.0 1.3

1.7

2.0

VSD, Body Diode Forward Voltage (V)

Figure 6. Body Diode Forward Voltage

Variation with Source Current

3

10

VDS=480V
ID=3A

8

6

4

2

VGS, Gate to Source Voltage (V)

0

0 2 4 6 108

Qg, Total Gate Charge (nC)

ID, Drain Current (A)

CEF05N6

2

10

1

R

10

0

10

-1

10

10

Limit

DS(ON)

TC=25 C
TJ=175 C

Single Pulse

0

1

10

VDS, Drain-Source Voltage (V)

DC

10ms

100ms

10

1ms

4

2

3

10

Figure 7. Gate Charge

IN

V

D

V

GS

GEN

R

G

S

Figure 9. Switching Test Circuit

0

10

D=0.5

0.2

0.1

-1

10

0.05

0.02

10

-2

-5

10

0.01

Single Pulse

-4

10

r(t),Normalized Effective

Transient Thermal Impedance

DD

V

R

L

OUT

V

-3

10

Square Wave Pulse Duration (sec)

Figure 8. Maximum Safe

on

t

r

t

90%

10% 10%

INVERTED

50% 50%

V

V

t

d(on)

OUT

IN

10%

PULSE WIDTH

Figure 10. Switching Waveforms

PDM

-2

10

-1

10

Operating Area

t

off

d(off)

t

90%

90%

t1

t2

1. RθJC (t)=r (t) * RθJC

2. RθJC=See Datasheet

3. TJM-TC = P* RθJC (t)

4. Duty Cycle, D=t1/t2

0

10

f

t

1

10

Figure 11. Normalized Thermal Transient Impedance Curve

4