Datasheet ced3423_ceu3423 Datasheet

CED3423/CEU3423

P-Channel Enhancement Mode Field Effect Transistor

FEATURES

-30V, -18A, R

R

Super high dense cell design for extremely low R

= 45mΩ @VGS = -10V.

DS(ON)

= 80mΩ @VGS = -4.5V.

DS(ON)

.

High power and current handing capability.

Lead free product is acquired.

TO-251 & TO-252 package.

D

G

S CEU SERIES TO-252(D-PAK)

ABSOLUTE MAXIMUM RATINGS T

Parameter

Drain-Source Voltage

Gate-Source Voltage

Drain Current-Continuous

Drain Current-Pulsed

Maximum Power Dissipation @ TC = 25 C

a

- Derate above 25 C

G

D

S

CED SERIES TO-251(I-PAK)

= 25 C unless otherwise noted

c

Symbol

V

DS

V

GS

I

D

I

DM

P

D

G

Limit

±20

0.25

Operating and Store Temperature Range TJ,Tstg -55 to 150

-30

-18

-72

31

D

S

Units

V

A

W

W/ C

C

Thermal Characteristics

Parameter Symbol Limit Units

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient

Details are subject to change without notice .

C/W

RθJA

4RθJC

50

Rev 3. 2010.Apr

http://www.cetsemi.com

1

CED3423/CEU3423

Electrical Characteristics T

= 25 C unless otherwise noted

A

Parameter Symbol Min Units

Off Characteristics

Drain-Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate Body Leakage Current, Forward

Gate Body Leakage Current, Reverse

On Characteristics

c

Gate Threshold Voltage

Static Drain-Source

On-Resistance

Forward Transconductance

Dynamic Characteristics

d

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Switching Characteristics

d

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

V

R

BV

C

t

d(on)

t

d(off)

Q

DSS

I

DSS

I

GSSF

IGSSR

GS(th)

DS(on)

g

FS

iss

oss

rss

t

r

t

f

Q

g

gs

gd

Drain-Source Diode Characteristics and Maximun Ratings

Drain-Source Diode Forward Current

Drain-Source Diode Forward Voltage

Notes :

a.Repetitive Rating : Pulse width limited by maximum junction temperature. b.Surface Mounted on FR4 Board, t < 10 sec. c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%. d.Guaranteed by design, not subject to production testing. 

b

c

I

S

V

SD

Test Condition

VGS = 0V, ID = -250µA

VDS = -24V, VGS = 0V

VGS = 20V, VDS = 0V

VGS = -20V, VDS = 0V

VGS = VDS, ID = -250µA

VGS = -10V, ID = -10A

VGS = -4.5V, ID = -5A

VDS = -15V, ID = -10A

VDS = -15V, VGS = 0V, f = 1.0 MHz

VDD = -15V, ID = -1A, VGS = -10V, R

GEN

= 6Ω

VDS = -15V, ID = -10A, VGS = -10V

VGS = 0V, IS = -10A

-30

-1

Typ Max

-1

100

-100

-3

4537

8062 mΩ

4.5

640

135

95

11

22

5

10

30

60

7

14

12.5

16

2

2.4

-10

-1.3

V

µA

nA

V

mΩ

S

pF

ns

nC

A

V

2

CED3423/CEU3423

50

40

30

20

-ID, Drain Current (A)

10

0

0 2 8 1064

900

750

600

450

3

0

C, Capacitance (pF)

1

5

0

-VGS=10,8,6V

-V

=3V

GS

-VDS, Drain-to-Source Voltage (V)

Figure 1. Output Characteristics

C

iss

C

o

s

C

rss

5

1

0

1

5

2

0

-VDS, Drain-to-Source Voltage (V)

25

20

15

10

-ID, Drain Current (A)

5

0

0 2 4 51 3

TJ=125 C

25 C

-55 C

5

-VGS, Gate-to-Source Voltage (V)

Figure 2. Transfer Characteristics

2.2 ID=-10A

VGS=-10V

1.9

1.6

1.3

1.0

RDS(ON), Normalized

0.7

RDS(ON), On-Resistance(Ohms)

0.4

2

5

-100 -50 0 50 100 150 200

TJ, Junction Temperature( C)

Figure 3. Capacitance

1.3 VDS=V

GS

ID=-250µA

1.2

1.1

1.0

0.9

0.8

VTH, Normalized

0.7

Gate-Source Threshold Voltage

0.6

-50 -25 0 25 50 75 100 125 150

TJ, Junction Temperature( C)

Figure 5. Gate Threshold Variation

with Temperature

Figure 4. On-Resistance Variation

with Temperature

V

=0

V

GS

1

10

0

10

-IS, Source-drain current (A)

-1

10

0.4 0.6 0.8 1.0

1.41.2

-VSD, Body Diode Forward Voltage (V)

Figure 6. Body Diode Forward Voltage

Variation with Source Current

3

10

8

6

VDS=-15V

ID=-10A

CED3423/CEU3423

2

10

R

Limit

DS(ON)

1

10

10ms

100ms

1s

DC

4

2

-VGS, Gate to Source Voltage (V)

0

0 4 8 12 16

Qg, Total Gate Charge (nC)

Figure 7. Gate Charge

DD

V

IN

V

R

D

V

GS

GEN

R

G

S

Figure 9. Switching Test Circuit

0

10

-ID, Drain Current (A)

-1

10

TC=25 C TJ=150 C

Single Pulse

-1

10

0

10

1

10

2

10

-VDS, Drain-Source Voltage (V)

Figure 8. Maximum Safe

Operating Area

on

t

d(off)

t

r

d(on)

L

OUT

V

t

OUT

V

IN

V

10%

t

90%

10% 10%

INVERTED

50% 50%

90%

t

off

f

t

90%

PULSE WIDTH

Figure 10. Switching Waveforms

0

10

D=0.5

0.2

-1

0.1

10

0.05

0.02

10

-2

10

0.01

Single Pulse

-1

10

0

10

1

10

r(t),Normalized Effective

Transient Thermal Impedance

PDM

t1

t2

1. RθJC (t)=r (t) * RθJC

2. RθJC=See Datasheet

3. TJM-TC = P* RθJC (t)

4. Duty Cycle, D=t1/t2

2

10

3

10

4

10

Square Wave Pulse Duration (sec)

Figure 11. Normalized Thermal Transient Impedance Curve

4