Datasheet CEC1712 Datasheet

CEC1712

Cryptographic Embedded Controller

Operating Conditions

• Operating Voltages: 3.3 V and 1.8 V

• Operating Temperature Range: -40

o

C to 85 oC

Low Power Modes

• Chip is designed to always operate in Lowest
Power state during Normal Operation

• Supports all 5 ACPI Power States for PC plat­forms

• Supports 2 Chip-level Sleep Modes: Light Sleep
and Heavy Sleep

- Low Standby Current in Sleep Modes

ARM® Cortex-M4 Embedded Processor

• Programmable clock frequency up to 48 MHz

• Fixed point processor

• Single 4GByte Addressing Space

• Nested Vectored Interrupt Controller (NVIC)

- Maskable Interrupt Controller

- Maskable hardware wake up events

- 8 Levels of priority, individually assignable by

vector

• EC Interrupt Aggregator expands number of Inter­rupt sources supported or reduces number of vec­tors needed

• Complete ARM

- JTAG-Based DAP port, comprised of SWJ-

DP and AHB-AP debugger access functions

®

Standard debug support

Memory Components

- 256 KB Code/Data SRAM

- 224 KB optimized for code performance

- 32 KB optimized for data performance

- 64 Bytes Battery Powered Storage SRAM

- 288 Bytes OTP

- In circuit programmable

-ROM

- Contains Boot ROM

- Contains Runtime APIs for built-in func­tions

Clocks

• 48 MHz Internal PLL

• 32 kHz Clock Sources

- Internal 32 kHz silicon oscillator

- External 32 kHz crystal (XTAL) source

- External single-ended 32 kHz clock
source

Package Options

- 84 pin WFBGA

Security Features

• Boot ROM Secure Boot Loader

- Hardware Root of trust using Secure Boot
and Immutable code using ECDSA P-384
and SHA-384

- Supports 2 Code Images in external SPI
Flash (Primary and Fall back image)

- Authenticates SPI Flash image before load­ing

- Support AES-256 Encrypted SPI Flash
images

- Key Revocation

- Roll back protection

- DICE support

• Hardware Accelerators:

- Multi purpose AES Crypto Engine:

- Support for 128-bit - 256-bit key length

- Supports Battery Authentication applica­tions

- Digital Signature Algorithm Support

- Support for ECDSA and EC_KCDSA

- Cryptographic Hash Engine

- Support for SHA-1, SHA-256 to SHA-512

- Public Key Crypto Engine

- Hardware support for RSA and Elliptic
Curve asymmetric public key algorithms

- RSA keys length of 1024 to 4096 bits

- ECC Prime Field keys up to 571 bits

- ECC Binary Field keys up to 571 bits

- Microcoded support for standard public
key algorithms

- OTP for storing Keys and IDs

- Lockable on 32 B boundaries to prevent
read access or write access

- True Random Number Generator

- 1 kbit FIFO

- JTAG Disabled by default

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CEC1712

Peripheral Features

• One Serial Peripheral Interface (SPI) Master Con­troller

- Dual and Quad I/O Support

- Flexible Clock Rates

- Support for 1.8V and 3.3V slave devices

- SPI Burst Capable

- SPI Controller Operates with Internal DMA

Controller with CRC Generation

- Mappable to 2 ports (only 1 port active at a

time)

- SPI interface can be disabled after loading

code

• Internal DMA Controller

- Hardware or Firmware Flow Control

- Firmware Initiated Memory-to-Memory trans-

fers

- Hardware CRC-32 Generator on Channel 0

- 12-Hardware DMA Channels support five

SMBus Master/Slave Controllers and One
SPI Controller

• I2C/SMBus Controllers

- 5 I2C/SMBus controllers

- 3 I2C only controllers without the Network

layer

- 10 Configurable I2C ports

- Full Crossbar switch allows any port to be
connected to any controller

- Supports Promiscuous mode of operation

- Fully Operational on Standby Power

- Multi-Master Capable

- Supports Clock Stretching

- Programmable Bus Speeds

- 1 MHz Capable

- Supports DMA Network Layer

• General Purpose I/O Pins

- Inputs

- Asynchronous rising and falling edge
wakeup detection Interrupt High or Low
Level

- Outputs:

- Push Pull or Open Drain output

- Programmable power well emulation

- Pull up or pull down resistor control

- Automatically disabling pull-up resistors
when output driven low

- Automatically disabling pull-down resis­tors when output driven high

- Programmable drive strength

- Two separate1.8V/3.3V configurable IO
regions

- Group or individual control of GPIO data

- 8 - Over voltage tolerant GPIO pins

- Glitch protection and Under-Voltage Protec­tion on all GPIO pins

• Input Capture and Compare timer

- Six 32-bit Capture Registers

- 11 Input Pins (ICTx)

- Full Crossbar switch allows any port to be
connected to any capture register

- 32-bit Free-running timer

- One 32-bit Compare Register output

- Capture, Compare and Overflow Interrupts

• Universal Asynchronous Receiver Transmitter
(UART)

- Three High Speed NS16C550A Compatible

UARTs with Send/Receive 16-Byte FIFOs

- UART1 - Configurable 2-pin/4-pin

- UART2 - 2-pin

- UART3 - 2-pin

- Programmable Main Power or Standby

Power Functionality

- Standard Baud Rates to 115.2 Kbps, Custom

Baud Rates to 1.5 Mbps

• Programmable Timer Interface

- Two16-bit Auto-reloading Timer Instances

- 16 bit Pre-Scale divider

- Halt and Reload control

- Auto Reload

- Two 32-bit Auto-reloading Timer Instances

- 16 bit Pre-Scale divider

- Halt and Reload control

- Auto Reload

- Three Operating Modes per Instance: Timer

(Reload or Free-Running) or One-shot.

- Event Mode is not supported

• 32-bit RTOS Timer

- Runs Off 32kHz Clock Source

- Continues Counting in all the Chip Sleep

States regardless of Processor Sleep State

- Counter is Halted when Embedded Controller

is Halted (e.g., JTAG debugger active, break
points)

- Generates wake-capable interrupt event

• Watch Dog Timer (WDT)

- Generates an interrupt prior to resetting

• 6 Programmable Pulse Width Modulator (PWM)
outputs

- Multiple Clock Rates

- 16-Bit ON & 16-Bit OFF Counters

• 2 Fan Tachometer Inputs

- 16 Bit Resolution

• Breathing LED Interface

- Two Blinking/Breathing LEDs

DS00003416B-page 2  2020 Microchip Technology Inc.

- Programmable Blink Rates

- Piecewise Linear Breathing LED Output Con­troller

- Provides for programmable rise and fall
waveforms

- Operational in EC Sleep States

- Both 5V tolerant LED pins

Analog Features

• ADC Interface

- 10-bit or 12-bit readings supported

- ADC Conversion time 500nS/channel

- 5 Channels

- External voltage reference

- Supports thermistor temperature readings

Battery Powered Peripherals

• Real Time Clock (RTC)

- VBAT Powered

- 32KHz Crystal Oscillator orExternal single­ended 32 kHz clock source

- Time-of-Day and Calendar Registers

- Programmable Alarms

- Supports Leap Year and Daylight Savings
Time

• Hibernation Timer Interface

- Two 32.768 KHz Driven Timers

- Programmable Wake-up from 0.5ms to 128
Minutes

• Week Timer

- System Power Present Input Pin

- Week Alarm Event only generated when
System Power is Available

- Power-up Event

- Week Alarm Interrupt with 1 Second to 8.5
Year Time-out

- Sub-Week Alarm Interrupt with 0.50 Seconds

- 72.67 hours time-out

- 1 Second and Sub-second Interrupts

• VBAT-Powered Control Interface (VCI)

- 2 Active-low VCI Inputs

- System Power Present Detection for gating
RTC wake events

- Optional filter

• Battery- powered General purpose Output
(BGPO)

Debug Features

• 2-pin Serial Wire Debug (SWD) interface

• 4-Pin JTAG interface for Boundary Scan

• Trace FIFO Debug Port (TFDP)

CEC1712

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CEC1712

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DS00003416B-page 4  2020 Microchip Technology Inc.

CEC1712

Table Of Contents

1.0 General Description ........................................................................................................................................................................ 6

2.0 Pin Configuration .......................................................................................................................................................................... 10

3.0 Device Inventory ........................................................................................................................................................................... 31

4.0 Power, Clocks, and Resets ........................................................................................................................................................... 65

5.0 ARM M4 Based Embedded Controller .......................................................................................................................................... 80

6.0 RAM and ROM ..............................................................................................................................................................................90

7.0 Internal DMA Controller ................................................................................................................................................................ 92

8.0 EC Interrupt Aggregator .............................................................................................................................................................. 108

9.0 Chip Configuration ...................................................................................................................................................................... 117

10.0 UART ........................................................................................................................................................................................ 122

11.0 GPIO Interface .......................................................................................................................................................................... 140

12.0 Watchdog Timer (WDT) ............................................................................................................................................................ 156

13.0 16/32 Bit Basic Timer ................................................................................................................................................................ 161

14.0 Input Capture and Compare Timer ........................................................................................................................................... 168

15.0 Hibernation Timer ..................................................................................................................................................................... 181

16.0 RTOS Timer .............................................................................................................................................................................. 184

17.0 Real Time Clock ........................................................................................................................................................................ 189

18.0 Week Timer ............................................................................................................................................................................... 201

19.0 TACH ........................................................................................................................................................................................ 211

20.0 PWM ......................................................................................................................................................................................... 218

21.0 Analog to Digital Converter ....................................................................................................................................................... 223

22.0 Blinking/Breathing LED ............................................................................................................................................................. 235

23.0 I2C/SMBus Interface ................................................................................................................................................................. 251

24.0 Quad SPI Master Controller ...................................................................................................................................................... 255

25.0 Trace FIFO Debug Port (TFDP) ................................................................................................................................................ 274

26.0 VBAT-Powered Control Interface .............................................................................................................................................. 278

27.0 VBAT-Powered RAM ................................................................................................................................................................ 289

28.0 VBAT Register Bank ................................................................................................................................................................. 291

29.0 EC Subsystem Registers ..................................................................................................

30.0 Security Features ...................................................................................................................................................................... 301

31.0 OTP Block ................................................................................................................................................................................. 305

32.0 Test Mechanisms ...................................................................................................................................................................... 308

33.0 Electrical Specifications ............................................................................................................................................................ 310

34.0 Timing Diagrams ....................................................................................................................................................................... 319

Appendix A: Data Sheet Revision History ......................................................................................................................................... 335

The Microchip Web Site .................................................................................................................................................................... 336

Customer Change Notification Service ............................................................................................................................................. 336

Customer Support ............................................................................................................................................................................. 336

Product Identification System ........................................................................................................................................................... 337

........................................................ 294

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CEC1712

1.0 GENERAL DESCRIPTION

The CEC1712 device is a low power integrated embedded controller designed with strong cryptographic support . The
CEC1712 is a highly-configurable, mixed-signal, advanced I/O controller architecture. It contains a 32-bit ARM® Cortex­M4 processor core with closely-coupled memory for optimal code execution and data access. An internal ROM, embed­ded in the design, is used to store the power on/boot sequence and APIs available during run time. When VTR_CORE
is applied to the device, the secure boot loader API is used to download the custom firmware image from the system’s
shared SPI Flash device, thereby allowing system designers to customize the device’s behavior.

The CEC1712 device is directly powered by a minimum of two separate suspend supply planes (VBAT and VTR). The
CEC1712 has two banks of I/O pins that are able to operate at either 3.3 V or 1.8 V. Operating at 1.8V allows the
CEC1712 to interface with the latest platform controller hubs and will lower the overall power consumed by the device,
Whereas 3.3V allows this device to be integrated into legacy platforms that require 3.3V operation.

The CEC1712 secure boot loader authenticates and optionally decrypts the SPI Flash OEM boot image using the AES­256, ECDSA P-384, SHA-384 cryptographic hardware accelerators. The CEC1712 hardware accelerators support 128­bit and 256-bit AES encryption, ECDSA and EC_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and Elliptic
asymmetric public key algorithms, and a True Random Number Generator (TRNG). Runtime APIs are provided in the
ROM for customer application code to use the cryptographic hardware. Additionally, the device offers lockable OTP stor­age for private keys and IDs. Additional features supported include Key Revocation, Roll back protection and DICE.

CEC1712 offers a software development system interface that includes a Trace FIFO debug port and a 2-pin Serail wire
debug (SWD)/ JTAG interface

1.1 Family Features

TABLE 1-1: CEC1712 FEATURE LIST

Features CEC1712 -84 WFBGA

Package 84 pin WFBGA

Device ID 0023_A2

Boundary Scan JTAG ID 0223_2445

CPU 32-bit ARM

SRAM 256 kB

Code/Data Options (Primary use) 224kB/32kB

Battery Backed SRAM 64 bytes

Trace FIFO Debug Port Yes

Internal DMA Channels 12

32-bit Timer 2

16-bit Timer 2

Capture Timer Registers 6

ICT Channels 11

Compare Timer Yes

Watchdog Timer (WDT) 1

Hibernation Timer 2

Week Timer 1

Sub Week Timer 1

RTC 1

RTOS Timer 1

Keyboard Matrix scan support No

SMBus 2.0 Host Controllers 5

®

Cortex-M4

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TABLE 1-1: CEC1712 FEATURE LIST (CONTINUED)

Features CEC1712 -84 WFBGA

Package 84 pin WFBGA

I2C Host Controllers 3

I2C/SMBus Ports 10

QMSPI Controller 1 Controller/2 ports

PWMs 6

Tachometers (TACHs) 2

GPIOs 68

Over voltage protected Pads 8

10/12- bit ADC Channels 5

UARTs 3

UART0: 2/4 pin configurable
UART1: 2 pin
UART2: 2 pin

Battery powered GPIO 1

VBAT powered Control Interface
inputs

2 Pin parallel XTAL Oscillator Yes

Single ended external 32kHz clock
input (XTAL2)

JTAG 4-pin/2-pin

AES Hardware Support 128-256 bit

SHA Hashing Support SHA-1 to SHA-512

Public Key Cryptography Support RSA: 4K bit

True Random Number Generator 1K bit

Root of Trust Yes

Secure Boot Yes

Immutable Code Yes

Customer OTP 288 bytes

Optional OTP Selectable Features (Note 1)

QA Testing Yes

JTAG Disable Yes

Authentication Yes

Encrypt ECDH Private Key (Bytes 0-

31)

AES Encryption Mandatory Yes

OTP Write Lock - [0] ECDH Private
Key

OTP Write Lock - [4] Authentication
Key - Public Qx

OTP Write Lock - [5] Authentication
Key - Public Qy

OTP Write Lock - [6] ECDH Public
Key 2, Public Rx

OTP Write Lock - [7] ECDH Public
Key 2, Public Ry

TAG0 SPI Flash Base Address Yes

2

Yes

ECC: 571 bit

Yes

Yes

Yes

Yes

Yes

Yes

CEC1712

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CEC1712

UART0

Battery

Pack

SMBus

Fansor

General

Use

PWMs

2‐pinUART

(x2)

UART

BreathingPWM

TraceFIFO

Deb ugPort

TFDP

SMBus/

I2CDevice

(s)

SMBus/I2C

GPIOs

VoltageMo ni tori ng

(e.g.,Thermistors,

PowerSupplies)

ADCs

PowerSupply

PowerButton(s)

BatteryPowered

GPIO

BGPO

2/4‐pin

Deb ug

JTAG

CEC1712Embedded

Controller

2/4‐pin

UART

QuadSPI(x2)

MainPowerSupply

VCC_PWRGD

LEDs(x2)

ICT

Sensors/

PWMinputs

TACH s

VCI_OUT

Note 1: Please refer to Boot ROM document for below set of optional OTP selectable feature.

1.2 Boot ROM

Following the release of the RESET_EC signal, the processor will start executing code in the Boot ROM. The B oot ROM
executes the SPI Flash Loader, which downloads User Code from SPI Flash and stores it in the internal Code RAM.
Refer to CEC1712 Boot ROM document for further details.

1.3 System Block Diagram

1.4 CEC1712 Internal Address Spaces

The Internal Embedded Controller can access any register in the EC Address Space or Host Address Space.

DS00003416B-page 8  2020 Microchip Technology Inc.

FIGURE 1-1: BLOCK DIAGRAM

Bus Swi tch

ARMM4F

JTAG/SWD

Memory

Controller

BootROM

SRAM

SRAM

DTCM

ITCM

MASTER MASTERSLAVE

Internal

DMA

Controller

HASH/AES

Engin e

PublicKey

Engin e

Crypto

RAM

SLAVE

Wa tc hdog

Timer

16‐bit B asi c

Timer

(x4)

32‐bit B asi c

Timer

(x2)

Capture/
Compare

Timer

SMB/I2C

Controller

(x5)

QuadSPI

Master

PWM

(x6)

Tach

(x2)

ADC

TraceFIFO

Hibernation

Timer

(x2)

WeekT imer

64Byte

VBATRAM

Blink/

BreatheLED

(x2)

Random

Number

Generator

VBAT

Control

Interface

RTOSTimer

Interrupt

Aggregator

SLAVE SLAVE

OTP

Power,
Clocks,

Resets

GPIOs

UART

(x3)

RealTime

Clock

MASTER

CEC1712

 2020 Microchip Technology Inc. DS00003416B-page 9

CEC1712

2.0 PIN CONFIGURATION

2.1 Description

The Pin Configuration chapter includes Pin List, Pin Multiplexing.

2.2 Terminology and Symbols for Pins/Buffers

2.2.1 BUFFER TERMINOLOGY

Term Definition

# The ‘#’ sign at the end of a signal name indicates an active-low signal

n The lowercase ‘n’ preceding a signal name indicates an active-low signal

PWR Power

Programmable as Input, Output, Open Drain Output, Bi-directional or Bi-directional with Open
Drain Output. Configurable drive strength from 2ma to12ma.

PIO

In I Type Input Buffer.

O2 O-2 mA Type Buffer.

PECI PECI Input/Output. These pins operate at the processor voltage level (VREF_VTT)

SB-TSI SB-TSI Input/Output. These pins operate at the processor voltage level (VREF_VTT)

Note: All GPIOs have programmable drive strength options of 2ma, 4ma, 8ma and 12ma.

GPIO pin drive strength is determined by the Pin Control Register Defaults field in
the Pin Control Register 2.

2.2.2 PIN NAMING CONVENTIONS

• Pin Name is composed of the multiplexed options separated by ‘/’. E.g., GPIOxxxx/SignalA/SignalB.

• The first signal shown in a pin name is the default signal. E.g., GPIOxxxx/SignalA/SignalB means the GPIO is the
default signal.

• Parenthesis ‘()’ are used to list aliases or alternate functionality for a single mux option.

• Square brackets ‘[ ]’ are used to indicate there is a Strap Option on a pin. This is always shown as the last signal
on the Pin Name.

• Signal Names appended with a numeric value indicates the Instance Number. E.g., PWM0, PWM1, etc. indicates
that PWM0 is the PWM output for PWM Instance 0, PWM1 is the PWM output for PWM Instance 1, etc. The
instance number may be omitted if there in only one instance of the IP block implemented.

2.3 Pin List

TABLE 2-1: CEC1712 PIN MAP

Ball map Signal

D2 nRESET_IN

F3 GPIO057/VCC_PWRGD

E2 GPIO106/PWROK

B2 GPIO051/ICT1_TACH1

A3 GPIO050/ICT0_TACH0

F2 GPIO200/ADC00/TRACEDAT0

G2 GPIO201/ADC01/TRACEDAT1

H2 GPIO202/ADC02/TRACEDAT2

G1 GPIO203/ADC03/TRACEDAT3

H1 GPIO204/ADC04

DS00003416B-page 10  2020 Microchip Technology Inc.

Ball map Signal

D1 VSS

J8 GPIO070/I2C14_SDA

K8 GPIO071/I2C14_SCL

J6 GPIO063/PWM6_ALT/ICT8

K3 GPIO224/SHD_IO1

K2 GPIO016/SHD_IO3/ICT3

K4 GPIO227/SHD_IO2

K5 GPIO223/SHD_IO0

K7 GPIO055/PWM2/SHD_CS0#

K6 GPIO056/PWM3/SHD_CLK

K1 GPIO012/I2C07_SDA

J2 GPIO013/I2C07_SCL

J5 GPIO130/I2C01_SDA

J9 GPIO131/I2C01_SCL

J3 GPIO020

J4 GPIO021

J7 GPIO002/PWM5/SHD_CS1#

H6 GPIO015/PWM7/ICT10

H5 GPIO032

A9 GPIO132/I2C06_SDA

B7 GPIO140/I2C06_SCL/ICT5

K9 GPIO026/I2C12_SDA

K10 GPIO053/PWM0

J10 GPIO027/I2C12_SCL

G7 GPIO030/I2C10_SDA

H9 GPIO107/I2C10_SCL

H10 GPIO120

G9 GPIO112

G10 GPIO113/ICT9

G4 GPIO034

F9 GPIO170/UART1_TX[JTAG_STRAP]

F8 GPIO171/UART1_RX

E8 JTAG_RST#

D9 GPIO104/UART0_TX/TFDP_CLK[VTR2_STRAP]

E9 GPIO105/UART0_RX/TFDP_DATA/TRACECLK

C9 GPIO046/ICT11

B8 GPIO047/PWM3_ALT/ICT13

D10 GPIO121/PVT_IO0

B10 GPIO122/PVT_IO1

E10 GPIO123/PVT_IO2

F10 GPIO126/PVT_IO3

C10 GPIO124/PVT_CS#/ICT12

A10 GPIO125/PVT_CLK

C6 GPIO127

CEC1712

 2020 Microchip Technology Inc. DS00003416B-page 11

CEC1712

Ball map Signal

D7 GPIO156/LED0

B9 GPIO157/LED1

C5 GPIO045/PWM2_ALT/ICT14

A6 GPIO165/32KHZ_IN/CTOUT0

C2 GPIO145/I2C09_SDA/JTAG_TDI/UART2_RX

B6 GPIO146/I2C09_SCL/JTAG_TDO/UART2_TX

A7 GPIO147/I2C15_SDA/JTAG_CLK

B3 GPIO150/I2C15_SCL/JTAG_TMS

E7 GPIO143/I2C04_SDA/UART0_CTS#

D6 GPIO144/I2C04_SCL/UART0_RTS#

A8 GPIO004/I2C00_SCL

B5 GPIO003/I2C00_SDA

A5 VCI_IN3#/GPIO000

B4 VCI_IN0#/GPIO163

B1 BGPO0/GPIO253

A1 VCI_OUT/GPIO250

A4 XTAL1

A2 XTAL2

D4 VSS_ANALOG

C1 VTR_PLL

D5 VBAT

E4 VSS

E1 VTR_REG

E3 VREF_ADC

F7 VSS

G6 VTR1

F4 VTR_ANALOG

F1 VR_CAP

G5 VTR2

J1 VSS_ADC

Note: GPIO055/PWM2/SHD_CS0# should be pulled up for proper boot up of the chip.

2.4 Pin Multiplexing

2.4.1 DEFAULT STATE

The default state for analog pins is Input. The default state for all pins that default to a GPIO function is input/output/inter­rupt disabled. The default state for pins that differ is shown in the Section 3.5, "GPIO Register Assignments". Entries for
the Default State column are

• O2ma-Low: Push-Pull output, Slow slew rate, 2ma drive strength, grounded

• O2ma-High Push-Pull output, Slow slew rate, 2ma drive strength, high output

• PU Input, with pull-up resistor enabled

2.4.2 POWER RAIL

The Power Rail column defines the power pin that provides I/O power for the signal pin.

DS00003416B-page 12  2020 Microchip Technology Inc.

CEC1712

2.4.3 BUFFER TYPES

The Buffer Type column defines the type of Buffer associated with each signal. Some pins have signals with two different
buffer types sharing the pin; in this case, table shows the buffer type for each of the signals that share the pin.

Input signals muxed with GPIOs are marked as “I”

Output signals muxed with GPIOs are marked as “PIO”, because the GPIO input path is always active even when the
alternate function selected is “output only”. So the GPIO input can be read to see the level of the output signal.

Pad Types are defined in the Section 33.0, "Electrical Specifications," on page 310.

• I/O Pad Types are defined in Section 33.2.4, "DC Electrical Characteristics for I/O Buffers," on page 312.

• The abbreviation “PWR” is used to denote power pins. The power supplies are defined in Section 33.2.1, "Power

Supply Operational Characteristics," on page 310.

2.4.4 GLITCH PROTECTION

Pins with glitch protection are glitch-free tristate pins and will not drive out while their associated power rail is rising.
These glitch-free tristate pins require either an external pull-up or pull-down to set the state of the pin high or low.

Note: If the pin needs to default low, a 1M ohm (max) external pull-down is required.

All pins are glitch protected.

Note: The power rail must rise monotonically in order for glitch protection to operate.

2.4.5 OVER-VOLTAGE PROTECTION

If a pin is over-voltage protected (over-voltage protection = YES) then the following is true: If the pad is powered by 1.8V
+/- 5% (operational) it can tolerate up to 3.63V on the pad. This allows for a pull-up to 3.3V power rail +/- 10%. If the
pad is powered by 3.3V +/- 5% (operational) it can tolerate up to 5.5V on the pad. This allows for a pull-up to 5.0V power
rail +/- 10%.

If a pin is not over-voltage protected (over-voltage protection = NO) then the following is true: If the pad is powered by

1.8V +/- 5% (operational), it can tolerate up to 1.8V +10% (i.e., +1.98V max). If the pad is powered by 3.3V +/- 5% (oper-

ational) it can tolerate up to 3.3V +10% (i.e., +3.63V max).

2.4.6 UNDER-VOLTAGE PROTECTION

Pins that are identified as having Under-voltage PROTECTION may be configured so they will not sink excess current
if powered by 3.3V and externally pulled up to 1.8V. The following configuration requirements must be met.

• If the pad is an output only pad type and it is configured as either open drain or the output is disabled.

• If the pin is a GPIO pin with a PIO pad type then is must be configured as open drain output with the input dis­abled. The input is disabled by setting the GPIO Power Gating Signals (PGS) bits to 11b.

All pins are under voltage protected.

2.4.7 BACKDRIVE PROTECTION

Assuming that the external voltage on the pin is within the parameters defined for the specific pad type, the backdrive
protected pin will not sink excess current when it is at a lower potential than the external circuit. There are two cases
where this occurs:

• The pad power is off and the external circuit is powered

• The pad power is on and the external circuitry is pulled to a higher potential than the pad power. This may occur
on 3.3V powered pads that are 5V tolerant or on 1.8V powered pads that are 3.6V tolerant.

2.4.8 EMULATED POWER WELL

Power well emulation for GPIOs and for signals that are multiplexed with GPIO signals is controlled by the Power Gating

Signals (PGS) option in the GPIO Pin Control Register. The Emulated Power Well column in the Pin Multiplexing table

defines the power gating programming options supported for each signal.

 2020 Microchip Technology Inc. DS00003416B-page 13

CEC1712

Note: VBAT powered signals do not support power emulation and must program the PGS bit field to 00b (VTR)

2.4.9 GATED STATE

This column defines the internal value of an input signal when either its emulated power well is inactive or it is not
selected by the GPIO alternate function MUX. A value of “No Gate” means that the internal signal always follows the
pin even when the emulated power well is inactive.

Note: Gated state is only meaningful to the operation of input signals. A gated state on an output pin defines the

internal behavior of the GPIO MUX and does not imply pin behavior.

Note: Only the pins that are 5V tolerant have an entry in the 5VT column in the Pin Description Table.

2.4.10 NOTES

The below notes are for all tables in this chapter.

TABLE 2-2: NUMBERED NOTES

NOTE Description

Note 1 An external cap must be connected as close to the VR_CAP pin/ball as possible with a routing resistance

and CAP ESR of less than 100mohms. The capacitor value is 1uF and must be ceramic with X5R or X7R
dielectric. The cap pin/ball should remain on the top layer of the PCB and traced to the CAP. Avoid adding
vias to other layers to minimize inductance.

Note 2 This SMBus ports supports 1 Mbps operation as defined by I2C. For 1 Mbps I2C recommended capaci-

tance/pull-up relationships from Intel, refer to the Shark Bay platform guide, Intel ref number 486714. Refer
to the PCH - SMBus 2.0/SMLink Interface Design Guidelines, Bus Capacitance/Pull-Up Resistor Relation­ship.

Note 4 The voltage on the ADC pins must not exceed 3.6 V or damage to the device will occur.

Note 5 The VCI pins may be used as GPIOs. The VCI input signals are not gated by selecting the GPIO alternate

function. Firmware must disable (i.e., gate) these inputs by writing the bits in the VCI Input Enable Register
when the GPIO function is enabled.

Note 6 The Over voltage protected GPIO pins will not support the Repeater mode mentioned in the GPIO pin con-

figuration register

Note 7 Refer Configurable Signal Routing section under Pin Configuration chapter for details on using the <signal>

and <signal>_ALT. Both <signal> and <signal>_ALT cannot be enabled simultaneously.

Note 8 <Signal> with ‘#’ as suffix will be shown as <Signal>_n in MPLab Tools

Note 9 32kHz_IN is named CLK32kHz_IN in MPLab Tools

Note 10 Clock Enable Register Bits [3:2] should be configured to be driven by single ended 32Khz source. Connect

the pin to SUSCLK from PCH.

Note 11 When the JTAG_RST# pin is not asserted (logic'1'), the JTAG or ARM SWJ signal functions in the JTAG

interface are unconditionally routed to the GPIO interface; the Pin Control register for these GPIO pins has
no effect.When the JTAG_RST# pin is asserted (logic'0'), the signal functions in the JTAG interface are not
routed to the interface and the Pin Control Register for these GPIO pins controls the muxing. The pin con­trol registers can not route the JTAG interface to the pins. System Board Designer should terminate this pin
in all functional state using jumpers and pull-up or pull down resistors, etc.

Note 12 The JTAG signals TDI,TDO,TMS,TCK are muxed with GPIO pins. Routing of JTAG signals to these pins

are dependent on DEBUG ENABLE REGISTER bits [2:0] and JTAG_RST# pin (Note . To configure these
GPIO pins for non JTAG functions, pull JTAG_RST# low externally and select the appropriate alternate
function in the Pin Control Register

Note 13 The BGPO pins may be used as GPIO. For this the BGPO power control register and GPIO pin control reg-

ister needs to be configured

Note 14 GPIO000/VCI_IN3#, if not used must be connected to VBAT through a high impedance resistor of the order

of 100k

DS00003416B-page 14  2020 Microchip Technology Inc.

TABLE 2-2: NUMBERED NOTES

NOTE Description

Note 15 External pull up should be added on GPIO055/SHD_CS0# pin for proper booting

2.4.11 CEC1712 MULTIPLEXING

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

Gated

State

CEC1712

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0nRESET_IN I VTR1 PGS=00

(only)

1 Reserved

2 Reserved

3 Reserved

Default: 0GPIO057 PIO VTR1 All PGS

options

1 VCC_PWRGD PIO PGS=00

(only)

2 Reserved

3 Reserved

Default: 0GPIO106 PIO VTR1 All PGS

options

1 PWROK PIO PGS=00

(only)

2 Reserved

3 Reserved

Default: 0GPIO051 PIO VTR1 All PGS

options

1 ICT1_TACH1 PIO All PGS

options

2 Reserved

3 Reserved

Yes

No Gate Yes Yes

High

No Gate Yes

NA

No Gate Yes

Low

Default: 0GPIO050 PIO VTR1 All PGS

options

1 ICT0_TACH0 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO200 PIO VTR1 All PGS

options

 2020 Microchip Technology Inc. DS00003416B-page 15

No Gate Yes

Low

No Gate No

CEC1712

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

1 ADC00 I_AN PGS=00

2 Reserved

3 Reserved

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

(only)

Gated

State

Low Note 4

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO201 PIO VTR1 All PGS

options

1 ADC01 I_AN PGS=00

(only)

2 Reserved

3 Reserved

Default: 0GPIO202 PIO VTR1 All PGS

options

1 ADC02 I_AN PGS=00

(only)

2 Reserved

3 Reserved

Default: 0GPIO203 PIO VTR1 All PGS

options

1 ADC03 I_AN PGS=00

(only)

2 Reserved

3 Reserved

Default: 0GPIO204 PIO VTR1 All PGS

options

1 ADC04 I_AN PGS=00

(only)

2 Reserved

3 Reserved

No Gate No

Low Note 4

No Gate No

Low Note 4

No Gate No

Low Note 4

No Gate No

Low Note 4

Default: 0GPIO070 PIO VTR2 All PGS

options

1 Reserved

2 I2C14_SDA PIO All PGS

options

3 Reserved

Default: 0GPIO071 PIO VTR2 All PGS

options

1 Reserved

2 I2C14_SCL PIO All PGS

options

3 Reserved

DS00003416B-page 16  2020 Microchip Technology Inc.

No Gate Yes

High

No Gate Yes

High

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

Gated

State

CEC1712

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO063 PIO VTR2 All PGS

options

1 Reserved

2 PWM6_ALT PIO All PGS

options

3 ICT8 I All PGS

options

Default: 0GPIO224 PIO VTR2 All PGS

options

1 Reserved

2 SHD_IO1 PIO All PGS

options

3 Reserved

Default: 0GPIO016 PIO VTR2 All PGS

options

1 Reserved

2 SHD_IO3 PIO All PGS

options

3 ICT3 PIO All PGS

options

No Gate Yes

NA Note 7

Low

No Gate Yes

Low

No Gate Yes

Low

Low

Default: 0GPIO227 PIO VTR2 All PGS

options

1 SHD_IO2 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO223 PIO VTR2 All PGS

options

1 SHD_IO0 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO055 PIO VTR2 All PGS

options

1 PWM2 PIO All PGS

options

2 SHD_CS0# PIO All PGS

options

3 Reserved

No Gate Yes

Low

No Gate Yes

Low

No Gate Yes

NA

NA Note

15

 2020 Microchip Technology Inc. DS00003416B-page 17

CEC1712

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

Default: 0GPIO056 PIO VTR2 All PGS

1 PWM3 PIO All PGS

2 SHD_CLK PIO All PGS

3 Reserved

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

options

options

options

Gated

State

No Gate Yes

NA

NA

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO012 PIO VTR2 All PGS

options

1 I2C07_SDA PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO013 PIO VTR2 All PGS

options

1 I2C07_SCL PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO130 PIO VTR2 All PGS

options

1 I2C01_SDA PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO131 PIO VTR2 All PGS

options

1 I2C01_SCL PIO All PGS

options

2 Reserved

3 Reserved

No Gate Yes Yes

High Note 2

No Gate Yes Yes

High Note 2

No Gate Yes Yes

High Note 2

No Gate Yes Yes

High Note 2

Default: 0GPIO020 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 Reserved

Default: 0GPIO021 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

DS00003416B-page 18  2020 Microchip Technology Inc.

No Gate Yes

No Gate Yes

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

3 Reserved

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

Gated

State

CEC1712

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO002 PIO VTR2 All PGS

options

1 PWM5 PIO All PGS

options

2 SHD_CS1# PIO All PGS

options

3 Reserved

Default: 0GPIO015 PIO VTR2 All PGS

options

1 PWM7 PIO All PGS

options

2 ICT10 I All PGS

options

3 Reserved

Default: 0GPIO032 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 Reserved

Default: 0GPIO132 PIO VTR1 All PGS

options

1 I2C06_SDA PIO All PGS

options

2 Reserved

3 Reserved

No Gate Yes

NA

High

No Gate Yes

NA

Low

No Gate Yes

No Gate Yes

High

Default: 0GPIO140 PIO VTR1 All PGS

options

1 I2C06_SCL PIO All PGS

options

2 ICT5 PIO All PGS

options

3 Reserved

Default: 0GPIO026 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 I2C12_SDA PIO All PGS

options

 2020 Microchip Technology Inc. DS00003416B-page 19

No Gate Yes

High

Low

No Gate Yes

High

CEC1712

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

Default: 0GPIO053 PIO VTR2 All PGS

1 PWM0 PIO All PGS

2 Reserved

3 Reserved

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

options

options

Gated

State

No Gate Yes

NA

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO027 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 I2C12_SCL PIO All PGS

options

Default: 0GPIO030 PIO VTR1 All PGS

options

1 Reserved

2 I2C10_SDA PIO All PGS

options

3 Reserved

Default: 0GPIO107 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 I2C10_SCL PIO All PGS

options

Default: 0GPIO120 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 Reserved

No Gate Yes

High

No Gate Yes

High

No Gate Yes

High

No Gate Yes

Default: 0GPIO112 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 Reserved

Default: 0GPIO113 PIO VTR1 All PGS

options

1 Reserved

2 ICT9 I All PGS

options

DS00003416B-page 20  2020 Microchip Technology Inc.

No Gate Yes

No Gate Yes

Low

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

3 Reserved

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

Gated

State

CEC1712

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO034 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 Reserved

Default: 0GPIO170 PIO PU VTR1 All PGS

options

1 UART1_TX PIO All PGS

options

2 Reserved

3 Reserved

Strap JTAG_STRAP PIO

Default: 0GPIO171 PIO VTR1 All PGS

options

1 UART1_RX PIO All PGS

options

2 Reserved

3 Reserved

Default: 0JTAG_RST# I VTR1 N/A Yes Note

1 Reserved

2 Reserved

3 Reserved

No Gate Yes

No Gate Yes

NA

No Gate Yes

Low

11, 12

Default: 0GPIO104 PIO VTR1 All PGS

options

1 UART0_TX PIO All PGS

options

2 TFDP_CLK PIO All PGS

options

3 Reserved

Strap VTR2_STRAP PIO

Default: 0GPIO105 PIO VTR1 All PGS

options

1 UART0_RX PIO All PGS

options

2 TFDP_DATA PIO All PGS

options

3 Reserved

Default: 0GPIO046 PIO VTR1 All PGS

options

 2020 Microchip Technology Inc. DS00003416B-page 21

No Gate Yes

NA

NA

No Gate Yes

Low

NA

No Gate Yes

CEC1712

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

1 KSO2 PIO All PGS

2 Reserved

3 ICT11 I All PGS

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

options

options

Gated

State

NA

Low

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO047 PIO VTR1 All PGS

options

1 Reserved

2 PWM3_ALT PIO All PGS

options

3 ICT13 I All PGS

options

Default: 0GPIO121 PIO VTR1 All PGS

options

1 PVT_IO0 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO122 PIO VTR1 All PGS

options

1 PVT_IO1 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO123 PIO VTR1 All PGS

options

1 PVT_IO2 PIO All PGS

options

2 Reserved

3 Reserved

No Gate Yes

NA Note 7

Low

No Gate Yes

Low

No Gate Yes

Low

No Gate Yes Yes

Low

Default: 0GPIO126 PIO VTR1 All PGS

options

1 PVT_IO3 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO124 PIO VTR1 All PGS

options

1 PVT_CS# PIO All PGS

options

DS00003416B-page 22  2020 Microchip Technology Inc.

No Gate Yes

Low

No Gate Yes

NA

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

2 Reserved

3 ICT12 I All PGS

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

options

Gated

State

Low

CEC1712

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO125 PIO VTR1 All PGS

options

1 PVT_CLK PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO127 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 Reserved

Default: 0GPIO156 PIO VTR1 All PGS

options

1 LED0 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO157 PIO VTR1 All PGS

options

1 LED1 PIO All PGS

options

2 Reserved

3 Reserved

No Gate Yes

NA

No Gate Yes

No Gate Yes Yes

NA

No Gate Yes Yes

NA

Default: 0GPIO045 PIO VTR1 All PGS

options

1 Reserved

2 PWM2_ALT PIO All PGS

options

3 ICT14 I All PGS

options

Default: 0GPIO165 PIO VTR1 All PGS

options

1 32KHZ_IN PIO PGS=00

(only)

2 Reserved

3 CTOUT0 PIO All PGS

options

 2020 Microchip Technology Inc. DS00003416B-page 23

No Gate Yes

NA

Low

No Gate Yes

Low

NA

CEC1712

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

Gated

State

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO145 PIO VTR1 All PGS

options

1 I2C09_SDA PIO All PGS

options

2 UART2_RX I All PGS

options

3 Reserved

Default: 0GPIO146 PIO VTR1 All PGS

options

1 I2C09_SCL PIO All PGS

options

2 UART2_TX PIO All PGS

options

3 Reserved

Default: 0GPIO147 PIO VTR1 All PGS

options

1 I2C15_SDA PIO All PGS

options

2 Reserved

3 Reserved

No Gate Yes

High

Low

No Gate Yes

High

NA

No Gate Yes

High

Default: 0GPIO150 PIO VTR1 All PGS

options

1 I2C15_SCL PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO143 PIO VTR1 All PGS

options

1 I2C04_SDA PIO All PGS

options

2 UART0_CTS# I All PGS

options

3 Reserved

Default: 0GPIO144 PIO VTR1 All PGS

options

1 I2C04_SCL PIO All PGS

options

2 UART0_RTS# PIO All PGS

options

3 Reserved

No Gate Yes

High

No Gate Yes

High

High

No Gate Yes

High

NA

DS00003416B-page 24  2020 Microchip Technology Inc.

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

Gated

State

CEC1712

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO004 PIO VTR1 All PGS

options

1 I2C00_SCL PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO003 PIO VTR1 All PGS

options

1 I2C00_SDA PIO All PGS

options

2 Reserved

3 Reserved

0 GPIO000 PIO VBAT All PGS

options

Default: 1VCI_IN3# ILLK PGS=00

(only)

2 Reserved

3 Reserved

0 GPIO163 PIO VBAT All PGS

options

Default: 1VCI_IN0# ILLK PGS=00

(only)

2 Reserved

3 Reserved

No Gate Yes

High

No Gate Yes

High

No Gate Yes

No Gate Note

14

No Gate Yes

No Gate Note 5

0 GPIO253 PIO VBAT All PGS

options

Default: 1BGPO0 PIO O2ma-

Low

2 Reserved

3 Reserved

0 GPIO250 PIO VBAT All PGS

Default: 1VCI_OUT PIO O2ma-

High

2 Reserved

3 Reserved

 2020 Microchip Technology Inc. DS00003416B-page 25

PGS=00
(only)

options

PGS=00
(only)

No Gate Yes

NA Note

13

No Gate Yes

NA

CEC1712

2.5 Configurable Signal Routing

To accommodate the signal routing across packages, some Signals are routed to more than one GPIO. At any given
time, only the <Signal> or <Signal>_ALT can be selected. Both cannot be selected at the same time.

2.5.1 SIGNAL DESCRIPTION BY INTERFACE

TABLE 2-4: SIGNAL DESCRIPTION BY INTERFACE

SIG_NAME Description Notes

ADC

ADCxx ADC channel input Note 5

‘xx’ is the index of the ADC input. Refer Family
features table to find the number of ADC
inputs supported in the package

Miscellaneous

I2C/SMBus Controller

I2Cxx_SDA I2C/SMBus Controller Port 0 Data Note 2

‘xx’ is the index of the I2C port. Refer Family
features table to find the number of I2C ports
supported in the package

I2Cxx_SCL I2C/SMBus Controller Port 0 Clock Note 2

GPIO

GPIOx General Purpose Input Output Pins

PCR Interface

32KHZ_OUT 32.768 KHz Digital Output

32KHZ_IN 32.768 KHz Digital Input

nRESET_IN External System Reset Input

PECI

PECI_DAT PECI Bus

VREF_VTT Processor Interface Voltage Reference

Quad Mode SPI Controller ports

PVT_CS# Private SPI Chip Select SPI_CS0# of QMSPI Controller

PVT_IO0 Private SPI Data 0 SPI_IO0 of QMSPI Controller

PVT_IO1 Private SPI Data 1 SPI_IO1 of QMSPI Controller

PVT_IO2 Private SPI Data 2 SPI_IO2 of QMSPI Controller

PVT_IO3 Private SPI Data 3 SPI_IO3 of QMSPI Controller

PVT_CLK Private SPI Clock SPI_CLK of QMSPI Controller

SHD_CS1# Shared SPI Chip Select1 SPI_CS1# of QMSPI Controlelr

SHD_CS0# Shared SPI Chip Select SPI_CS0# of QMSPI Controller

SHD_IO0 Shared SPI Data 0 SPI_IO0 of QMSPI Controller

SHD_IO1 Shared SPI Data 1 SPI_IO1 of QMSPI Controller

SHD_IO2 Shared SPI Data 2 SPI_IO2 of QMSPI Controller

SHD_IO3 Shared SPI Data 3 SPI_IO3 of QMSPI Controller

SHD_CLK Shared SPI Clock SPI_CLK of QMSPI Controller

DS00003416B-page 26  2020 Microchip Technology Inc.

CEC1712

TABLE 2-4: SIGNAL DESCRIPTION BY INTERFACE (CONTINUED)

SIG_NAME Description Notes

FAN PWM and Tachometer

ICT0_TACH0 Fan Tachometer Input 0

ICT1_TACH1 Fan Tachometer Input 1

ICT2_TACH2 Fan Tachometer Input 2

TACH3 Fan Tachometer Input 3

PWMx Pulse Width Modulator Output ‘x’ is the index of the PWM output. Refer Fam-

ily features table to find the number of PWM
outputs supported in the package

Input Capture/Compare timer

ICTx Input capture timer input ‘x’ is the index of the PWM output. Refer Fam-

ily features table to find the number of ICT
inputs supported in the package

CTOUT0 Compare timer 0 toggle output

CTOUT1 Compare timer 1 toggle output

Serial ports

UART_CLK UART Baud Clock Input

UART0_RX UART Receive Data (RXD)

UART0_TX UART Transmit Data (TXD)

UART0_CTS# Clear to Send Input

UART0_RTS# Request to Send Output

UART0_RI# Ring Indicator Input

UART0_DCD# Data Carrier Detect Input

UART0_DSR# Data Set Ready Input

UART0_DTR# Data Terminal Ready Output

JTAG

JTAG_RST# JTAG test active low reset Note 11,12

JTAG_TDI JTAG test data in Note 11,12

JTAG_TDO JTAG test data out Note 11,12

JTAG_CLK JTAG test clk; SWDCLK Note 11,12

JTAG_TMS JTAG test mode select; SWDIO Note 11,12

TFDP_DATA Trace FIFO debug port - data

TFDP_CLK Trace FIFO debug port - clock

TRACECLK ARM Embedded Trace Macro Clock Trace Port is enabled by setting TRACE_EN

bit of ETM Trace enable register in EC Regis­ter Bank

TRACEDATA0 ARM Embedded Trace Macro Data 0

TRACEDATA1 ARM Embedded Trace Macro Data 1

TRACEDATA2 ARM Embedded Trace Macro Data 2

TRACEDATA3 ARM Embedded Trace Macro Data 3

Power pins

VREF_ADC ADC Reference Voltage

VSS_ADC Analog ADC supply associated ground

VBAT VBAT supply

VR_CAP Internal Voltage Regulator Capacitor Note 1

 2020 Microchip Technology Inc. DS00003416B-page 27

CEC1712

TABLE 2-4: SIGNAL DESCRIPTION BY INTERFACE (CONTINUED)

SIG_NAME Description Notes

VSS VTR associated ground

VSS_VBAT VBAT associated ground

VTR1 VTR Suspend Power Supply

VTR2 Peripheral Power Supply

VTR_PLL PLL power supply

VTR_REG Main Regulator Power supply

2.5.2 STRAPPING OPTIONS

GPIO170 is used for the TAP Controller select strap. If any of the JTAG TAP controllers are used, GPIO170 must only
be configured as an output to a VTRx powered external function. GPIO170 may only be configured as an input when
the JTAG TAP controllers are not needed or when an external driver does not violate the Slave Select Timing.See Sec-

tion 32.2.1, "TAP Controller Select Strap Option".

TABLE 2-5: STRAP PINS

Pin Name Strap Name Strap Define and Value

GPIO170 JTAG_STRAP 1= Boundary Scan

The JTAG Port is used to access the Boundary scan TAP
controller
0= Normal Operation
The JTAG port is used to access the ARM TAP Controller

I/O Power

Rail

VTR1

GPIO104 VTR2_STRAP Voltage Level strap is used to determine if the Shared

Flash interface must be configured for 3.3V or 1.8V
operation
1= 3.3V Operation
0= 1.8V Operation

VTR1

2.6 Pin Default State Through Power Transitions

The power state and power state transitions illustrated in the following tables are defined in Section 4.0, "Power,

Clocks, and Resets". Pin behavior in this table assumes no specific programming to change the pin state. All GPIO

default pins that have the same behavior are described in the table generically as GPIOXXX.

TABLE 2-6: PIN DEFAULT STATE THROUGH POWER TRANSITIONS

RESET_

Signal

GPIO170

GPIOXXX

nRESET_IN

BGPOx Out=0 Out=0 Retain Retain Retain Retain

VCI_INx# In In In In In In

VBAT

Applied

un-

powered

un-

powered

un-

powered

VBAT

Stable

un-

powered

un-

powered

un-

powered

VTR

Applied

High In Z glitch

Z Z Z glitch

Low In Z glitch

SYS

De-

asserted

RESET_

SYS

Asserted

VTR

Un-

powered

VBAT

Un-

powered

un-

powered

un-

powered

un-

powered

un-

powered

un-

powered

Note

Note

D

Note

B

DS00003416B-page 28  2020 Microchip Technology Inc.

TABLE 2-6: PIN DEFAULT STATE THROUGH POWER TRANSITIONS

Signal

VCI_OUT

XTAL1

XTAL2

RESET_

VBAT

Applied

Out

logic

CrystalInCrystalInCrystalInCrystalInCrystalInCrystalInCrystal

Crystal

Out

VBAT

Stable

Out

logic

Crystal

Out

VTR

Applied

Out

logic

Crystal

Out

SYS

De-

asserted

Out

logic

Crystal

Out

RESET_

SYS

Asserted

Out

logic

Crystal

Out

VTR

Un-

powered

Out

logic

Crystal

Out

VBAT

powered

powered

Crystal

Un-

un-

In

Out

CEC1712

Note

Note

C

Legend
(P) = I/O state is driven by proto­col while power is applied.

Z = Tristate
In = Input

Notes

Note D: Does not include GPIO170

Note B: Pin is programmable by the EC and retains its value through a

VTR power cycle.

 2020 Microchip Technology Inc. DS00003416B-page 29

CEC1712

2.7 Package Information

2.7.1 84 PIN WFBGA/SX1 PACKAGE

Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.micro-

chip.com/packaging.

DS00003416B-page 30  2020 Microchip Technology Inc.