Datasheet CEC1712 Datasheet

CEC1712

Cryptographic Embedded Controller

Operating Conditions

• Operating Voltages: 3.3 V and 1.8 V

• Operating Temperature Range: -40

o

C to 85 oC

Low Power Modes

• Chip is designed to always operate in Lowest
Power state during Normal Operation

• Supports all 5 ACPI Power States for PC plat­forms

• Supports 2 Chip-level Sleep Modes: Light Sleep
and Heavy Sleep

- Low Standby Current in Sleep Modes

ARM® Cortex-M4 Embedded Processor

• Programmable clock frequency up to 48 MHz

• Fixed point processor

• Single 4GByte Addressing Space

• Nested Vectored Interrupt Controller (NVIC)

- Maskable Interrupt Controller

- Maskable hardware wake up events

- 8 Levels of priority, individually assignable by

vector

• EC Interrupt Aggregator expands number of Inter­rupt sources supported or reduces number of vec­tors needed

• Complete ARM

- JTAG-Based DAP port, comprised of SWJ-

DP and AHB-AP debugger access functions

®

Standard debug support

Memory Components

- 256 KB Code/Data SRAM

- 224 KB optimized for code performance

- 32 KB optimized for data performance

- 64 Bytes Battery Powered Storage SRAM

- 288 Bytes OTP

- In circuit programmable

-ROM

- Contains Boot ROM

- Contains Runtime APIs for built-in func­tions

Clocks

• 48 MHz Internal PLL

• 32 kHz Clock Sources

- Internal 32 kHz silicon oscillator

- External 32 kHz crystal (XTAL) source

- External single-ended 32 kHz clock
source

Package Options

- 84 pin WFBGA

Security Features

• Boot ROM Secure Boot Loader

- Hardware Root of trust using Secure Boot
and Immutable code using ECDSA P-384
and SHA-384

- Supports 2 Code Images in external SPI
Flash (Primary and Fall back image)

- Authenticates SPI Flash image before load­ing

- Support AES-256 Encrypted SPI Flash
images

- Key Revocation

- Roll back protection

- DICE support

• Hardware Accelerators:

- Multi purpose AES Crypto Engine:

- Support for 128-bit - 256-bit key length

- Supports Battery Authentication applica­tions

- Digital Signature Algorithm Support

- Support for ECDSA and EC_KCDSA

- Cryptographic Hash Engine

- Support for SHA-1, SHA-256 to SHA-512

- Public Key Crypto Engine

- Hardware support for RSA and Elliptic
Curve asymmetric public key algorithms

- RSA keys length of 1024 to 4096 bits

- ECC Prime Field keys up to 571 bits

- ECC Binary Field keys up to 571 bits

- Microcoded support for standard public
key algorithms

- OTP for storing Keys and IDs

- Lockable on 32 B boundaries to prevent
read access or write access

- True Random Number Generator

- 1 kbit FIFO

- JTAG Disabled by default

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CEC1712

Peripheral Features

• One Serial Peripheral Interface (SPI) Master Con­troller

- Dual and Quad I/O Support

- Flexible Clock Rates

- Support for 1.8V and 3.3V slave devices

- SPI Burst Capable

- SPI Controller Operates with Internal DMA

Controller with CRC Generation

- Mappable to 2 ports (only 1 port active at a

time)

- SPI interface can be disabled after loading

code

• Internal DMA Controller

- Hardware or Firmware Flow Control

- Firmware Initiated Memory-to-Memory trans-

fers

- Hardware CRC-32 Generator on Channel 0

- 12-Hardware DMA Channels support five

SMBus Master/Slave Controllers and One
SPI Controller

• I2C/SMBus Controllers

- 5 I2C/SMBus controllers

- 3 I2C only controllers without the Network

layer

- 10 Configurable I2C ports

- Full Crossbar switch allows any port to be
connected to any controller

- Supports Promiscuous mode of operation

- Fully Operational on Standby Power

- Multi-Master Capable

- Supports Clock Stretching

- Programmable Bus Speeds

- 1 MHz Capable

- Supports DMA Network Layer

• General Purpose I/O Pins

- Inputs

- Asynchronous rising and falling edge
wakeup detection Interrupt High or Low
Level

- Outputs:

- Push Pull or Open Drain output

- Programmable power well emulation

- Pull up or pull down resistor control

- Automatically disabling pull-up resistors
when output driven low

- Automatically disabling pull-down resis­tors when output driven high

- Programmable drive strength

- Two separate1.8V/3.3V configurable IO
regions

- Group or individual control of GPIO data

- 8 - Over voltage tolerant GPIO pins

- Glitch protection and Under-Voltage Protec­tion on all GPIO pins

• Input Capture and Compare timer

- Six 32-bit Capture Registers

- 11 Input Pins (ICTx)

- Full Crossbar switch allows any port to be
connected to any capture register

- 32-bit Free-running timer

- One 32-bit Compare Register output

- Capture, Compare and Overflow Interrupts

• Universal Asynchronous Receiver Transmitter
(UART)

- Three High Speed NS16C550A Compatible

UARTs with Send/Receive 16-Byte FIFOs

- UART1 - Configurable 2-pin/4-pin

- UART2 - 2-pin

- UART3 - 2-pin

- Programmable Main Power or Standby

Power Functionality

- Standard Baud Rates to 115.2 Kbps, Custom

Baud Rates to 1.5 Mbps

• Programmable Timer Interface

- Two16-bit Auto-reloading Timer Instances

- 16 bit Pre-Scale divider

- Halt and Reload control

- Auto Reload

- Two 32-bit Auto-reloading Timer Instances

- 16 bit Pre-Scale divider

- Halt and Reload control

- Auto Reload

- Three Operating Modes per Instance: Timer

(Reload or Free-Running) or One-shot.

- Event Mode is not supported

• 32-bit RTOS Timer

- Runs Off 32kHz Clock Source

- Continues Counting in all the Chip Sleep

States regardless of Processor Sleep State

- Counter is Halted when Embedded Controller

is Halted (e.g., JTAG debugger active, break
points)

- Generates wake-capable interrupt event

• Watch Dog Timer (WDT)

- Generates an interrupt prior to resetting

• 6 Programmable Pulse Width Modulator (PWM)
outputs

- Multiple Clock Rates

- 16-Bit ON & 16-Bit OFF Counters

• 2 Fan Tachometer Inputs

- 16 Bit Resolution

• Breathing LED Interface

- Two Blinking/Breathing LEDs

DS00003416B-page 2  2020 Microchip Technology Inc.

- Programmable Blink Rates

- Piecewise Linear Breathing LED Output Con­troller

- Provides for programmable rise and fall
waveforms

- Operational in EC Sleep States

- Both 5V tolerant LED pins

Analog Features

• ADC Interface

- 10-bit or 12-bit readings supported

- ADC Conversion time 500nS/channel

- 5 Channels

- External voltage reference

- Supports thermistor temperature readings

Battery Powered Peripherals

• Real Time Clock (RTC)

- VBAT Powered

- 32KHz Crystal Oscillator orExternal single­ended 32 kHz clock source

- Time-of-Day and Calendar Registers

- Programmable Alarms

- Supports Leap Year and Daylight Savings
Time

• Hibernation Timer Interface

- Two 32.768 KHz Driven Timers

- Programmable Wake-up from 0.5ms to 128
Minutes

• Week Timer

- System Power Present Input Pin

- Week Alarm Event only generated when
System Power is Available

- Power-up Event

- Week Alarm Interrupt with 1 Second to 8.5
Year Time-out

- Sub-Week Alarm Interrupt with 0.50 Seconds

- 72.67 hours time-out

- 1 Second and Sub-second Interrupts

• VBAT-Powered Control Interface (VCI)

- 2 Active-low VCI Inputs

- System Power Present Detection for gating
RTC wake events

- Optional filter

• Battery- powered General purpose Output
(BGPO)

Debug Features

• 2-pin Serial Wire Debug (SWD) interface

• 4-Pin JTAG interface for Boundary Scan

• Trace FIFO Debug Port (TFDP)

CEC1712

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CEC1712

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DS00003416B-page 4  2020 Microchip Technology Inc.

CEC1712

Table Of Contents

1.0 General Description ........................................................................................................................................................................ 6

2.0 Pin Configuration .......................................................................................................................................................................... 10

3.0 Device Inventory ........................................................................................................................................................................... 31

4.0 Power, Clocks, and Resets ........................................................................................................................................................... 65

5.0 ARM M4 Based Embedded Controller .......................................................................................................................................... 80

6.0 RAM and ROM ..............................................................................................................................................................................90

7.0 Internal DMA Controller ................................................................................................................................................................ 92

8.0 EC Interrupt Aggregator .............................................................................................................................................................. 108

9.0 Chip Configuration ...................................................................................................................................................................... 117

10.0 UART ........................................................................................................................................................................................ 122

11.0 GPIO Interface .......................................................................................................................................................................... 140

12.0 Watchdog Timer (WDT) ............................................................................................................................................................ 156

13.0 16/32 Bit Basic Timer ................................................................................................................................................................ 161

14.0 Input Capture and Compare Timer ........................................................................................................................................... 168

15.0 Hibernation Timer ..................................................................................................................................................................... 181

16.0 RTOS Timer .............................................................................................................................................................................. 184

17.0 Real Time Clock ........................................................................................................................................................................ 189

18.0 Week Timer ............................................................................................................................................................................... 201

19.0 TACH ........................................................................................................................................................................................ 211

20.0 PWM ......................................................................................................................................................................................... 218

21.0 Analog to Digital Converter ....................................................................................................................................................... 223

22.0 Blinking/Breathing LED ............................................................................................................................................................. 235

23.0 I2C/SMBus Interface ................................................................................................................................................................. 251

24.0 Quad SPI Master Controller ...................................................................................................................................................... 255

25.0 Trace FIFO Debug Port (TFDP) ................................................................................................................................................ 274

26.0 VBAT-Powered Control Interface .............................................................................................................................................. 278

27.0 VBAT-Powered RAM ................................................................................................................................................................ 289

28.0 VBAT Register Bank ................................................................................................................................................................. 291

29.0 EC Subsystem Registers ..................................................................................................

30.0 Security Features ...................................................................................................................................................................... 301

31.0 OTP Block ................................................................................................................................................................................. 305

32.0 Test Mechanisms ...................................................................................................................................................................... 308

33.0 Electrical Specifications ............................................................................................................................................................ 310

34.0 Timing Diagrams ....................................................................................................................................................................... 319

Appendix A: Data Sheet Revision History ......................................................................................................................................... 335

The Microchip Web Site .................................................................................................................................................................... 336

Customer Change Notification Service ............................................................................................................................................. 336

Customer Support ............................................................................................................................................................................. 336

Product Identification System ........................................................................................................................................................... 337

........................................................ 294

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CEC1712

1.0 GENERAL DESCRIPTION

The CEC1712 device is a low power integrated embedded controller designed with strong cryptographic support . The
CEC1712 is a highly-configurable, mixed-signal, advanced I/O controller architecture. It contains a 32-bit ARM® Cortex­M4 processor core with closely-coupled memory for optimal code execution and data access. An internal ROM, embed­ded in the design, is used to store the power on/boot sequence and APIs available during run time. When VTR_CORE
is applied to the device, the secure boot loader API is used to download the custom firmware image from the system’s
shared SPI Flash device, thereby allowing system designers to customize the device’s behavior.

The CEC1712 device is directly powered by a minimum of two separate suspend supply planes (VBAT and VTR). The
CEC1712 has two banks of I/O pins that are able to operate at either 3.3 V or 1.8 V. Operating at 1.8V allows the
CEC1712 to interface with the latest platform controller hubs and will lower the overall power consumed by the device,
Whereas 3.3V allows this device to be integrated into legacy platforms that require 3.3V operation.

The CEC1712 secure boot loader authenticates and optionally decrypts the SPI Flash OEM boot image using the AES­256, ECDSA P-384, SHA-384 cryptographic hardware accelerators. The CEC1712 hardware accelerators support 128­bit and 256-bit AES encryption, ECDSA and EC_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and Elliptic
asymmetric public key algorithms, and a True Random Number Generator (TRNG). Runtime APIs are provided in the
ROM for customer application code to use the cryptographic hardware. Additionally, the device offers lockable OTP stor­age for private keys and IDs. Additional features supported include Key Revocation, Roll back protection and DICE.

CEC1712 offers a software development system interface that includes a Trace FIFO debug port and a 2-pin Serail wire
debug (SWD)/ JTAG interface

1.1 Family Features

TABLE 1-1: CEC1712 FEATURE LIST

Features CEC1712 -84 WFBGA

Package 84 pin WFBGA

Device ID 0023_A2

Boundary Scan JTAG ID 0223_2445

CPU 32-bit ARM

SRAM 256 kB

Code/Data Options (Primary use) 224kB/32kB

Battery Backed SRAM 64 bytes

Trace FIFO Debug Port Yes

Internal DMA Channels 12

32-bit Timer 2

16-bit Timer 2

Capture Timer Registers 6

ICT Channels 11

Compare Timer Yes

Watchdog Timer (WDT) 1

Hibernation Timer 2

Week Timer 1

Sub Week Timer 1

RTC 1

RTOS Timer 1

Keyboard Matrix scan support No

SMBus 2.0 Host Controllers 5

®

Cortex-M4

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TABLE 1-1: CEC1712 FEATURE LIST (CONTINUED)

Features CEC1712 -84 WFBGA

Package 84 pin WFBGA

I2C Host Controllers 3

I2C/SMBus Ports 10

QMSPI Controller 1 Controller/2 ports

PWMs 6

Tachometers (TACHs) 2

GPIOs 68

Over voltage protected Pads 8

10/12- bit ADC Channels 5

UARTs 3

UART0: 2/4 pin configurable
UART1: 2 pin
UART2: 2 pin

Battery powered GPIO 1

VBAT powered Control Interface
inputs

2 Pin parallel XTAL Oscillator Yes

Single ended external 32kHz clock
input (XTAL2)

JTAG 4-pin/2-pin

AES Hardware Support 128-256 bit

SHA Hashing Support SHA-1 to SHA-512

Public Key Cryptography Support RSA: 4K bit

True Random Number Generator 1K bit

Root of Trust Yes

Secure Boot Yes

Immutable Code Yes

Customer OTP 288 bytes

Optional OTP Selectable Features (Note 1)

QA Testing Yes

JTAG Disable Yes

Authentication Yes

Encrypt ECDH Private Key (Bytes 0-

31)

AES Encryption Mandatory Yes

OTP Write Lock - [0] ECDH Private
Key

OTP Write Lock - [4] Authentication
Key - Public Qx

OTP Write Lock - [5] Authentication
Key - Public Qy

OTP Write Lock - [6] ECDH Public
Key 2, Public Rx

OTP Write Lock - [7] ECDH Public
Key 2, Public Ry

TAG0 SPI Flash Base Address Yes

2

Yes

ECC: 571 bit

Yes

Yes

Yes

Yes

Yes

Yes

CEC1712

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CEC1712

UART0

Battery

Pack

SMBus

Fansor

General

Use

PWMs

2‐pinUART

(x2)

UART

BreathingPWM

TraceFIFO

Deb ugPort

TFDP

SMBus/

I2CDevice

(s)

SMBus/I2C

GPIOs

VoltageMo ni tori ng

(e.g.,Thermistors,

PowerSupplies)

ADCs

PowerSupply

PowerButton(s)

BatteryPowered

GPIO

BGPO

2/4‐pin

Deb ug

JTAG

CEC1712Embedded

Controller

2/4‐pin

UART

QuadSPI(x2)

MainPowerSupply

VCC_PWRGD

LEDs(x2)

ICT

Sensors/

PWMinputs

TACH s

VCI_OUT

Note 1: Please refer to Boot ROM document for below set of optional OTP selectable feature.

1.2 Boot ROM

Following the release of the RESET_EC signal, the processor will start executing code in the Boot ROM. The B oot ROM
executes the SPI Flash Loader, which downloads User Code from SPI Flash and stores it in the internal Code RAM.
Refer to CEC1712 Boot ROM document for further details.

1.3 System Block Diagram

1.4 CEC1712 Internal Address Spaces

The Internal Embedded Controller can access any register in the EC Address Space or Host Address Space.

DS00003416B-page 8  2020 Microchip Technology Inc.

FIGURE 1-1: BLOCK DIAGRAM

Bus Swi tch

ARMM4F

JTAG/SWD

Memory

Controller

BootROM

SRAM

SRAM

DTCM

ITCM

MASTER MASTERSLAVE

Internal

DMA

Controller

HASH/AES

Engin e

PublicKey

Engin e

Crypto

RAM

SLAVE

Wa tc hdog

Timer

16‐bit B asi c

Timer

(x4)

32‐bit B asi c

Timer

(x2)

Capture/
Compare

Timer

SMB/I2C

Controller

(x5)

QuadSPI

Master

PWM

(x6)

Tach

(x2)

ADC

TraceFIFO

Hibernation

Timer

(x2)

WeekT imer

64Byte

VBATRAM

Blink/

BreatheLED

(x2)

Random

Number

Generator

VBAT

Control

Interface

RTOSTimer

Interrupt

Aggregator

SLAVE SLAVE

OTP

Power,
Clocks,

Resets

GPIOs

UART

(x3)

RealTime

Clock

MASTER

CEC1712

 2020 Microchip Technology Inc. DS00003416B-page 9

CEC1712

2.0 PIN CONFIGURATION

2.1 Description

The Pin Configuration chapter includes Pin List, Pin Multiplexing.

2.2 Terminology and Symbols for Pins/Buffers

2.2.1 BUFFER TERMINOLOGY

Term Definition

# The ‘#’ sign at the end of a signal name indicates an active-low signal

n The lowercase ‘n’ preceding a signal name indicates an active-low signal

PWR Power

Programmable as Input, Output, Open Drain Output, Bi-directional or Bi-directional with Open
Drain Output. Configurable drive strength from 2ma to12ma.

PIO

In I Type Input Buffer.

O2 O-2 mA Type Buffer.

PECI PECI Input/Output. These pins operate at the processor voltage level (VREF_VTT)

SB-TSI SB-TSI Input/Output. These pins operate at the processor voltage level (VREF_VTT)

Note: All GPIOs have programmable drive strength options of 2ma, 4ma, 8ma and 12ma.

GPIO pin drive strength is determined by the Pin Control Register Defaults field in
the Pin Control Register 2.

2.2.2 PIN NAMING CONVENTIONS

• Pin Name is composed of the multiplexed options separated by ‘/’. E.g., GPIOxxxx/SignalA/SignalB.

• The first signal shown in a pin name is the default signal. E.g., GPIOxxxx/SignalA/SignalB means the GPIO is the
default signal.

• Parenthesis ‘()’ are used to list aliases or alternate functionality for a single mux option.

• Square brackets ‘[ ]’ are used to indicate there is a Strap Option on a pin. This is always shown as the last signal
on the Pin Name.

• Signal Names appended with a numeric value indicates the Instance Number. E.g., PWM0, PWM1, etc. indicates
that PWM0 is the PWM output for PWM Instance 0, PWM1 is the PWM output for PWM Instance 1, etc. The
instance number may be omitted if there in only one instance of the IP block implemented.

2.3 Pin List

TABLE 2-1: CEC1712 PIN MAP

Ball map Signal

D2 nRESET_IN

F3 GPIO057/VCC_PWRGD

E2 GPIO106/PWROK

B2 GPIO051/ICT1_TACH1

A3 GPIO050/ICT0_TACH0

F2 GPIO200/ADC00/TRACEDAT0

G2 GPIO201/ADC01/TRACEDAT1

H2 GPIO202/ADC02/TRACEDAT2

G1 GPIO203/ADC03/TRACEDAT3

H1 GPIO204/ADC04

DS00003416B-page 10  2020 Microchip Technology Inc.

Ball map Signal

D1 VSS

J8 GPIO070/I2C14_SDA

K8 GPIO071/I2C14_SCL

J6 GPIO063/PWM6_ALT/ICT8

K3 GPIO224/SHD_IO1

K2 GPIO016/SHD_IO3/ICT3

K4 GPIO227/SHD_IO2

K5 GPIO223/SHD_IO0

K7 GPIO055/PWM2/SHD_CS0#

K6 GPIO056/PWM3/SHD_CLK

K1 GPIO012/I2C07_SDA

J2 GPIO013/I2C07_SCL

J5 GPIO130/I2C01_SDA

J9 GPIO131/I2C01_SCL

J3 GPIO020

J4 GPIO021

J7 GPIO002/PWM5/SHD_CS1#

H6 GPIO015/PWM7/ICT10

H5 GPIO032

A9 GPIO132/I2C06_SDA

B7 GPIO140/I2C06_SCL/ICT5

K9 GPIO026/I2C12_SDA

K10 GPIO053/PWM0

J10 GPIO027/I2C12_SCL

G7 GPIO030/I2C10_SDA

H9 GPIO107/I2C10_SCL

H10 GPIO120

G9 GPIO112

G10 GPIO113/ICT9

G4 GPIO034

F9 GPIO170/UART1_TX[JTAG_STRAP]

F8 GPIO171/UART1_RX

E8 JTAG_RST#

D9 GPIO104/UART0_TX/TFDP_CLK[VTR2_STRAP]

E9 GPIO105/UART0_RX/TFDP_DATA/TRACECLK

C9 GPIO046/ICT11

B8 GPIO047/PWM3_ALT/ICT13

D10 GPIO121/PVT_IO0

B10 GPIO122/PVT_IO1

E10 GPIO123/PVT_IO2

F10 GPIO126/PVT_IO3

C10 GPIO124/PVT_CS#/ICT12

A10 GPIO125/PVT_CLK

C6 GPIO127

CEC1712

 2020 Microchip Technology Inc. DS00003416B-page 11

CEC1712

Ball map Signal

D7 GPIO156/LED0

B9 GPIO157/LED1

C5 GPIO045/PWM2_ALT/ICT14

A6 GPIO165/32KHZ_IN/CTOUT0

C2 GPIO145/I2C09_SDA/JTAG_TDI/UART2_RX

B6 GPIO146/I2C09_SCL/JTAG_TDO/UART2_TX

A7 GPIO147/I2C15_SDA/JTAG_CLK

B3 GPIO150/I2C15_SCL/JTAG_TMS

E7 GPIO143/I2C04_SDA/UART0_CTS#

D6 GPIO144/I2C04_SCL/UART0_RTS#

A8 GPIO004/I2C00_SCL

B5 GPIO003/I2C00_SDA

A5 VCI_IN3#/GPIO000

B4 VCI_IN0#/GPIO163

B1 BGPO0/GPIO253

A1 VCI_OUT/GPIO250

A4 XTAL1

A2 XTAL2

D4 VSS_ANALOG

C1 VTR_PLL

D5 VBAT

E4 VSS

E1 VTR_REG

E3 VREF_ADC

F7 VSS

G6 VTR1

F4 VTR_ANALOG

F1 VR_CAP

G5 VTR2

J1 VSS_ADC

Note: GPIO055/PWM2/SHD_CS0# should be pulled up for proper boot up of the chip.

2.4 Pin Multiplexing

2.4.1 DEFAULT STATE

The default state for analog pins is Input. The default state for all pins that default to a GPIO function is input/output/inter­rupt disabled. The default state for pins that differ is shown in the Section 3.5, "GPIO Register Assignments". Entries for
the Default State column are

• O2ma-Low: Push-Pull output, Slow slew rate, 2ma drive strength, grounded

• O2ma-High Push-Pull output, Slow slew rate, 2ma drive strength, high output

• PU Input, with pull-up resistor enabled

2.4.2 POWER RAIL

The Power Rail column defines the power pin that provides I/O power for the signal pin.

DS00003416B-page 12  2020 Microchip Technology Inc.

CEC1712

2.4.3 BUFFER TYPES

The Buffer Type column defines the type of Buffer associated with each signal. Some pins have signals with two different
buffer types sharing the pin; in this case, table shows the buffer type for each of the signals that share the pin.

Input signals muxed with GPIOs are marked as “I”

Output signals muxed with GPIOs are marked as “PIO”, because the GPIO input path is always active even when the
alternate function selected is “output only”. So the GPIO input can be read to see the level of the output signal.

Pad Types are defined in the Section 33.0, "Electrical Specifications," on page 310.

• I/O Pad Types are defined in Section 33.2.4, "DC Electrical Characteristics for I/O Buffers," on page 312.

• The abbreviation “PWR” is used to denote power pins. The power supplies are defined in Section 33.2.1, "Power

Supply Operational Characteristics," on page 310.

2.4.4 GLITCH PROTECTION

Pins with glitch protection are glitch-free tristate pins and will not drive out while their associated power rail is rising.
These glitch-free tristate pins require either an external pull-up or pull-down to set the state of the pin high or low.

Note: If the pin needs to default low, a 1M ohm (max) external pull-down is required.

All pins are glitch protected.

Note: The power rail must rise monotonically in order for glitch protection to operate.

2.4.5 OVER-VOLTAGE PROTECTION

If a pin is over-voltage protected (over-voltage protection = YES) then the following is true: If the pad is powered by 1.8V
+/- 5% (operational) it can tolerate up to 3.63V on the pad. This allows for a pull-up to 3.3V power rail +/- 10%. If the
pad is powered by 3.3V +/- 5% (operational) it can tolerate up to 5.5V on the pad. This allows for a pull-up to 5.0V power
rail +/- 10%.

If a pin is not over-voltage protected (over-voltage protection = NO) then the following is true: If the pad is powered by

1.8V +/- 5% (operational), it can tolerate up to 1.8V +10% (i.e., +1.98V max). If the pad is powered by 3.3V +/- 5% (oper-

ational) it can tolerate up to 3.3V +10% (i.e., +3.63V max).

2.4.6 UNDER-VOLTAGE PROTECTION

Pins that are identified as having Under-voltage PROTECTION may be configured so they will not sink excess current
if powered by 3.3V and externally pulled up to 1.8V. The following configuration requirements must be met.

• If the pad is an output only pad type and it is configured as either open drain or the output is disabled.

• If the pin is a GPIO pin with a PIO pad type then is must be configured as open drain output with the input dis­abled. The input is disabled by setting the GPIO Power Gating Signals (PGS) bits to 11b.

All pins are under voltage protected.

2.4.7 BACKDRIVE PROTECTION

Assuming that the external voltage on the pin is within the parameters defined for the specific pad type, the backdrive
protected pin will not sink excess current when it is at a lower potential than the external circuit. There are two cases
where this occurs:

• The pad power is off and the external circuit is powered

• The pad power is on and the external circuitry is pulled to a higher potential than the pad power. This may occur
on 3.3V powered pads that are 5V tolerant or on 1.8V powered pads that are 3.6V tolerant.

2.4.8 EMULATED POWER WELL

Power well emulation for GPIOs and for signals that are multiplexed with GPIO signals is controlled by the Power Gating

Signals (PGS) option in the GPIO Pin Control Register. The Emulated Power Well column in the Pin Multiplexing table

defines the power gating programming options supported for each signal.

 2020 Microchip Technology Inc. DS00003416B-page 13

CEC1712

Note: VBAT powered signals do not support power emulation and must program the PGS bit field to 00b (VTR)

2.4.9 GATED STATE

This column defines the internal value of an input signal when either its emulated power well is inactive or it is not
selected by the GPIO alternate function MUX. A value of “No Gate” means that the internal signal always follows the
pin even when the emulated power well is inactive.

Note: Gated state is only meaningful to the operation of input signals. A gated state on an output pin defines the

internal behavior of the GPIO MUX and does not imply pin behavior.

Note: Only the pins that are 5V tolerant have an entry in the 5VT column in the Pin Description Table.

2.4.10 NOTES

The below notes are for all tables in this chapter.

TABLE 2-2: NUMBERED NOTES

NOTE Description

Note 1 An external cap must be connected as close to the VR_CAP pin/ball as possible with a routing resistance

and CAP ESR of less than 100mohms. The capacitor value is 1uF and must be ceramic with X5R or X7R
dielectric. The cap pin/ball should remain on the top layer of the PCB and traced to the CAP. Avoid adding
vias to other layers to minimize inductance.

Note 2 This SMBus ports supports 1 Mbps operation as defined by I2C. For 1 Mbps I2C recommended capaci-

tance/pull-up relationships from Intel, refer to the Shark Bay platform guide, Intel ref number 486714. Refer
to the PCH - SMBus 2.0/SMLink Interface Design Guidelines, Bus Capacitance/Pull-Up Resistor Relation­ship.

Note 4 The voltage on the ADC pins must not exceed 3.6 V or damage to the device will occur.

Note 5 The VCI pins may be used as GPIOs. The VCI input signals are not gated by selecting the GPIO alternate

function. Firmware must disable (i.e., gate) these inputs by writing the bits in the VCI Input Enable Register
when the GPIO function is enabled.

Note 6 The Over voltage protected GPIO pins will not support the Repeater mode mentioned in the GPIO pin con-

figuration register

Note 7 Refer Configurable Signal Routing section under Pin Configuration chapter for details on using the <signal>

and <signal>_ALT. Both <signal> and <signal>_ALT cannot be enabled simultaneously.

Note 8 <Signal> with ‘#’ as suffix will be shown as <Signal>_n in MPLab Tools

Note 9 32kHz_IN is named CLK32kHz_IN in MPLab Tools

Note 10 Clock Enable Register Bits [3:2] should be configured to be driven by single ended 32Khz source. Connect

the pin to SUSCLK from PCH.

Note 11 When the JTAG_RST# pin is not asserted (logic'1'), the JTAG or ARM SWJ signal functions in the JTAG

interface are unconditionally routed to the GPIO interface; the Pin Control register for these GPIO pins has
no effect.When the JTAG_RST# pin is asserted (logic'0'), the signal functions in the JTAG interface are not
routed to the interface and the Pin Control Register for these GPIO pins controls the muxing. The pin con­trol registers can not route the JTAG interface to the pins. System Board Designer should terminate this pin
in all functional state using jumpers and pull-up or pull down resistors, etc.

Note 12 The JTAG signals TDI,TDO,TMS,TCK are muxed with GPIO pins. Routing of JTAG signals to these pins

are dependent on DEBUG ENABLE REGISTER bits [2:0] and JTAG_RST# pin (Note . To configure these
GPIO pins for non JTAG functions, pull JTAG_RST# low externally and select the appropriate alternate
function in the Pin Control Register

Note 13 The BGPO pins may be used as GPIO. For this the BGPO power control register and GPIO pin control reg-

ister needs to be configured

Note 14 GPIO000/VCI_IN3#, if not used must be connected to VBAT through a high impedance resistor of the order

of 100k

DS00003416B-page 14  2020 Microchip Technology Inc.

TABLE 2-2: NUMBERED NOTES

NOTE Description

Note 15 External pull up should be added on GPIO055/SHD_CS0# pin for proper booting

2.4.11 CEC1712 MULTIPLEXING

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

Gated

State

CEC1712

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0nRESET_IN I VTR1 PGS=00

(only)

1 Reserved

2 Reserved

3 Reserved

Default: 0GPIO057 PIO VTR1 All PGS

options

1 VCC_PWRGD PIO PGS=00

(only)

2 Reserved

3 Reserved

Default: 0GPIO106 PIO VTR1 All PGS

options

1 PWROK PIO PGS=00

(only)

2 Reserved

3 Reserved

Default: 0GPIO051 PIO VTR1 All PGS

options

1 ICT1_TACH1 PIO All PGS

options

2 Reserved

3 Reserved

Yes

No Gate Yes Yes

High

No Gate Yes

NA

No Gate Yes

Low

Default: 0GPIO050 PIO VTR1 All PGS

options

1 ICT0_TACH0 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO200 PIO VTR1 All PGS

options

 2020 Microchip Technology Inc. DS00003416B-page 15

No Gate Yes

Low

No Gate No

CEC1712

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

1 ADC00 I_AN PGS=00

2 Reserved

3 Reserved

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

(only)

Gated

State

Low Note 4

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO201 PIO VTR1 All PGS

options

1 ADC01 I_AN PGS=00

(only)

2 Reserved

3 Reserved

Default: 0GPIO202 PIO VTR1 All PGS

options

1 ADC02 I_AN PGS=00

(only)

2 Reserved

3 Reserved

Default: 0GPIO203 PIO VTR1 All PGS

options

1 ADC03 I_AN PGS=00

(only)

2 Reserved

3 Reserved

Default: 0GPIO204 PIO VTR1 All PGS

options

1 ADC04 I_AN PGS=00

(only)

2 Reserved

3 Reserved

No Gate No

Low Note 4

No Gate No

Low Note 4

No Gate No

Low Note 4

No Gate No

Low Note 4

Default: 0GPIO070 PIO VTR2 All PGS

options

1 Reserved

2 I2C14_SDA PIO All PGS

options

3 Reserved

Default: 0GPIO071 PIO VTR2 All PGS

options

1 Reserved

2 I2C14_SCL PIO All PGS

options

3 Reserved

DS00003416B-page 16  2020 Microchip Technology Inc.

No Gate Yes

High

No Gate Yes

High

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

Gated

State

CEC1712

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO063 PIO VTR2 All PGS

options

1 Reserved

2 PWM6_ALT PIO All PGS

options

3 ICT8 I All PGS

options

Default: 0GPIO224 PIO VTR2 All PGS

options

1 Reserved

2 SHD_IO1 PIO All PGS

options

3 Reserved

Default: 0GPIO016 PIO VTR2 All PGS

options

1 Reserved

2 SHD_IO3 PIO All PGS

options

3 ICT3 PIO All PGS

options

No Gate Yes

NA Note 7

Low

No Gate Yes

Low

No Gate Yes

Low

Low

Default: 0GPIO227 PIO VTR2 All PGS

options

1 SHD_IO2 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO223 PIO VTR2 All PGS

options

1 SHD_IO0 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO055 PIO VTR2 All PGS

options

1 PWM2 PIO All PGS

options

2 SHD_CS0# PIO All PGS

options

3 Reserved

No Gate Yes

Low

No Gate Yes

Low

No Gate Yes

NA

NA Note

15

 2020 Microchip Technology Inc. DS00003416B-page 17

CEC1712

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

Default: 0GPIO056 PIO VTR2 All PGS

1 PWM3 PIO All PGS

2 SHD_CLK PIO All PGS

3 Reserved

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

options

options

options

Gated

State

No Gate Yes

NA

NA

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO012 PIO VTR2 All PGS

options

1 I2C07_SDA PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO013 PIO VTR2 All PGS

options

1 I2C07_SCL PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO130 PIO VTR2 All PGS

options

1 I2C01_SDA PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO131 PIO VTR2 All PGS

options

1 I2C01_SCL PIO All PGS

options

2 Reserved

3 Reserved

No Gate Yes Yes

High Note 2

No Gate Yes Yes

High Note 2

No Gate Yes Yes

High Note 2

No Gate Yes Yes

High Note 2

Default: 0GPIO020 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 Reserved

Default: 0GPIO021 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

DS00003416B-page 18  2020 Microchip Technology Inc.

No Gate Yes

No Gate Yes

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

3 Reserved

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

Gated

State

CEC1712

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO002 PIO VTR2 All PGS

options

1 PWM5 PIO All PGS

options

2 SHD_CS1# PIO All PGS

options

3 Reserved

Default: 0GPIO015 PIO VTR2 All PGS

options

1 PWM7 PIO All PGS

options

2 ICT10 I All PGS

options

3 Reserved

Default: 0GPIO032 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 Reserved

Default: 0GPIO132 PIO VTR1 All PGS

options

1 I2C06_SDA PIO All PGS

options

2 Reserved

3 Reserved

No Gate Yes

NA

High

No Gate Yes

NA

Low

No Gate Yes

No Gate Yes

High

Default: 0GPIO140 PIO VTR1 All PGS

options

1 I2C06_SCL PIO All PGS

options

2 ICT5 PIO All PGS

options

3 Reserved

Default: 0GPIO026 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 I2C12_SDA PIO All PGS

options

 2020 Microchip Technology Inc. DS00003416B-page 19

No Gate Yes

High

Low

No Gate Yes

High

CEC1712

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

Default: 0GPIO053 PIO VTR2 All PGS

1 PWM0 PIO All PGS

2 Reserved

3 Reserved

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

options

options

Gated

State

No Gate Yes

NA

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO027 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 I2C12_SCL PIO All PGS

options

Default: 0GPIO030 PIO VTR1 All PGS

options

1 Reserved

2 I2C10_SDA PIO All PGS

options

3 Reserved

Default: 0GPIO107 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 I2C10_SCL PIO All PGS

options

Default: 0GPIO120 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 Reserved

No Gate Yes

High

No Gate Yes

High

No Gate Yes

High

No Gate Yes

Default: 0GPIO112 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 Reserved

Default: 0GPIO113 PIO VTR1 All PGS

options

1 Reserved

2 ICT9 I All PGS

options

DS00003416B-page 20  2020 Microchip Technology Inc.

No Gate Yes

No Gate Yes

Low

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

3 Reserved

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

Gated

State

CEC1712

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO034 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 Reserved

Default: 0GPIO170 PIO PU VTR1 All PGS

options

1 UART1_TX PIO All PGS

options

2 Reserved

3 Reserved

Strap JTAG_STRAP PIO

Default: 0GPIO171 PIO VTR1 All PGS

options

1 UART1_RX PIO All PGS

options

2 Reserved

3 Reserved

Default: 0JTAG_RST# I VTR1 N/A Yes Note

1 Reserved

2 Reserved

3 Reserved

No Gate Yes

No Gate Yes

NA

No Gate Yes

Low

11, 12

Default: 0GPIO104 PIO VTR1 All PGS

options

1 UART0_TX PIO All PGS

options

2 TFDP_CLK PIO All PGS

options

3 Reserved

Strap VTR2_STRAP PIO

Default: 0GPIO105 PIO VTR1 All PGS

options

1 UART0_RX PIO All PGS

options

2 TFDP_DATA PIO All PGS

options

3 Reserved

Default: 0GPIO046 PIO VTR1 All PGS

options

 2020 Microchip Technology Inc. DS00003416B-page 21

No Gate Yes

NA

NA

No Gate Yes

Low

NA

No Gate Yes

CEC1712

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

1 KSO2 PIO All PGS

2 Reserved

3 ICT11 I All PGS

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

options

options

Gated

State

NA

Low

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO047 PIO VTR1 All PGS

options

1 Reserved

2 PWM3_ALT PIO All PGS

options

3 ICT13 I All PGS

options

Default: 0GPIO121 PIO VTR1 All PGS

options

1 PVT_IO0 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO122 PIO VTR1 All PGS

options

1 PVT_IO1 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO123 PIO VTR1 All PGS

options

1 PVT_IO2 PIO All PGS

options

2 Reserved

3 Reserved

No Gate Yes

NA Note 7

Low

No Gate Yes

Low

No Gate Yes

Low

No Gate Yes Yes

Low

Default: 0GPIO126 PIO VTR1 All PGS

options

1 PVT_IO3 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO124 PIO VTR1 All PGS

options

1 PVT_CS# PIO All PGS

options

DS00003416B-page 22  2020 Microchip Technology Inc.

No Gate Yes

Low

No Gate Yes

NA

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

2 Reserved

3 ICT12 I All PGS

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

options

Gated

State

Low

CEC1712

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO125 PIO VTR1 All PGS

options

1 PVT_CLK PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO127 PIO VTR1 All PGS

options

1 Reserved

2 Reserved

3 Reserved

Default: 0GPIO156 PIO VTR1 All PGS

options

1 LED0 PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO157 PIO VTR1 All PGS

options

1 LED1 PIO All PGS

options

2 Reserved

3 Reserved

No Gate Yes

NA

No Gate Yes

No Gate Yes Yes

NA

No Gate Yes Yes

NA

Default: 0GPIO045 PIO VTR1 All PGS

options

1 Reserved

2 PWM2_ALT PIO All PGS

options

3 ICT14 I All PGS

options

Default: 0GPIO165 PIO VTR1 All PGS

options

1 32KHZ_IN PIO PGS=00

(only)

2 Reserved

3 CTOUT0 PIO All PGS

options

 2020 Microchip Technology Inc. DS00003416B-page 23

No Gate Yes

NA

Low

No Gate Yes

Low

NA

CEC1712

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

Gated

State

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO145 PIO VTR1 All PGS

options

1 I2C09_SDA PIO All PGS

options

2 UART2_RX I All PGS

options

3 Reserved

Default: 0GPIO146 PIO VTR1 All PGS

options

1 I2C09_SCL PIO All PGS

options

2 UART2_TX PIO All PGS

options

3 Reserved

Default: 0GPIO147 PIO VTR1 All PGS

options

1 I2C15_SDA PIO All PGS

options

2 Reserved

3 Reserved

No Gate Yes

High

Low

No Gate Yes

High

NA

No Gate Yes

High

Default: 0GPIO150 PIO VTR1 All PGS

options

1 I2C15_SCL PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO143 PIO VTR1 All PGS

options

1 I2C04_SDA PIO All PGS

options

2 UART0_CTS# I All PGS

options

3 Reserved

Default: 0GPIO144 PIO VTR1 All PGS

options

1 I2C04_SCL PIO All PGS

options

2 UART0_RTS# PIO All PGS

options

3 Reserved

No Gate Yes

High

No Gate Yes

High

High

No Gate Yes

High

NA

DS00003416B-page 24  2020 Microchip Technology Inc.

TABLE 2-3: CEC1712 PIN MULTIPLEXING

Mux

Value

Signal Name

Buffer

Typ e

Drive

Strength

PAD

Power

Well

Emulated

Power

Well

Gated

State

CEC1712

OverVolt-

age

Protect

Back-

drive

Protect

Notes

Default: 0GPIO004 PIO VTR1 All PGS

options

1 I2C00_SCL PIO All PGS

options

2 Reserved

3 Reserved

Default: 0GPIO003 PIO VTR1 All PGS

options

1 I2C00_SDA PIO All PGS

options

2 Reserved

3 Reserved

0 GPIO000 PIO VBAT All PGS

options

Default: 1VCI_IN3# ILLK PGS=00

(only)

2 Reserved

3 Reserved

0 GPIO163 PIO VBAT All PGS

options

Default: 1VCI_IN0# ILLK PGS=00

(only)

2 Reserved

3 Reserved

No Gate Yes

High

No Gate Yes

High

No Gate Yes

No Gate Note

14

No Gate Yes

No Gate Note 5

0 GPIO253 PIO VBAT All PGS

options

Default: 1BGPO0 PIO O2ma-

Low

2 Reserved

3 Reserved

0 GPIO250 PIO VBAT All PGS

Default: 1VCI_OUT PIO O2ma-

High

2 Reserved

3 Reserved

 2020 Microchip Technology Inc. DS00003416B-page 25

PGS=00
(only)

options

PGS=00
(only)

No Gate Yes

NA Note

13

No Gate Yes

NA

CEC1712

2.5 Configurable Signal Routing

To accommodate the signal routing across packages, some Signals are routed to more than one GPIO. At any given
time, only the <Signal> or <Signal>_ALT can be selected. Both cannot be selected at the same time.

2.5.1 SIGNAL DESCRIPTION BY INTERFACE

TABLE 2-4: SIGNAL DESCRIPTION BY INTERFACE

SIG_NAME Description Notes

ADC

ADCxx ADC channel input Note 5

‘xx’ is the index of the ADC input. Refer Family
features table to find the number of ADC
inputs supported in the package

Miscellaneous

I2C/SMBus Controller

I2Cxx_SDA I2C/SMBus Controller Port 0 Data Note 2

‘xx’ is the index of the I2C port. Refer Family
features table to find the number of I2C ports
supported in the package

I2Cxx_SCL I2C/SMBus Controller Port 0 Clock Note 2

GPIO

GPIOx General Purpose Input Output Pins

PCR Interface

32KHZ_OUT 32.768 KHz Digital Output

32KHZ_IN 32.768 KHz Digital Input

nRESET_IN External System Reset Input

PECI

PECI_DAT PECI Bus

VREF_VTT Processor Interface Voltage Reference

Quad Mode SPI Controller ports

PVT_CS# Private SPI Chip Select SPI_CS0# of QMSPI Controller

PVT_IO0 Private SPI Data 0 SPI_IO0 of QMSPI Controller

PVT_IO1 Private SPI Data 1 SPI_IO1 of QMSPI Controller

PVT_IO2 Private SPI Data 2 SPI_IO2 of QMSPI Controller

PVT_IO3 Private SPI Data 3 SPI_IO3 of QMSPI Controller

PVT_CLK Private SPI Clock SPI_CLK of QMSPI Controller

SHD_CS1# Shared SPI Chip Select1 SPI_CS1# of QMSPI Controlelr

SHD_CS0# Shared SPI Chip Select SPI_CS0# of QMSPI Controller

SHD_IO0 Shared SPI Data 0 SPI_IO0 of QMSPI Controller

SHD_IO1 Shared SPI Data 1 SPI_IO1 of QMSPI Controller

SHD_IO2 Shared SPI Data 2 SPI_IO2 of QMSPI Controller

SHD_IO3 Shared SPI Data 3 SPI_IO3 of QMSPI Controller

SHD_CLK Shared SPI Clock SPI_CLK of QMSPI Controller

DS00003416B-page 26  2020 Microchip Technology Inc.

CEC1712

TABLE 2-4: SIGNAL DESCRIPTION BY INTERFACE (CONTINUED)

SIG_NAME Description Notes

FAN PWM and Tachometer

ICT0_TACH0 Fan Tachometer Input 0

ICT1_TACH1 Fan Tachometer Input 1

ICT2_TACH2 Fan Tachometer Input 2

TACH3 Fan Tachometer Input 3

PWMx Pulse Width Modulator Output ‘x’ is the index of the PWM output. Refer Fam-

ily features table to find the number of PWM
outputs supported in the package

Input Capture/Compare timer

ICTx Input capture timer input ‘x’ is the index of the PWM output. Refer Fam-

ily features table to find the number of ICT
inputs supported in the package

CTOUT0 Compare timer 0 toggle output

CTOUT1 Compare timer 1 toggle output

Serial ports

UART_CLK UART Baud Clock Input

UART0_RX UART Receive Data (RXD)

UART0_TX UART Transmit Data (TXD)

UART0_CTS# Clear to Send Input

UART0_RTS# Request to Send Output

UART0_RI# Ring Indicator Input

UART0_DCD# Data Carrier Detect Input

UART0_DSR# Data Set Ready Input

UART0_DTR# Data Terminal Ready Output

JTAG

JTAG_RST# JTAG test active low reset Note 11,12

JTAG_TDI JTAG test data in Note 11,12

JTAG_TDO JTAG test data out Note 11,12

JTAG_CLK JTAG test clk; SWDCLK Note 11,12

JTAG_TMS JTAG test mode select; SWDIO Note 11,12

TFDP_DATA Trace FIFO debug port - data

TFDP_CLK Trace FIFO debug port - clock

TRACECLK ARM Embedded Trace Macro Clock Trace Port is enabled by setting TRACE_EN

bit of ETM Trace enable register in EC Regis­ter Bank

TRACEDATA0 ARM Embedded Trace Macro Data 0

TRACEDATA1 ARM Embedded Trace Macro Data 1

TRACEDATA2 ARM Embedded Trace Macro Data 2

TRACEDATA3 ARM Embedded Trace Macro Data 3

Power pins

VREF_ADC ADC Reference Voltage

VSS_ADC Analog ADC supply associated ground

VBAT VBAT supply

VR_CAP Internal Voltage Regulator Capacitor Note 1

 2020 Microchip Technology Inc. DS00003416B-page 27

CEC1712

TABLE 2-4: SIGNAL DESCRIPTION BY INTERFACE (CONTINUED)

SIG_NAME Description Notes

VSS VTR associated ground

VSS_VBAT VBAT associated ground

VTR1 VTR Suspend Power Supply

VTR2 Peripheral Power Supply

VTR_PLL PLL power supply

VTR_REG Main Regulator Power supply

2.5.2 STRAPPING OPTIONS

GPIO170 is used for the TAP Controller select strap. If any of the JTAG TAP controllers are used, GPIO170 must only
be configured as an output to a VTRx powered external function. GPIO170 may only be configured as an input when
the JTAG TAP controllers are not needed or when an external driver does not violate the Slave Select Timing.See Sec-

tion 32.2.1, "TAP Controller Select Strap Option".

TABLE 2-5: STRAP PINS

Pin Name Strap Name Strap Define and Value

GPIO170 JTAG_STRAP 1= Boundary Scan

The JTAG Port is used to access the Boundary scan TAP
controller
0= Normal Operation
The JTAG port is used to access the ARM TAP Controller

I/O Power

Rail

VTR1

GPIO104 VTR2_STRAP Voltage Level strap is used to determine if the Shared

Flash interface must be configured for 3.3V or 1.8V
operation
1= 3.3V Operation
0= 1.8V Operation

VTR1

2.6 Pin Default State Through Power Transitions

The power state and power state transitions illustrated in the following tables are defined in Section 4.0, "Power,

Clocks, and Resets". Pin behavior in this table assumes no specific programming to change the pin state. All GPIO

default pins that have the same behavior are described in the table generically as GPIOXXX.

TABLE 2-6: PIN DEFAULT STATE THROUGH POWER TRANSITIONS

RESET_

Signal

GPIO170

GPIOXXX

nRESET_IN

BGPOx Out=0 Out=0 Retain Retain Retain Retain

VCI_INx# In In In In In In

VBAT

Applied

un-

powered

un-

powered

un-

powered

VBAT

Stable

un-

powered

un-

powered

un-

powered

VTR

Applied

High In Z glitch

Z Z Z glitch

Low In Z glitch

SYS

De-

asserted

RESET_

SYS

Asserted

VTR

Un-

powered

VBAT

Un-

powered

un-

powered

un-

powered

un-

powered

un-

powered

un-

powered

Note

Note

D

Note

B

DS00003416B-page 28  2020 Microchip Technology Inc.

TABLE 2-6: PIN DEFAULT STATE THROUGH POWER TRANSITIONS

Signal

VCI_OUT

XTAL1

XTAL2

RESET_

VBAT

Applied

Out

logic

CrystalInCrystalInCrystalInCrystalInCrystalInCrystalInCrystal

Crystal

Out

VBAT

Stable

Out

logic

Crystal

Out

VTR

Applied

Out

logic

Crystal

Out

SYS

De-

asserted

Out

logic

Crystal

Out

RESET_

SYS

Asserted

Out

logic

Crystal

Out

VTR

Un-

powered

Out

logic

Crystal

Out

VBAT

powered

powered

Crystal

Un-

un-

In

Out

CEC1712

Note

Note

C

Legend
(P) = I/O state is driven by proto­col while power is applied.

Z = Tristate
In = Input

Notes

Note D: Does not include GPIO170

Note B: Pin is programmable by the EC and retains its value through a

VTR power cycle.

 2020 Microchip Technology Inc. DS00003416B-page 29

CEC1712

2.7 Package Information

2.7.1 84 PIN WFBGA/SX1 PACKAGE

Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.micro-

chip.com/packaging.

DS00003416B-page 30  2020 Microchip Technology Inc.

CEC1712

3.0 DEVICE INVENTORY

3.1 Conventions

Term Defi nition

Block Used to identify or describe the logic or IP Blocks implemented in the device.

Reserved Reserved registers and bits defined in the following table are read only values that

return 0 when read. Writes to these reserved registers have no effect.

TEST Microchip Reserved locations which should not be modified from their default value.

Changing a TEST register or a TEST field within a register may cause unwanted
results.

b The letter ‘b’ following a number denotes a binary number.

h The letter ‘h’ following a number denotes a hexadecimal number.

Register access notation is in the form “Read / Write”. A Read term without a Write term means that the bit is read-only
and writing has no effect. A Write term without a Read term means that the bit is write-only, and assumes that reading
returns all zeros.

Register Field

Type

R Read: A register or bit with this attribute can be read.

W Write: A register or bit with this attribute can be written.

RS Read to Set: This bit is set on read.

RC Read to Clear: Content is cleared after the read. Writes have no effect.

WC or W1C Write One to Clear: writing a one clears the value. Writing a zero has no effect.

WZC Write Zero to Clear: writing a zero clears the value. Writing a one has no effect.

WS or W1S Write One to Set: writing a one sets the value to 1. Writing a zero has no effect.

WZS Write Zero to Set: writing a zero sets the value to 1. Writing a one has no effect.

Field Description

 2020 Microchip Technology Inc. DS00003416B-page 31

CEC1712

3.2 Block Overview and Base Addresses

Table 3-1, "Base address" lists all the IP components, referred to as Blocks, implemented in the design. The registers

implemented in each block are accessible by the embedded controller (EC) at an offset from the Base Address shown
in Table 3-1, "Base address". The registers can also be accessed by various hosts in the system as below

1. I2C : I2C host access is handled by firmware

2. JTAG : JTAG port has access to all the registers defined in Table 3-1, "Base address".

TABLE 3-1: BASE ADDRESS

Feature Instance Logical Device Number Base Address

Watchdog Timer 4000_0400h

16-bit Basic Timer 0 4000_0C00h

16-bit Basic Timer 1 4000_0C20h

32-bit Basic Timer 0 4000_0C80h

32-bit Basic Timer 1 4000_0CA0h

Capture-Compare Timers 4000_1000h

DMA Controller 4000_2400h

SMB-I2C Controller 0 4000_4000h

SMB-I2C Controller 1 4000_4400h

SMB-I2C Controller 2 4000_4800h

SMB-I2C Controller 3 4000_4C00h

SMB-I2C Controller 4 4000_5000h

I2C Controller 5 4000_5100h

I2C Controller 6 4000_5200h

I2C Controller 7 4000_5300h

Quad Master SPI 4007_0000h

16-bit PWM 0 4000_5800h

16-bit PWM 2 4000_5820h

16-bit PWM 3 4000_5830h

16-bit PWM 5 4000_5850h

16-bit PWM 6 4000_5860h

16-bit PWM 7 4000_5870h

16-bit Tach 0 4000_6000h

16-bit Tach 1 4000_6010h

RTOS Timer 4000_7400h

ADC 4000_7C00h

Trace FIFO 4000_8C00h

Hibernation Timer 0 4000_9800h

Hibernation Timer 1 4000_9820h

VBAT Register Bank 4000_A400h

VBAT Powered RAM 4000_A800h

Week Timer 4000_AC80h

VBAT-Powered Control Interface 4000_AE00h

Blinking-Breathing LED 0 4000_B800h

Blinking-Breathing LED 1 4000_B900h

Interrupt Aggregator 4000_E000h

DS00003416B-page 32  2020 Microchip Technology Inc.

TABLE 3-1: BASE ADDRESS

Feature Instance Logical Device Number Base Address

EC Subsystem Registers 4000_FC00h

JTAG 4008_0000h

Power, Clocks and Resets 4008_0100h

GPIOs 4008_1000h

UART 0 9h 400F_2400h

UART 1 Ah 400F_2800h

UART 2 Bh 400F_2C00h

Real Time Clock 14h 400F_5000h

Global Configuration 3Fh 400F_FF00h

CEC1712

 2020 Microchip Technology Inc. DS00003416B-page 33

CEC1712

3.3 Sleep Enable Register Assignments

TABLE 3-2: SLEEP ALLOCATION

Block Instance

JTAG STAP 0 NA Clock Required 0 NA

Interrupt 0 Sleep Enable 1 Clock Required 1 Reset Enable 1

Tach 0 2 Sleep Enable 1 Clock Required 1 Reset Enable 1

PWM 0 4 Sleep Enable 1 Clock Required 1 Reset Enable 1

DMA 6 Sleep Enable 1 Clock Required 1 Reset Enable 1

TFDP 7 Sleep Enable 1 Clock Required 1 Reset Enable 1

PROCESSOR 8 Sleep Enable 1 Clock Required 1 NA

WDT 9 NA Clock Required 1 Reset Enable 1

SMB 0 10 Sleep Enable 1 Clock Required 1 Reset Enable 1

Tach 1 11 Sleep Enable 1 Clock Required 1 Reset Enable 1

PWM 2 21 Sleep Enable 1 Clock Required 1 Reset Enable 1

PWM 3 22 Sleep Enable 1 Clock Required 1 Reset Enable 1

PWM 5 24 Sleep Enable 1 Clock Required 1 Reset Enable 1

PWM 6 25 Sleep Enable 1 Clock Required 1 Reset Enable 1

PWM 7 26 Sleep Enable 1 Clock Required 1 Reset Enable 1

EC Register Bank 29 Sleep Enable 1 Clock Required 1 NA

Basic Timer 16 0 30 Sleep Enable 1 Clock Required 1 Reset Enable 1

Basic Timer 16 1 31 Sleep Enable 1 Clock Required 1 Reset Enable 1

UART 0 1 Sleep Enable 2 Clock Required 2 Reset Enable 2

UART 1 2 Sleep Enable 2 Clock Required 2 Reset Enable 2

Global Configuration 12 NA Clock Required 2 NA

RTC 18 NA Clock Required 2 NA

ADC 3 Sleep Enable 3 Clock Required 3 Reset Enable 3

Hibernation Timer 0 10 Sleep Enable 3 Clock Required 3 Reset Enable 3

SMB 1 13 Sleep Enable 3 Clock Required 3 Reset Enable 3

SMB 2 14 Sleep Enable 3 Clock Required 3 Reset Enable 3

SMB 3 15 Sleep Enable 3 Clock Required 3 Reset Enable 3

LED 0 16 Sleep Enable 3 Clock Required 3 Reset Enable 3

LED 1 17 Sleep Enable 3 Clock Required 3 Reset Enable 3

SMB 4 20 Sleep Enable 3 Clock Required 3 Reset Enable 3

Basic Timer 32 0 23 Sleep Enable 3 Clock Required 3 Reset Enable 3

Basic Timer 32 1 24 Sleep Enable 3 Clock Required 3 Reset Enable 3

Hibernation Timer 1 29 Sleep Enable 3 Clock Required 3 Reset Enable 3

CCT 0 30 Sleep Enable 3 Clock Required 3 Reset Enable 3

RTOS Timer 6 NA Clock Required 4 Reset Enable 4

Quad SPI Master 8 Sleep Enable 4 Clock Required 4 Reset Enable 4

I2C 5 10 Sleep Enable 4 Clock Required 4 Reset Enable 4

I2C 6 11 Sleep Enable 4 Clock Required 4 Reset Enable 4

I2C 7 12 Sleep Enable 4 Clock Required 4 Reset Enable 4

Bit

Position

Sleep Enable

Register

Clock Required

Register

Reset Enable

Register

DS00003416B-page 34  2020 Microchip Technology Inc.

CEC1712

3.4 Interrupt Aggregator Bit Assignments

TABLE 3-3: GIRQ_MAPPING

Agg IRQ

GIRQ8 0 GPIO140 GPIO Event Yes GPIO Interrupt Event 0 N/A

Agg

Bits

1-2 Reserved

3 GPIO143 GPIO Event Yes GPIO Interrupt Event

4 GPIO144 GPIO Event Yes GPIO Interrupt Event

5 GPIO145 GPIO Event Yes GPIO Interrupt Event

6 GPIO146 GPIO Event Yes GPIO Interrupt Event

7 GPIO147 GPIO Event Yes GPIO Interrupt Event

8 GPIO150 GPIO Event Yes GPIO Interrupt Event

9-13 Reserved

14 GPIO156 GPIO Event Yes GPIO Interrupt Event

15 GPIO157 GPIO Event Yes GPIO Interrupt Event

16 Reserved

17 GPIO161 GPIO Event Yes GPIO Interrupt Event

18 Reserved

19 GPIO163 GPIO Event Yes GPIO Interrupt Event

20 Reserved

21 GPIO165 GPIO Event Yes GPIO Interrupt Event

22-23Reserved

HWB

Instance

Name

Interrupt Event

Wake
event

Source description

Agg

NVIC

Direct

NVIC

24 GPIO170 GPIO Event Yes GPIO Interrupt Event

25 GPIO171 GPIO Event Yes GPIO Interrupt Event

25 Reserved

26 GPIO172 GPIO Event Yes GPIO Interrupt Event

27-28Reserved

29 GPIO175 GPIO Event Yes GPIO Interrupt Event

30-31Reserved

GIRQ9 0-3 Reserved 1N/A

4 GPIO104 GPIO Event Yes GPIO Interrupt Event

5 GPIO105 GPIO Event Yes GPIO Interrupt Event

6 GPIO106 GPIO Event Yes GPIO Interrupt Event

7 GPIO107 GPIO Event Yes GPIO Interrupt Event

8-9 Reserved

10 GPIO112 GPIO Event Yes GPIO Interrupt Event

11-15 Reserved

16 GPIO120 GPIO Event Yes GPIO Interrupt Event

17 GPIO121 GPIO Event Yes GPIO Interrupt Event

18 GPIO122 GPIO Event Yes GPIO Interrupt Event

19 GPIO123 GPIO Event Yes GPIO Interrupt Event

 2020 Microchip Technology Inc. DS00003416B-page 35

CEC1712

TABLE 3-3: GIRQ_MAPPING

Agg IRQ

GIRQ10 0-4 Reserved 2N/A

Agg

Bits

20 GPIO124 GPIO Event Yes GPIO Interrupt Event

20 Reserved

21 GPIO125 GPIO Event Yes GPIO Interrupt Event

22 GPIO126 GPIO Event Yes GPIO Interrupt Event

23 GPIO127 GPIO Event Yes GPIO Interrupt Event

24 GPIO130 GPIO Event Yes GPIO Interrupt Event

25 GPIO131 GPIO Event Yes GPIO Interrupt Event

26 GPIO132 GPIO Event Yes GPIO Interrupt Event

27-31Reserved

5 GPIO045 GPIO Event Yes GPIO Interrupt Event

6 GPIO046 GPIO Event Yes GPIO Interrupt Event

7 GPIO047 GPIO Event Yes GPIO Interrupt Event

8 GPIO050 GPIO Event Yes GPIO Interrupt Event

9 GPIO051 GPIO Event Yes GPIO Interrupt Event

10 Reserved

11 GPIO053 GPIO Event Yes GPIO Interrupt Event

12 Reserved

13 GPIO055 GPIO Event Yes GPIO Interrupt Event

14 GPIO056 GPIO Event Yes GPIO Interrupt Event

15 GPIO057 GPIO Event Yes GPIO Interrupt Event

16-18Reserved

HWB

Instance

Name

Interrupt Event

Wake
event

Source description

Agg

NVIC

Direct

NVIC

19 GPIO063 GPIO Event Yes GPIO Interrupt Event

20-23Reserved

24 GPIO070 GPIO Event Yes GPIO Interrupt Event

25 GPIO071 GPIO Event Yes GPIO Interrupt Event

26-31Reserved

GIRQ11 0 GPIO000 GPIO Event Yes GPIO Interrupt Event 3 N/A

1 Reserved

2 GPIO002 GPIO Event Yes GPIO Interrupt Event

3 GPIO003 GPIO Event Yes GPIO Interrupt Event

4 GPIO004 GPIO Event Yes GPIO Interrupt Event

5-9 Reserved

10 GPIO012 GPIO Event Yes GPIO Interrupt Event

11 GPIO013 GPIO Event Yes GPIO Interrupt Event

12 Reserved

13 GPIO015 GPIO Event Yes GPIO Interrupt Event

14 GPIO016 GPIO Event Yes GPIO Interrupt Event

15-17Reserved

DS00003416B-page 36  2020 Microchip Technology Inc.

CEC1712

TABLE 3-3: GIRQ_MAPPING

Agg IRQ

GIRQ12 0 GPIO200 GPIO Event Yes GPIO Interrupt Event 4 N/A

Agg

Bits

16 GPIO020 GPIO Event Yes GPIO Interrupt Event

17 GPIO021 GPIO Event Yes GPIO Interrupt Event

18-21Reserved

22 GPIO026 GPIO Event Yes GPIO Interrupt Event

23 GPIO027 GPIO Event Yes GPIO Interrupt Event

24 GPIO030 GPIO Event Yes GPIO Interrupt Event

25 Reserved

26 GPIO032 GPIO Event Yes GPIO Interrupt Event

27 Reserved

28 GPIO034 GPIO Event Yes GPIO Interrupt Event

29-31Reserved

1 GPIO201 GPIO Event Yes GPIO Interrupt Event

2 GPIO202 GPIO Event Yes GPIO Interrupt Event

3 GPIO203 GPIO Event Yes GPIO Interrupt Event

4 GPIO204 GPIO Event Yes GPIO Interrupt Event

5-18 Reserved

19 GPIO223 GPIO Event Yes GPIO Interrupt Event

20 GPIO224 GPIO Event Yes GPIO Interrupt Event

21-22Reserved

HWB

Instance

Name

Interrupt Event

Wake
event

Source description

Agg

NVIC

Direct

NVIC

23 GPIO227 GPIO Event Yes GPIO Interrupt Event

24-31Reserved

GIRQ13 0 SMB-I2C

Controller0

1SMB-I2C

Controller1

2SMB-I2C

Controller2

3SMB-I2C

Controller3

4SMB-I2C

Controller4

5 I2C Control-

ler5

6 I2C Control-

ler6

7 I2C Control-

ler7

8-31 Reserved

GIRQ14 0 DMA Control-

ler

SMB-I2C No SMB-I2C Controller 0 Interrupt

Event

SMB-I2C No SMB-I2C Controller 1 Interrupt

Event

SMB-I2C No SMB-I2C Controller 2 Interrupt

Event

SMB-I2C No SMB-I2C Controller 3 Interrupt

Event

SMB-I2C No SMB-I2C Controller 4 Interrupt

Event

I2C No Slave I2C Controller 5 Inter-

rupt Event

I2C No Slave I2C Controller 6 Inter-

rupt Event

I2C No Slave I2C Controller 7 Inter-

rupt Event

DMA0 No DMA Controller - Channel 0

Interrupt Event

520

21

22

23

158

168

169

170

624

 2020 Microchip Technology Inc. DS00003416B-page 37

CEC1712

TABLE 3-3: GIRQ_MAPPING

HWB

Instance

Name

ler

ler

ler

ler

ler

ler

ler

ler

ler

ler

ler

Agg IRQ

Agg

Bits

1 DMA Control-

2 DMA Control-

3 DMA Control-

4 DMA Control-

5 DMA Control-

6 DMA Control-

7 DMA Control-

8 DMA Control-

9 DMA Control-

10 DMA Control-

11 DMA Control-

12-31Reserved

Interrupt Event

DMA1 No DMA Controller - Channel 1

DMA2 No DMA Controller - Channel 2

DMA3 No DMA Controller - Channel 3

DMA4 No DMA Controller - Channel 4

DMA5 No DMA Controller - Channel 5

DMA6 No DMA Controller - Channel 6

DMA7 No DMA Controller - Channel 7

DMA8 No DMA Controller - Channel 8

DMA9 No DMA Controller - Channel 9

DMA10 No DMA Controller - Channel 10

DMA11 No DMA Controller - Channel 11

Wake
event

Source description

Interrupt Event

Interrupt Event

Interrupt Event

Interrupt Event

Interrupt Event

Interrupt Event

Interrupt Event

Interrupt Event

Interrupt Event

Interrupt Event

Interrupt Event

Agg

NVIC

Direct

NVIC

25

26

27

28

29

30

31

32

33

34

35

GIRQ15 0 UART 0 UART No UART Interrupt Event 7 40

1 UART 1 UART No UART Interrupt Event 41

2-4 Reserved 42

4 UART2 UART No UART Interrupt Event 44

5-31 Reserved 45

GIRQ17 0 Reserved 70

1 TACH 0 TACH No Tachometer 0 Interrupt Event 71

2 TACH 1 TACH No Tachometer 1 Interrupt Event 72

3-7 Reserved

8ADC Control-

ler

9ADC Control-

ler

10-12Reserved

13 Breathing

LED 0

14 Breathing

LED 1

15-31Reserved

GIRQ18 0 Reserved 10

ADC_Single_Int No ADC Controller - Single-Sam-

ple ADC Conversion Event

ADC_Repeat_Int No ADC Controller - Repeat-Sam-

ple ADC Conversion Event

PWM_WDT No Blinking LED 0 Watchdog

Event

PWM_WDT No Blinking LED 1 Watchdog

Event

78

79

83

84

DS00003416B-page 38  2020 Microchip Technology Inc.

TABLE 3-3: GIRQ_MAPPING

HWB

Instance

Name

SPI Controller

pare Timer

pare Timer

pare Timer

pare Timer

pare Timer

pare Timer

pare Timer

pare Timer

pare Timer

Agg IRQ

Agg

Bits

1 Quad Master

2-19 Reserved

20 Capture Com-

21 Capture Com-

22 Capture Com-

23 Capture Com-

24 Capture Com-

25 Capture Com-

26 Capture Com-

27 Capture Com-

28 Capture Com-

29-31Reserved

CEC1712

Interrupt Event

QMSPI_INT No Master SPI Controller

CAPTURE TIMER No CCT Counter Event 146

CAPTURE 0 No CCT Capture 0 Event 147

CAPTURE 1 No CCT Capture 1 Event 148

CAPTURE 2 No CCT Capture 2 Event 149

CAPTURE 3 No CCT Capture 3 Event 150

CAPTURE 4 No CCT Capture 4 Event 151

CAPTURE 5 No CCT Capture 5 Event 152

COMPARE 0 No CCT Compare 0 Event 153

COMPARE 1 No CCT Compare 1 Event 154

Wake
event

Source description

Requires Servicing

Agg

NVIC

Direct

NVIC

91

GIRQ19 Reserved 11 103

GIRQ20 0-2 Reserved

3 OTP READY_INTR No OTP ready interrupt 173

4-31 Reserved

GIRQ21 0-1 Reserved 13

2 WDT WDT_INT Yes Watch Dog Timer Interupt 171

3 Week Alarm WEEK_ALARM_INT Yes Week Alarm Interrupt. 114

4 Week Alarm SUB-

_WEEK_ALARM_INT

5 Week Alarm ONE_SECOND Yes Week Alarm - One Second

6 Week Alarm SUB_SECOND Yes Week Alarm - Sub-second

7 Week Alarm SYSPWR_PRES Yes System power present pin

8 RTC RTC Yes Real Time Clock Interrupt 119

9 RTC RTC ALARM Yes Real Time Clock Alarm Inter-

10 Reserved

11 VBAT-Pow-

ered Control

Interface

VCI_IN0 Yes VCI_IN0 Active-low Input Pin

Yes Sub-Week Alarm Interrupt 115

116

Interrupt

117

Interrupt

118

interrupt

120

rupt

122

Interrupt

 2020 Microchip Technology Inc. DS00003416B-page 39

CEC1712

TABLE 3-3: GIRQ_MAPPING

Agg IRQ

GIRQ22 0 Reserved N/A N/A

GIRQ23 0 16-Bit Basic

Agg

Bits

14 VBAT-Pow-

15-31Reserved

1 SMB-I2C

2 SMB-I2C

3 SMB-I2C

4 SMB-I2C

5 SMB-I2C

6 I2C Control-

7 I2C Control-

8 I2C Control-

6-31 Reserved

1 16-Bit Basic

2-3 Reserved

4 32-Bit Basic

5 32-Bit Basic

6-9 Reserved

10 RTOS Timer RTOS_TIMER Yes 32-bit RTOS Timer Event 111

11 RTOS Timer SWI_0 No Soft Interrupt request 0

12 RTOS Timer SWI_1 No Soft Interrupt request 1

13 RTOS Timer SWI_2 No Soft Interrupt request 2

14 RTOS Timer SWI_3 No Soft Interrupt request 3

15 Reserved

16 Hibernation

17 Hibernation

HWB

Instance

Name

ered Control

Interface

Controller0

Controller1

Controller2

Controller3

Controller4

ler5

ler6

ler7

Timer 0

Timer 1

Timer 0

Timer 1

Timer0

Timer1

Interrupt Event

VCI_IN3 Yes VCI_IN3 Active-low Input Pin

SMB-I2C _WAKE_ONLY Yes Wake-Only Event (No Interrupt

SMB-I2C _WAKE_ONLY Yes Wake-Only Event (No Interrupt

SMB-I2C _WAKE_ONLY Yes Wake-Only Event (No Interrupt

SMB-I2C _WAKE_ONLY Yes Wake-Only Event (No Interrupt

SMB-I2C _WAKE_ONLY Yes Wake-Only Event (No Interrupt

I2C Yes Slave I2C Controller 5 Wake

I2C Yes Slave I2C Controller 6 Wake

I2C Yes Slave I2C Controller 7 Wake

Timer_16_0 No Basic Timer Event 14 136

Timer_16_1 No Basic Timer Event 137

Timer_32_0 No Basic Timer Event 140

Timer_32_1 No Basic Timer Event 141

HTIMER Yes Hibernation Timer Event 112

HTIMER Yes Hibernation Timer Event 113

Wake
event

Source description

Interrupt

Generated) - SMB-I2C.0

START Detected

Generated) - SMB-I2C.1

START Detected

Generated) - SMB-I2C.2

START Detected

Generated) - SMB-I2C.3

START Detected

Generated) - SMB-I2C.4

START Detected

Event

Event

Event

Agg

NVIC

Direct

NVIC

125

DS00003416B-page 40  2020 Microchip Technology Inc.

CEC1712

TABLE 3-3: GIRQ_MAPPING

Agg IRQ

GIRQ24 Reserved N/A

GIRQ25 Reserved N/A

GIRQ26 0-7 Reserved 17 N/A

Note: Registers and bits associated with GPIOs not implemented are Reserved. Please refer to Section 2.3, "Pin

Agg

Bits

18-31Reserved

8 GPIO250 GPIO Event Yes GPIO Interrupt Event

9-10 Reserved

11 GPIO253 GPIO Event Yes GPIO Interrupt Event

12-31Reserved

List" for GPIOs implemented in the chip.

HWB

Instance

Name

Interrupt Event

Wake
event

Source description

Agg

NVIC

Direct

NVIC

 2020 Microchip Technology Inc. DS00003416B-page 41

CEC1712

3.5 GPIO Register Assignments

All GPIOs except the below come up in default GPIO Input/output/interrupt disabled state. Pin control register defaults

0x00008040.

to

TABLE 3-4: GPIO PIN CONTROL DEFAULT VALUES

GPIO Pin control register value Default function

GPIO000 0x00001040 VCI_IN

GPIO163 0x00001040 VCI_IN

GPIO170 0x00000041 JTAG_STRAP BS (input, pull up)

GPIO250 0x00001240 VCI_OUT

3.6 Register Map

TABLE 3-5: REGISTER MAP

Block Instance Register

Watchdog Timer 0 WDT Load Register 40000400

Watchdog Timer 0 WDT Control Register 40000404

Watchdog Timer 0 WDT Kick Register 40000408

Watchdog Timer 0 WDT Count Register 4000040C

Watchdog Timer 0 WDT Status Register 40000410

Watchdog Timer 0 WDT Interrupt Enable Register 40000414

16-bit Basic Timer 0 Timer Count Register 40000C00

16-bit Basic Timer 0 Timer Preload Register 40000C04

16-bit Basic Timer 0 Timer Status Register 40000C08

16-bit Basic Timer 0 Timer Int Enable Register 40000C0C

16-bit Basic Timer 0 Timer Control Register 40000C10

16-bit Basic Timer 1 Timer Count Register 40000C20

16-bit Basic Timer 1 Timer Preload Register 40000C24

16-bit Basic Timer 1 Timer Status Register 40000C28

16-bit Basic Timer 1 Timer Int Enable Register 40000C2C

16-bit Basic Timer 1 Timer Control Register 40000C30

32-bit Basic Timer 0 Timer Count Register 40000C80

32-bit Basic Timer 0 Timer Preload Register 40000C84

32-bit Basic Timer 0 Timer Status Register 40000C88

32-bit Basic Timer 0 Timer Int Enable Register 40000C8C

32-bit Basic Timer 0 Timer Control Register 40000C90

32-bit Basic Timer 1 Timer Count Register 40000CA0

32-bit Basic Timer 1 Timer Preload Register 40000CA4

32-bit Basic Timer 1 Timer Status Register 40000CA8

32-bit Basic Timer 1 Timer Int Enable Register 40000CAC

32-bit Basic Timer 1 Timer Control Register 40000CB0

Capture Compare Timer 0 Capture and Compare Timer Control Register 40001000

Capture Compare Timer 0 Capture Control 0 Register 40001004

Capture Compare Timer 0 Capture Control 1 Register 40001008

Host
Type

Register
Address

DS00003416B-page 42  2020 Microchip Technology Inc.

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

Capture Compare Timer 0 Free Running Timer Register 4000100C

Capture Compare Timer 0 Capture 0 Register 40001010

Capture Compare Timer 0 Capture 1 Register 40001014

Capture Compare Timer 0 Capture 2 Register 40001018

Capture Compare Timer 0 Capture 3 Register 4000101C

Capture Compare Timer 0 Capture 4 Register 40001020

Capture Compare Timer 0 Capture 5 Register 40001024

Capture Compare Timer 0 Compare 0 Register 40001028

Capture Compare Timer 0 Compare 1 Register 4000102C

Capture Compare Timer 0 ICT Mux Select Register 40001030

DMA Controller 0 DMA Main Control Register 40002400

DMA Controller 0 DMA Data Packet Register 40002404

DMA Controller 0 TEST 40002408

DMA Channel 0 DMA Channel N Activate Register 40002440

DMA Channel 0 DMA Channel N Memory Start Address Register 40002444

DMA Channel 0 DMA Channel N Memory End Address Register 40002448

DMA Channel 0 DMA Channel N Device Address 4000244C

DMA Channel 0 DMA Channel N Control Register 40002450

DMA Channel 0 DMA Channel N Interrupt Status Register 40002454

DMA Channel 0 DMA Channel N Interrupt Enable Register 40002458

DMA Channel 0 TEST 4000245C

DMA Channel 0 Channel N CRC Enable Register 40002460

DMA Channel 0 Channel N CRC Data Register 40002464

DMA Channel 0 Channel N CRC Post Status Register 40002468

DMA Channel 0 TEST 4000246C

DMA Channel 1 DMA Channel N Activate Register 40002480

DMA Channel 1 DMA Channel N Memory Start Address Register 40002484

DMA Channel 1 DMA Channel N Memory End Address Register 40002488

DMA Channel 1 DMA Channel N Device Address 4000248C

DMA Channel 1 DMA Channel N Control Register 40002490

DMA Channel 1 DMA Channel N Interrupt Status Register 40002494

DMA Channel 1 DMA Channel N Interrupt Enable Register 40002498

DMA Channel 1 TEST 4000249C

DMA Channel 1 Channel N Fill Enable Register 400024A0

DMA Channel 1 Channel N Fill Data Register 400024A4

DMA Channel 1 Channel N Fill Status Register 400024A8

DMA Channel 1 TEST 400024AC

DMA Channel 2 DMA Channel N Activate Register 400024C0

DMA Channel 2 DMA Channel N Memory Start Address Register 400024C4

DMA Channel 2 DMA Channel N Memory End Address Register 400024C8

DMA Channel 2 DMA Channel N Device Address 400024CC

DMA Channel 2 DMA Channel N Control Register 400024D0

DMA Channel 2 DMA Channel N Interrupt Status Register 400024D4

DMA Channel 2 DMA Channel N Interrupt Enable Register 400024D8

Host
Type

Register
Address

 2020 Microchip Technology Inc. DS00003416B-page 43

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

DMA Channel 2 TEST 400024DC

DMA Channel 3 DMA Channel N Activate Register 40002500

DMA Channel 3 DMA Channel N Memory Start Address Register 40002504

DMA Channel 3 DMA Channel N Memory End Address Register 40002508

DMA Channel 3 DMA Channel N Device Address 4000250C

DMA Channel 3 DMA Channel N Control Register 40002510

DMA Channel 3 DMA Channel N Interrupt Status Register 40002514

DMA Channel 3 DMA Channel N Interrupt Enable Register 40002518

DMA Channel 3 TEST 4000251C

DMA Channel 4 DMA Channel N Activate Register 40002540

DMA Channel 4 DMA Channel N Memory Start Address Register 40002544

DMA Channel 4 DMA Channel N Memory End Address Register 40002548

DMA Channel 4 DMA Channel N Device Address 4000254C

DMA Channel 4 DMA Channel N Control Register 40002550

DMA Channel 4 DMA Channel N Interrupt Status Register 40002554

DMA Channel 4 DMA Channel N Interrupt Enable Register 40002558

DMA Channel 4 TEST 4000255C

DMA Channel 5 DMA Channel N Activate Register 40002580

DMA Channel 5 DMA Channel N Memory Start Address Register 40002584

DMA Channel 5 DMA Channel N Memory End Address Register 40002588

DMA Channel 5 DMA Channel N Device Address 4000258C

DMA Channel 5 DMA Channel N Control Register 40002590

DMA Channel 5 DMA Channel N Interrupt Status Register 40002594

DMA Channel 5 DMA Channel N Interrupt Enable Register 40002598

DMA Channel 5 TEST 4000259C

DMA Channel 6 DMA Channel N Activate Register 400025C0

DMA Channel 6 DMA Channel N Memory Start Address Register 400025C4

DMA Channel 6 DMA Channel N Memory End Address Register 400025C8

DMA Channel 6 DMA Channel N Device Address 400025CC

DMA Channel 6 DMA Channel N Control Register 400025D0

DMA Channel 6 DMA Channel N Interrupt Status Register 400025D4

DMA Channel 6 DMA Channel N Interrupt Enable Register 400025D8

DMA Channel 6 TEST 400025DC

DMA Channel 7 DMA Channel N Activate Register 40002600

DMA Channel 7 DMA Channel N Memory Start Address Register 40002604

DMA Channel 7 DMA Channel N Memory End Address Register 40002608

DMA Channel 7 DMA Channel N Device Address 4000260C

DMA Channel 7 DMA Channel N Control Register 40002610

DMA Channel 7 DMA Channel N Interrupt Status Register 40002614

DMA Channel 7 DMA Channel N Interrupt Enable Register 40002618

DMA Channel 7 TEST 4000261C

DMA Channel 8 DMA Channel N Activate Register 40002640

DMA Channel 8 DMA Channel N Memory Start Address Register 40002644

DMA Channel 8 DMA Channel N Memory End Address Register 40002648

Host
Type

Register
Address

DS00003416B-page 44  2020 Microchip Technology Inc.

TABLE 3-5: REGISTER MAP

Block Instance Register

DMA Channel 8 DMA Channel N Device Address 4000264C

DMA Channel 8 DMA Channel N Control Register 40002650

DMA Channel 8 DMA Channel N Interrupt Status Register 40002654

DMA Channel 8 DMA Channel N Interrupt Enable Register 40002658

DMA Channel 8 TEST 4000265C

DMA Channel 9 DMA Channel N Activate Register 40002680

DMA Channel 9 DMA Channel N Memory Start Address Register 40002684

DMA Channel 9 DMA Channel N Memory End Address Register 40002688

DMA Channel 9 DMA Channel N Device Address 4000268C

DMA Channel 9 DMA Channel N Control Register 40002690

DMA Channel 9 DMA Channel N Interrupt Status Register 40002694

DMA Channel 9 DMA Channel N Interrupt Enable Register 40002698

DMA Channel 9 TEST 4000269C

DMA Channel 10 DMA Channel N Activate Register 400026C0

DMA Channel 10 DMA Channel N Memory Start Address Register 400026C4

DMA Channel 10 DMA Channel N Memory End Address Register 400026C8

DMA Channel 10 DMA Channel N Device Address 400026CC

DMA Channel 10 DMA Channel N Control Register 400026D0

DMA Channel 10 DMA Channel N Interrupt Status Register 400026D4

DMA Channel 10 DMA Channel N Interrupt Enable Register 400026D8

DMA Channel 10 TEST 400026DC

DMA Channel 11 DMA Channel N Activate Register 40002700

DMA Channel 11 DMA Channel N Memory Start Address Register 40002704

DMA Channel 11 DMA Channel N Memory End Address Register 40002708

DMA Channel 11 DMA Channel N Device Address 4000270C

DMA Channel 11 DMA Channel N Control Register 40002710

DMA Channel 11 DMA Channel N Interrupt Status Register 40002714

DMA Channel 11 DMA Channel N Interrupt Enable Register 40002718

DMA Channel 11 TEST 4000271C

I2C-SMB 0 Control Register 40004000

I2C-SMB 0 Status Register 40004000

I2C-SMB 0 Own Address Register 40004004

I2C-SMB 0 Data Register 40004008

I2C-SMB 0 Master Command Register 4000400C

I2C-SMB 0 Slave Command Register 40004010

I2C-SMB 0 PEC Register 40004014

I2C-SMB 0 Repeated START Hold Time Register 40004018

I2C-SMB 0 Completion Register 40004020

I2C-SMB 0 Idle Scaling Register 40004024

I2C-SMB 0 Configuration Register 40004028

I2C-SMB 0 Bus Clock Register 4000402C

I2C-SMB 0 Block ID Register 40004030

I2C-SMB 0 Revision Register 40004034

I2C-SMB 0 Bit-Bang Control Register 40004038

CEC1712

Host
Type

Register
Address

 2020 Microchip Technology Inc. DS00003416B-page 45

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

I2C-SMB 0 TEST 4000403C

I2C-SMB 0 Data Timing Register 40004040

I2C-SMB 0 Time-Out Scaling Register 40004044

I2C-SMB 0 Slave Transmit Buffer Register 40004048

I2C-SMB 0 Slave Receive Buffer Register 4000404C

I2C-SMB 0 Master Transmit Buffer Register 40004050

I2C-SMB 0 Master Receive Buffer Register 40004054

I2C-SMB 0 TEST 40004058

I2C-SMB 0 TEST 4000405C

I2C-SMB 0 Wake Status Register 40004060

I2C-SMB 0 Wake Enable Register 40004064

I2C-SMB 0 TEST 40004068

I2C-SMB 0 Slave address 4000406C

I2C-SMB 0 Promiscuous Interrupt 40004070

I2C-SMB 0 Promiscuous Interrupt Enable 40004074

I2C-SMB 0 Promiscuous Control 40004078

I2C-SMB 1 Control Register 40004400

I2C-SMB 1 Status Register 40004400

I2C-SMB 1 Own Address Register 40004404

I2C-SMB 1 Data Register 40004408

I2C-SMB 1 Master Command Register 4000440C

I2C-SMB 1 Slave Command Register 40004410

I2C-SMB 1 PEC Register 40004414

I2C-SMB 1 Repeated START Hold Time Register 40004418

I2C-SMB 1 Completion Register 40004420

I2C-SMB 1 Idle Scaling Register 40004424

I2C-SMB 1 Configuration Register 40004428

I2C-SMB 1 Bus Clock Register 4000442C

I2C-SMB 1 Block ID Register 40004430

I2C-SMB 1 Revision Register 40004434

I2C-SMB 1 Bit-Bang Control Register 40004438

I2C-SMB 1 TEST 4000443C

I2C-SMB 1 Data Timing Register 40004440

I2C-SMB 1 Time-Out Scaling Register 40004444

I2C-SMB 1 Slave Transmit Buffer Register 40004448

I2C-SMB 1 Slave Receive Buffer Register 4000444C

I2C-SMB 1 Master Transmit Buffer Register 40004450

I2C-SMB 1 Master Receive Buffer Register 40004454

I2C-SMB 1 TEST 40004458

I2C-SMB 1 TEST 4000445C

I2C-SMB 1 Wake Status Register 40004460

I2C-SMB 1 Wake Enable Register 40004464

I2C-SMB 1 TEST 40004468

I2C-SMB 1 Slave address 4000446C

Host
Type

Register
Address

DS00003416B-page 46  2020 Microchip Technology Inc.

TABLE 3-5: REGISTER MAP

Block Instance Register

I2C-SMB 1 Promiscuous Interrupt 40004470

I2C-SMB 1 Promiscuous Interrupt Enable 40004474

I2C-SMB 1 Promiscuous Control 40004478

I2C-SMB 2 Control Register 40004800

I2C-SMB 2 Status Register 40004800

I2C-SMB 2 Own Address Register 40004804

I2C-SMB 2 Data Register 40004808

I2C-SMB 2 Master Command Register 4000480C

I2C-SMB 2 Slave Command Register 40004810

I2C-SMB 2 PEC Register 40004814

I2C-SMB 2 Repeated START Hold Time Register 40004818

I2C-SMB 2 Completion Register 40004820

I2C-SMB 2 Idle Scaling Register 40004824

I2C-SMB 2 Configuration Register 40004828

I2C-SMB 2 Bus Clock Register 4000482C

I2C-SMB 2 Block ID Register 40004830

I2C-SMB 2 Revision Register 40004834

I2C-SMB 2 Bit-Bang Control Register 40004838

I2C-SMB 2 TEST 4000483C

I2C-SMB 2 Data Timing Register 40004840

I2C-SMB 2 Time-Out Scaling Register 40004844

I2C-SMB 2 Slave Transmit Buffer Register 40004848

I2C-SMB 2 Slave Receive Buffer Register 4000484C

I2C-SMB 2 Master Transmit Buffer Register 40004850

I2C-SMB 2 Master Receive Buffer Register 40004854

I2C-SMB 2 TEST 40004858

I2C-SMB 2 TEST 4000485C

I2C-SMB 2 Wake Status Register 40004860

I2C-SMB 2 Wake Enable Register 40004864

I2C-SMB 2 TEST 40004868

I2C-SMB 2 Slave address 4000486C

I2C-SMB 2 Promiscuous Interrupt 40004870

I2C-SMB 2 Promiscuous Interrupt Enable 40004874

I2C-SMB 2 Promiscuous Control 40004878

I2C-SMB 3 Control Register 40004C00

I2C-SMB 3 Status Register 40004C00

I2C-SMB 3 Own Address Register 40004C04

I2C-SMB 3 Data Register 40004C08

I2C-SMB 3 Master Command Register 40004C0C

I2C-SMB 3 Slave Command Register 40004C10

I2C-SMB 3 PEC Register 40004C14

I2C-SMB 3 Repeated START Hold Time Register 40004C18

I2C-SMB 3 Completion Register 40004C20

I2C-SMB 3 Idle Scaling Register 40004C24

CEC1712

Host
Type

Register
Address

 2020 Microchip Technology Inc. DS00003416B-page 47

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

I2C-SMB 3 Configuration Register 40004C28

I2C-SMB 3 Bus Clock Register 40004C2C

I2C-SMB 3 Block ID Register 40004C30

I2C-SMB 3 Revision Register 40004C34

I2C-SMB 3 Bit-Bang Control Register 40004C38

I2C-SMB 3 TEST 40004C3C

I2C-SMB 3 Data Timing Register 40004C40

I2C-SMB 3 Time-Out Scaling Register 40004C44

I2C-SMB 3 Slave Transmit Buffer Register 40004C48

I2C-SMB 3 Slave Receive Buffer Register 40004C4C

I2C-SMB 3 Master Transmit Buffer Register 40004C50

I2C-SMB 3 Master Receive Buffer Register 40004C54

I2C-SMB 3 TEST 40004C58

I2C-SMB 3 TEST 40004C5C

I2C-SMB 3 Wake Status Register 40004C60

I2C-SMB 3 Wake Enable Register 40004C64

I2C-SMB 3 TEST 40004C68

I2C-SMB 3 Slave address 40004C6C

I2C-SMB 3 Promiscuous Interrupt 40004C70

I2C-SMB 3 Promiscuous Interrupt Enable 40004C74

I2C-SMB 3 Promiscuous Control 40004C78

I2C-SMB 4 Control Register 40005000

I2C-SMB 4 Status Register 40005000

I2C-SMB 4 Own Address Register 40005004

I2C-SMB 4 Data Register 40005008

I2C-SMB 4 Master Command Register 4000500C

I2C-SMB 4 Slave Command Register 40005010

I2C-SMB 4 PEC Register 40005014

I2C-SMB 4 Repeated START Hold Time Register 40005018

I2C-SMB 4 Completion Register 40005020

I2C-SMB 4 Idle Scaling Register 40005024

I2C-SMB 4 Configuration Register 40005028

I2C-SMB 4 Bus Clock Register 4000502C

I2C-SMB 4 Block ID Register 40005030

I2C-SMB 4 Revision Register 40005034

I2C-SMB 4 Bit-Bang Control Register 40005038

I2C-SMB 4 TEST 4000503C

I2C-SMB 4 Data Timing Register 40005040

I2C-SMB 4 Time-Out Scaling Register 40005044

I2C-SMB 4 Slave Transmit Buffer Register 40005048

I2C-SMB 4 Slave Receive Buffer Register 4000504C

I2C-SMB 4 Master Transmit Buffer Register 40005050

I2C-SMB 4 Master Receive Buffer Register 40005054

I2C-SMB 4 TEST 40005058

Host
Type

Register
Address

DS00003416B-page 48  2020 Microchip Technology Inc.

TABLE 3-5: REGISTER MAP

Block Instance Register

I2C-SMB 4 TEST 4000505C

I2C-SMB 4 Wake Status Register 40005060

I2C-SMB 4 Wake Enable Register 40005064

I2C-SMB 4 TEST 40005068

I2C-SMB 4 Slave address 4000506C

I2C-SMB 4 Promiscuous Interrupt 40005070

I2C-SMB 4 Promiscuous Interrupt Enable 40005074

I2C-SMB 4 Promiscuous Control 40005078

I2C 0 Control Register 40005100

I2C 0 Status Register 40005100

I2C 0 Own Address Register 40005104

I2C 0 Data Register 40005108

I2C 0 Repeated START Hold Time Register 40005118

I2C 0 Completion Register 40005120

I2C 0 Configuration Register 40005128

I2C 0 Bus Clock Register 4000512C

I2C 0 Block ID Register 40005130

I2C 0 Revision Register 40005134

I2C 0 Bit-Bang Control Register 40005138

I2C 0 TEST 4000513C

I2C 0 Data Timing Register 40005140

I2C 0 Time-Out Scaling Register 40005144

I2C 0 TEST 40005158

I2C 0 TEST 4000515C

I2C 0 Wake Status Register 40005160

I2C 0 Wake Enable Register 40005164

I2C 0 TEST 40005168

I2C 0 Slave address 4000516C

I2C 0 Promiscuous Interrupt 40005170

I2C 0 Promiscuous Interrupt Enable 40005174

I2C 0 Promiscuous Control 40005178

I2C 1 Control Register 40005200

I2C 1 Status Register 40005200

I2C 1 Own Address Register 40005204

I2C 1 Data Register 40005208

I2C 1 Repeated START Hold Time Register 40005218

I2C 1 Completion Register 40005220

I2C 1 Configuration Register 40005228

I2C 1 Bus Clock Register 4000522C

I2C 1 Block ID Register 40005230

I2C 1 Revision Register 40005234

I2C 1 Bit-Bang Control Register 40005238

I2C 1 TEST 4000523C

I2C 1 Data Timing Register 40005240

CEC1712

Host
Type

Register
Address

 2020 Microchip Technology Inc. DS00003416B-page 49

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

I2C 1 Time-Out Scaling Register 40005244

I2C 1 TEST 40005258

I2C 1 TEST 4000525C

I2C 1 Wake Status Register 40005260

I2C 1 Wake Enable Register 40005264

I2C 1 TEST 40005268

I2C 1 Slave address 4000526C

I2C 1 Promiscuous Interrupt 40005270

I2C 1 Promiscuous Interrupt Enable 40005274

I2C 1 Promiscuous Control 40005278

I2C 2 Control Register 40005300

I2C 2 Status Register 40005300

I2C 2 Own Address Register 40005304

I2C 2 Data Register 40005308

I2C 2 Repeated START Hold Time Register 40005318

I2C 2 Completion Register 40005320

I2C 2 Configuration Register 40005328

I2C 2 Bus Clock Register 4000532C

I2C 2 Block ID Register 40005330

I2C 2 Revision Register 40005334

I2C 2 Bit-Bang Control Register 40005338

I2C 2 TEST 4000533C

I2C 2 Data Timing Register 40005340

I2C 2 Time-Out Scaling Register 40005344

I2C 2 TEST 40005358

I2C 2 TEST 4000535C

I2C 2 Wake Status Register 40005360

I2C 2 Wake Enable Register 40005364

I2C 2 TEST 40005368

I2C 2 Slave address 4000536C

I2C 2 Promiscuous Interrupt 40005370

I2C 2 Promiscuous Interrupt Enable 40005374

I2C 2 Promiscuous Control 40005378

QMSPI 0 QMSPI Mode Register 40070000

QMSPI 0 QMSPI Control Register 40070004

QMSPI 0 QMSPI Execute Register 40070008

QMSPI 0 QMSPI Interface Control Register 4007000C

QMSPI 0 QMSPI Status Register 40070010

QMSPI 0 QMSPI Buffer Count Status Register 40070014

QMSPI 0 QMSPI Interrupt Enable Register 40070018

QMSPI 0 QMSPI Buffer Count Trigger Register 4007001C

QMSPI 0 QMSPI Transmit Buffer Register 40070020

QMSPI 0 QMSPI Receive Buffer Register 40070024

QMSPI 0 QMSPI Chip Select Timing Register 40070028

Host
Type

Register
Address

DS00003416B-page 50  2020 Microchip Technology Inc.

TABLE 3-5: REGISTER MAP

Block Instance Register

QMSPI 0 QMSPI Description Buffer 0 Register 40070030

QMSPI 0 QMSPI Description Buffer 1 Register 40070034

QMSPI 0 QMSPI Description Buffer 2 Register 40070038

QMSPI 0 QMSPI Description Buffer 3 Register 4007003C

QMSPI 0 QMSPI Description Buffer 4 Register 40070040

QMSPI 0 QMSPI Description Buffer 5 Register 40070044

QMSPI 0 QMSPI Description Buffer 6 Register 40070048

QMSPI 0 QMSPI Description Buffer 7 Register 4007004C

QMSPI 0 QMSPI Description Buffer 8 Register 40070050

QMSPI 0 QMSPI Description Buffer 9 Register 40070054

QMSPI 0 QMSPI Description Buffer 10 Register 40070058

QMSPI 0 QMSPI Description Buffer 11 Register 4007005C

QMSPI 0 QMSPI Description Buffer 12 Register 40070060

QMSPI 0 QMSPI Description Buffer 13 Register 40070064

QMSPI 0 QMSPI Description Buffer 14 Register 40070068

QMSPI 0 QMSPI Description Buffer 15 Register 4007006C

16-bit PWM 0 PWMx Counter ON Time Register 40005800

16-bit PWM 0 PWMx Counter OFF Time Register 40005804

16-bit PWM 0 PWMx Configuration Register 40005808

16-bit PWM 0 TEST 4000580C

16-bit PWM 2 PWMx Counter ON Time Register 40005820

16-bit PWM 2 PWMx Counter OFF Time Register 40005824

16-bit PWM 2 PWMx Configuration Register 40005828

16-bit PWM 2 TEST 4000582C

16-bit PWM 3 PWMx Counter ON Time Register 40005830

16-bit PWM 3 PWMx Counter OFF Time Register 40005834

16-bit PWM 3 PWMx Configuration Register 40005838

16-bit PWM 3 TEST 4000583C

16-bit PWM 5 PWMx Counter ON Time Register 40005850

16-bit PWM 5 PWMx Counter OFF Time Register 40005854

16-bit PWM 5 PWMx Configuration Register 40005858

16-bit PWM 5 TEST 4000585C

16-bit PWM 6 PWMx Counter ON Time Register 40005860

16-bit PWM 6 PWMx Counter OFF Time Register 40005864

16-bit PWM 6 PWMx Configuration Register 40005868

16-bit PWM 6 TEST 4000586C

16-bit PWM 7 PWMx Counter ON Time Register 40005870

16-bit PWM 7 PWMx Counter OFF Time Register 40005874

16-bit PWM 7 PWMx Configuration Register 40005878

16-bit PWM 7 TEST 4000587C

16-bit Tach 0 TACHx Control Register 40006000

16-bit Tach 0 TACHx Status Register 40006004

16-bit Tach 0 TACHx High Limit Register 40006008

16-bit Tach 0 TACHx Low Limit Register 4000600C

CEC1712

Host
Type

Register
Address

 2020 Microchip Technology Inc. DS00003416B-page 51

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

16-bit Tach 1 TACHx Control Register 40006010

16-bit Tach 1 TACHx Status Register 40006014

16-bit Tach 1 TACHx High Limit Register 40006018

16-bit Tach 1 TACHx Low Limit Register 4000601C

RTOS Timer 0 RTOS Timer Count Register 40007400

RTOS Timer 0 RTOS Timer Preload Register 40007404

RTOS Timer 0 RTOS Timer Control Register 40007408

RTOS Timer 0 Soft Interrupt Register 4000740C

ADC 0 ADC Control Register 40007C00

ADC 0 ADC Delay Register 40007C04

ADC 0 ADC Status Register 40007C08

ADC 0 ADC Single Register 40007C0C

ADC 0 ADC Repeat Register 40007C10

ADC 0 ADC Channel 0 Reading Register 40007C14

ADC 0 ADC Channel 1 Reading Register 40007C18

ADC 0 ADC Channel 2 Reading Register 40007C1C

ADC 0 ADC Channel 3 Reading Register 40007C20

ADC 0 ADC Channel 4 Reading Register 40007C24

ADC 0 ADC Channel 5 Reading Register 40007C28

ADC 0 ADC Channel 6 Reading Register 40007C2C

ADC 0 ADC Channel 7 Reading Register 40007C30

ADC 0 ADC Channel 8 Reading Register 40007C34

ADC 0 ADC Channel 9 Reading Register 40007C38

ADC 0 ADC Channel 10 Reading Register 40007C3C

ADC 0 ADC Channel 11 Reading Register 40007C40

ADC 0 ADC Configuration Register 40007C7C

ADC 0 VREF Channel Register 40007C80

ADC 0 VREF Control Register 40007C84

ADC 0 SAR ADC Control Register 40007C88

ADC 0 SAR ADC Config Register 40007C8C

TFDP 0 Debug Data Register 40008C00

TFDP 0 Debug Control Register 40008C04

Hibernation Timer 0 HTimer Preload Register 40009800

Hibernation Timer 0 HTimer Control Register 40009804

Hibernation Timer 0 HTimer Count Register 40009808

Hibernation Timer 1 HTimer Preload Register 40009820

Hibernation Timer 1 HTimer Control Register 40009824

Hibernation Timer 1 HTimer Count Register 40009828

VBAT Register Bank 0 Power-Fail and Reset Status Register 4000A400

VBAT Register Bank 0 TEST 4000A404

VBAT Register Bank 0 Clock Enable Register 4000A408

VBAT Register Bank 0 TEST 4000A40C

VBAT Register Bank 0 TEST 4000A410

VBAT Register Bank 0 TEST 4000A414

Host
Type

Register
Address

DS00003416B-page 52  2020 Microchip Technology Inc.

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

VBAT Register Bank 0 TEST 4000A41C

VBAT Register Bank 0 Monotonic Counter Register 4000A420

VBAT Register Bank 0 Counter HiWord Register 4000A424

VBAT Register Bank 0 TEST 4000A428

VBAT Register Bank 0 TEST 4000A42C

VBAT Powered RAM 0 Registers 4000A800

Week Timer 0 Control Register 4000AC80

Week Timer 0 Week Alarm Counter Register 4000AC84

Week Timer 0 Week Timer Compare Register 4000AC88

Week Timer 0 Clock Divider Register 4000AC8C

Week Timer 0 Sub-Second Programmable Interrupt Select Register 4000AC90

Week Timer 0 Sub-Week Control Register 4000AC94

Week Timer 0 Sub-Week Alarm Counter Register 4000AC98

Week Timer 0 BGPO Data Register 4000AC9C

Week Timer 0 BGPO Power Register 4000ACA0

Week Timer 0 BGPO Reset Register 4000ACA4

VBAT-Powered Control

Interface

VBAT-Powered Control

Interface

VBAT-Powered Control

Interface

VBAT-Powered Control

Interface

VBAT-Powered Control

Interface

VBAT-Powered Control

Interface

VBAT-Powered Control

Interface

VBAT-Powered Control

Interface

VBAT-Powered Control

Interface

Blinking-Breathing PWM 0 LED Configuration Register 4000B800

Blinking-Breathing PWM 0 LED Limits Register 4000B804

Blinking-Breathing PWM 0 LED Delay Register 4000B808

Blinking-Breathing PWM 0 LED Update Stepsize Register 4000B80C

Blinking-Breathing PWM 0 LED Update Interval Register 4000B810

Blinking-Breathing PWM 0 LED Output Delay 4000B814

Blinking-Breathing PWM 1 LED Configuration Register 4000B900

Blinking-Breathing PWM 1 LED Limits Register 4000B904

Blinking-Breathing PWM 1 LED Delay Register 4000B908

Blinking-Breathing PWM 1 LED Update Stepsize Register 4000B90C

Blinking-Breathing PWM 1 LED Update Interval Register 4000B910

Blinking-Breathing PWM 1 LED Output Delay 4000B914

0 VCI Register 4000AE00

0 Latch Enable Register 4000AE04

0 Latch Resets Register 4000AE08

0 VCI Input Enable Register 4000AE0C

0 Holdoff Count Register 4000AE10

0 VCI Polarity Register 4000AE14

0 VCI Posedge Detect Register 4000AE18

0 VCI Negedge Detect Register 4000AE1C

0 VCI Buffer Enable Register 4000AE20

Host
Type

Register
Address

 2020 Microchip Technology Inc. DS00003416B-page 53

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

Interrupt Aggregator 0 GIRQ8 Source Register 4000E000

Interrupt Aggregator 0 GIRQ8 Enable Set Register 4000E004

Interrupt Aggregator 0 GIRQ8 Result Register 4000E008

Interrupt Aggregator 0 GIRQ8 Enable Clear Register 4000E00C

Interrupt Aggregator 0 GIRQ9 Source Register 4000E014

Interrupt Aggregator 0 GIRQ9 Enable Set Register 4000E018

Interrupt Aggregator 0 GIRQ9 Result Register 4000E01C

Interrupt Aggregator 0 GIRQ9 Enable Clear Register 4000E020

Interrupt Aggregator 0 GIRQ10 Source Register 4000E028

Interrupt Aggregator 0 GIRQ10 Enable Set Register 4000E02C

Interrupt Aggregator 0 GIRQ10 Result Register 4000E030

Interrupt Aggregator 0 GIRQ10 Enable Clear Register 4000E034

Interrupt Aggregator 0 GIRQ11 Source Register 4000E03C

Interrupt Aggregator 0 GIRQ11 Enable Set Register 4000E040

Interrupt Aggregator 0 GIRQ11 Result Register 4000E044

Interrupt Aggregator 0 GIRQ11 Enable Clear Register 4000E048

Interrupt Aggregator 0 GIRQ12 Source Register 4000E050

Interrupt Aggregator 0 GIRQ12 Enable Set Register 4000E054

Interrupt Aggregator 0 GIRQ12 Result Register 4000E058

Interrupt Aggregator 0 GIRQ12 Enable Clear Register 4000E05C

Interrupt Aggregator 0 GIRQ13 Source Register 4000E064

Interrupt Aggregator 0 GIRQ13 Enable Set Register 4000E068

Interrupt Aggregator 0 GIRQ13 Result Register 4000E06C

Interrupt Aggregator 0 GIRQ13 Enable Clear Register 4000E070

Interrupt Aggregator 0 GIRQ14 Source Register 4000E078

Interrupt Aggregator 0 GIRQ14 Enable Set Register 4000E07C

Interrupt Aggregator 0 GIRQ14 Result Register 4000E080

Interrupt Aggregator 0 GIRQ14 Enable Clear Register 4000E084

Interrupt Aggregator 0 GIRQ15 Source Register 4000E08C

Interrupt Aggregator 0 GIRQ15 Enable Set Register 4000E090

Interrupt Aggregator 0 GIRQ15 Result Register 4000E094

Interrupt Aggregator 0 GIRQ15 Enable Clear Register 4000E098

Interrupt Aggregator 0 GIRQ16 Source Register 4000E0A0

Interrupt Aggregator 0 GIRQ16 Enable Set Register 4000E0A4

Interrupt Aggregator 0 GIRQ16 Result Register 4000E0A8

Interrupt Aggregator 0 GIRQ16 Enable Clear Register 4000E0AC

Interrupt Aggregator 0 GIRQ17 Source Register 4000E0B4

Interrupt Aggregator 0 GIRQ17 Enable Set Register 4000E0B8

Interrupt Aggregator 0 GIRQ17 Result Register 4000E0BC

Interrupt Aggregator 0 GIRQ17 Enable Clear Register 4000E0C0

Interrupt Aggregator 0 GIRQ18 Source Register 4000E0C8

Interrupt Aggregator 0 GIRQ18 Enable Set Register 4000E0CC

Interrupt Aggregator 0 GIRQ18 Result Register 4000E0D0

Interrupt Aggregator 0 GIRQ18 Enable Clear Register 4000E0D4

Host
Type

Register
Address

DS00003416B-page 54  2020 Microchip Technology Inc.

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

Interrupt Aggregator 0 GIRQ19 Source Register 4000E0DC

Interrupt Aggregator 0 GIRQ19 Enable Set Register 4000E0E0

Interrupt Aggregator 0 GIRQ19 Result Register 4000E0E4

Interrupt Aggregator 0 GIRQ19 Enable Clear Register 4000E0E8

Interrupt Aggregator 0 GIRQ20 Source Register 4000E0F0

Interrupt Aggregator 0 GIRQ20 Enable Set Register 4000E0F4

Interrupt Aggregator 0 GIRQ20 Result Register 4000E0F8

Interrupt Aggregator 0 GIRQ20 Enable Clear Register 4000E0FC

Interrupt Aggregator 0 GIRQ21 Source Register 4000E104

Interrupt Aggregator 0 GIRQ21 Enable Set Register 4000E108

Interrupt Aggregator 0 GIRQ21 Result Register 4000E10C

Interrupt Aggregator 0 GIRQ21 Enable Clear Register 4000E110

Interrupt Aggregator 0 GIRQ22 Source Register 4000E118

Interrupt Aggregator 0 GIRQ22 Enable Set Register 4000E11C

Interrupt Aggregator 0 GIRQ22 Result Register 4000E120

Interrupt Aggregator 0 GIRQ22 Enable Clear Register 4000E124

Interrupt Aggregator 0 GIRQ23 Source Register 4000E12C

Interrupt Aggregator 0 GIRQ23 Enable Set Register 4000E130

Interrupt Aggregator 0 GIRQ23 Result Register 4000E134

Interrupt Aggregator 0 GIRQ23 Enable Clear Register 4000E138

Interrupt Aggregator 0 GIRQ24 Source Register 4000E140

Interrupt Aggregator 0 GIRQ24 Enable Set Register 4000E144

Interrupt Aggregator 0 GIRQ24 Result Register 4000E148

Interrupt Aggregator 0 GIRQ24 Enable Clear Register 4000E14C

Interrupt Aggregator 0 GIRQ25 Source Register 4000E154

Interrupt Aggregator 0 GIRQ25 Enable Set Register 4000E158

Interrupt Aggregator 0 GIRQ25 Result Register 4000E15C

Interrupt Aggregator 0 GIRQ25 Enable Clear Register 4000E160

Interrupt Aggregator 0 GIRQ26 Source Register 4000E168

Interrupt Aggregator 0 GIRQ26 Enable Set Register 4000E16C

Interrupt Aggregator 0 GIRQ26 Result Register 4000E170

Interrupt Aggregator 0 GIRQ26 Enable Clear Register 4000E174

Interrupt Aggregator 0 Block Enable Set Register 4000E200

Interrupt Aggregator 0 Block Enable Clear Register 4000E204

Interrupt Aggregator 0 Block IRQ Vector Register 4000E208

EC Register Bank 0 TEST 4000FC00

EC Register Bank 0 AHB Error Address Register 4000FC04

EC Register Bank 0 TEST 4000FC08

EC Register Bank 0 TEST 4000FC0C

EC Register Bank 0 TEST 4000FC10

EC Register Bank 0 AHB Error Control Register 4000FC14

EC Register Bank 0 Interrupt Control Register 4000FC18

EC Register Bank 0 ETM TRACE Enable Register 4000FC1C

EC Register Bank 0 Debug Enable Register 4000FC20

Host
Type

Register
Address

 2020 Microchip Technology Inc. DS00003416B-page 55

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

EC Register Bank 0 TEST 4000FC24

EC Register Bank 0 WDT Event Count Register 4000FC28

EC Register Bank 0 PECI DISABLE Register 4000FC40

EC Register Bank 0 TEST 4000FC44

EC Register Bank 0 TEST 4000FC48

EC Register Bank 0 TEST 4000FC4C

EC Register Bank 0 TEST 4000FC60

EC Register Bank 0 GPIO Bank Power Register 4000FC64

EC Register Bank 0 TEST 4000FC68

EC Register Bank 0 TEST 4000FC6C

EC Register Bank 0 Vwire FW Override Register 4000FC90

EC Register Bank 0 Other IP trim Register 4000FCF0

EC Register Bank 0 TEST 4000FD00

EC Register Bank 0 FW Scratch Register0 4000FD80

EC Register Bank 0 FW Scratch Register1 4000FD84

EC Register Bank 0 FW Scratch Register2 4000FD88

EC Register Bank 0 FW Scratch Register3 4000FD8C

Power Clocks and Resets 0 System Sleep Control Register 40080100

Power Clocks and Resets 0 Processor Clock Control Register 40080104

Power Clocks and Resets 0 Slow Clock Control Register 40080108

Power Clocks and Resets 0 Oscillator ID Register 4008010C

Power Clocks and Resets 0 PCR Power Reset Status Register 40080110

Power Clocks and Resets 0 Power Reset Control Register 40080114

Power Clocks and Resets 0 System Reset Register 40080118

Power Clocks and Resets 0 TEST 4008011C

Power Clocks and Resets 0 TEST 40080120

Power Clocks and Resets 0 Sleep Enable 0 Register 40080130

Power Clocks and Resets 0 Sleep Enable 1 Register 40080134

Power Clocks and Resets 0 Sleep Enable 2 Register 40080138

Power Clocks and Resets 0 Sleep Enable 3 Register 4008013C

Power Clocks and Resets 0 Sleep Enable 4 Register 40080140

Power Clocks and Resets 0 Clock Required 0 Register 40080150

Power Clocks and Resets 0 Clock Required 1 Register 40080154

Power Clocks and Resets 0 Clock Required 2 Register 40080158

Power Clocks and Resets 0 Clock Required 3 Register 4008015C

Power Clocks and Resets 0 Clock Required 4 Register 40080160

Power Clocks and Resets 0 Reset Enable 0 Register 40080170

Power Clocks and Resets 0 Reset Enable 1 Register 40080174

Power Clocks and Resets 0 Reset Enable 2 Register 40080178

Power Clocks and Resets 0 Reset Enable 3 Register 4008017C

Power Clocks and Resets 0 Reset Enable 4 Register 40080180

Power Clocks and Resets 0 Peripheral Reset Lock Register 40080184

GPIO 0 GPIO000 Pin Control Register 40081000

GPIO 0 GPIO002 Pin Control Register 40081008

Host
Type

Register
Address

DS00003416B-page 56  2020 Microchip Technology Inc.

TABLE 3-5: REGISTER MAP

Block Instance Register

GPIO 0 GPIO003 Pin Control Register 4008100C

GPIO 0 GPIO004 Pin Control Register 40081010

GPIO 0 GPIO012 Pin Control Register 40081028

GPIO 0 GPIO013 Pin Control Register 4008102C

GPIO 0 GPIO015 Pin Control Register 40081034

GPIO 0 GPIO016 Pin Control Register 40081038

GPIO 0 GPIO020 Pin Control Register 40081040

GPIO 0 GPIO021 Pin Control Register 40081044

GPIO 0 GPIO026 Pin Control Register 40081058

GPIO 0 GPIO027 Pin Control Register 4008105C

GPIO 0 GPIO030 Pin Control Register 40081060

GPIO 0 GPIO032 Pin Control Register 40081068

GPIO 0 GPIO034 Pin Control Register 40081070

GPIO 0 GPIO045 Pin Control Register 40081094

GPIO 0 GPIO046 Pin Control Register 40081098

GPIO 0 GPIO047 Pin Control Register 4008109C

GPIO 0 GPIO050 Pin Control Register 400810A0

GPIO 0 GPIO051 Pin Control Register 400810A4

GPIO 0 GPIO053 Pin Control Register 400810AC

GPIO 0 GPIO055 Pin Control Register 400810B4

GPIO 0 GPIO056 Pin Control Register 400810B8

GPIO 0 GPIO057 Pin Control Register 400810BC

GPIO 0 GPIO063 Pin Control Register 400810CC

GPIO 0 GPIO070 Pin Control Register 400810E0

GPIO 0 GPIO071 Pin Control Register 400810E4

GPIO 0 GPIO104 Pin Control Register 40081110

GPIO 0 GPIO105 Pin Control Register 40081114

GPIO 0 GPIO106 Pin Control Register 40081118

GPIO 0 GPIO107 Pin Control Register 4008111C

GPIO 0 GPIO112 Pin Control Register 40081128

GPIO 0 GPIO113 Pin Control Register 4008112C

GPIO 0 GPIO120 Pin Control Register 40081140

GPIO 0 GPIO121 Pin Control Register 40081144

GPIO 0 GPIO122 Pin Control Register 40081148

GPIO 0 GPIO123 Pin Control Register 4008114C

GPIO 0 GPIO124 Pin Control Register 40081150

GPIO 0 GPIO125 Pin Control Register 40081154

GPIO 0 GPIO126 Pin Control Register 40081158

GPIO 0 GPIO127 Pin Control Register 4008115C

GPIO 0 GPIO130 Pin Control Register 40081160

GPIO 0 GPIO131 Pin Control Register 40081164

GPIO 0 GPIO132 Pin Control Register 40081168

GPIO 0 GPIO140 Pin Control Register 40081180

GPIO 0 GPIO143 Pin Control Register 4008118C

CEC1712

Host
Type

Register
Address

 2020 Microchip Technology Inc. DS00003416B-page 57

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

GPIO 0 GPIO144 Pin Control Register 40081190

GPIO 0 GPIO145 Pin Control Register 40081194

GPIO 0 GPIO146 Pin Control Register 40081198

GPIO 0 GPIO147 Pin Control Register 4008119C

GPIO 0 GPIO150 Pin Control Register 400811A0

GPIO 0 GPIO156 Pin Control Register 400811B8

GPIO 0 GPIO157 Pin Control Register 400811BC

GPIO 0 GPIO163 Pin Control Register 400811CC

GPIO 0 GPIO165 Pin Control Register 400811D4

GPIO 0 GPIO170 Pin Control Register 400811E0

GPIO 0 GPIO171 Pin Control Register 400811E4

GPIO 0 GPIO200 Pin Control Register 40081200

GPIO 0 GPIO201 Pin Control Register 40081204

GPIO 0 GPIO202 Pin Control Register 40081208

GPIO 0 GPIO203 Pin Control Register 4008120C

GPIO 0 GPIO204 Pin Control Register 40081210

GPIO 0 GPIO223 Pin Control Register 4008124C

GPIO 0 GPIO224 Pin Control Register 40081250

GPIO 0 GPIO227 Pin Control Register 4008125C

GPIO 0 GPIO250 Pin Control Register 400812A0

GPIO 0 GPIO253 Pin Control Register 400812AC

GPIO 0 Input GPIO[000:036] 40081300

GPIO 0 Input GPIO[040:076] 40081304

GPIO 0 Input GPIO[100:127] 40081308

GPIO 0 Input GPIO[140:176] 4008130C

GPIO 0 Input GPIO[200:236] 40081310

GPIO 0 Input GPIO[240:276] 40081314

GPIO 0 Output GPIO[000:036] 40081380

GPIO 0 Output GPIO[040:076] 40081384

GPIO 0 Output GPIO[100:127] 40081388

GPIO 0 Output GPIO[140:176] 4008138C

GPIO 0 Output GPIO[200:236] 40081390

GPIO 0 Output GPIO[240:276] 40081394

GPIO 0 GPIO000 Pin Control2 Register 40081500

GPIO 0 GPIO002 Pin Control2 Register 40081508

GPIO 0 GPIO003 Pin Control2 Register 4008150C

GPIO 0 GPIO004 Pin Control2 Register 40081510

GPIO 0 GPIO012 Pin Control2 Register 40081528

GPIO 0 GPIO013 Pin Control2 Register 4008152C

GPIO 0 GPIO015 Pin Control2 Register 40081534

GPIO 0 GPIO016 Pin Control2 Register 40081538

GPIO 0 GPIO020 Pin Control2 Register 40081540

GPIO 0 GPIO021 Pin Control2 Register 40081544

GPIO 0 GPIO026 Pin Control2 Register 40081558

Host
Type

Register
Address

DS00003416B-page 58  2020 Microchip Technology Inc.

TABLE 3-5: REGISTER MAP

Block Instance Register

GPIO 0 GPIO027 Pin Control2 Register 4008155C

GPIO 0 GPIO030 Pin Control2 Register 40081560

GPIO 0 GPIO032 Pin Control2 Register 40081568

GPIO 0 GPIO034 Pin Control2 Register 40081570

GPIO 0 GPIO045 Pin Control2 Register 40081594

GPIO 0 GPIO046 Pin Control2 Register 40081598

GPIO 0 GPIO047 Pin Control2 Register 4008159C

GPIO 0 GPIO050 Pin Control2 Register 400815A0

GPIO 0 GPIO051 Pin Control2 Register 400815A4

GPIO 0 GPIO053 Pin Control2 Register 400815AC

GPIO 0 GPIO055 Pin Control2 Register 400815B4

GPIO 0 GPIO056 Pin Control2 Register 400815B8

GPIO 0 GPIO057 Pin Control2 Register 400815BC

GPIO 0 GPIO063 Pin Control2 Register 400815CC

GPIO 0 GPIO070 Pin Control2 Register 400815E0

GPIO 0 GPIO071 Pin Control2 Register 400815E4

GPIO 0 GPIO104 Pin Control2 Register 40081610

GPIO 0 GPIO105 Pin Control2 Register 40081614

GPIO 0 GPIO106 Pin Control2 Register 40081618

GPIO 0 GPIO107 Pin Control2 Register 4008161C

GPIO 0 GPIO112 Pin Control2 Register 40081628

GPIO 0 GPIO113 Pin Control2 Register 4008162C

GPIO 0 GPIO120 Pin Control2 Register 40081640

GPIO 0 GPIO121 Pin Control2 Register 40081644

GPIO 0 GPIO122 Pin Control2 Register 40081648

GPIO 0 GPIO123 Pin Control2 Register 4008164C

GPIO 0 GPIO124 Pin Control2 Register 40081650

GPIO 0 GPIO125 Pin Control2 Register 40081654

GPIO 0 GPIO126 Pin Control2 Register 40081658

GPIO 0 GPIO127 Pin Control2 Register 4008165C

GPIO 0 GPIO130 Pin Control2 Register 40081660

GPIO 0 GPIO131 Pin Control2 Register 40081664

GPIO 0 GPIO132 Pin Control2 Register 40081668

GPIO 0 GPIO140 Pin Control2 Register 40081680

GPIO 0 GPIO143 Pin Control2 Register 4008168C

GPIO 0 GPIO144 Pin Control2 Register 40081690

GPIO 0 GPIO145 Pin Control2 Register 40081694

GPIO 0 GPIO146 Pin Control2 Register 40081698

GPIO 0 GPIO147 Pin Control2 Register 4008169C

GPIO 0 GPIO150 Pin Control2 Register 400816A0

GPIO 0 GPIO156 Pin Control2 Register 400816B8

GPIO 0 GPIO157 Pin Control2 Register 400816BC

GPIO 0 GPIO163 Pin Control2 Register 400816CC

GPIO 0 GPIO165 Pin Control2 Register 400816D4

CEC1712

Host
Type

Register
Address

 2020 Microchip Technology Inc. DS00003416B-page 59

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

GPIO 0 GPIO170 Pin Control2 Register 400816E0

GPIO 0 GPIO171 Pin Control2 Register 400816E4

GPIO 0 GPIO200 Pin Control2 Register 40081700

GPIO 0 GPIO201 Pin Control2 Register 40081704

GPIO 0 GPIO202 Pin Control2 Register 40081708

GPIO 0 GPIO203 Pin Control2 Register 4008170C

GPIO 0 GPIO204 Pin Control2 Register 40081710

GPIO 0 GPIO223 Pin Control2 Register 4008174C

GPIO 0 GPIO224 Pin Control2 Register 40081750

GPIO 0 GPIO227 Pin Control2 Register 4008175C

GPIO 0 GPIO250 Pin Control2 Register 400817A0

GPIO 0 GPIO253 Pin Control2 Register 400817AC

UART 0 Receive Buffer Register Run-

UART 0 Transmit Buffer Register Run-

UART 0 Programmable Baud Rate Generator LSB Register Run-

UART 0 Programmable Baud Rate Generator MSB Register Run-

UART 0 Interrupt Enable Register Run-

UART 0 FIFO Control Register Run-

UART 0 Interrupt Identification Register Run-

UART 0 Line Control Register Run-

UART 0 Modem Control Register Run-

UART 0 Line Status Register Run-

UART 0 Modem Status Register Run-

UART 0 Scratchpad Register Run-

UART 0 Activate Register Con-

UART 0 Configuration Select Register Con-

UART 1 Receive Buffer Register Run-

UART 1 Transmit Buffer Register Run-

UART 1 Programmable Baud Rate Generator LSB Register Run-

Host
Type

time

time

time

time

time

time

time

time

time

time

time

time

fig

fig

time

time

time

Register
Address

400F2400

400F2400

400F2400

400F2401

400F2401

400F2402

400F2402

400F2403

400F2404

400F2405

400F2406

400F2407

400F2730

400F27F0

400F2800

400F2800

400F2800

DS00003416B-page 60  2020 Microchip Technology Inc.

TABLE 3-5: REGISTER MAP

Block Instance Register

UART 1 Programmable Baud Rate Generator MSB Register Run-

UART 1 Interrupt Enable Register Run-

UART 1 FIFO Control Register Run-

UART 1 Interrupt Identification Register Run-

UART 1 Line Control Register Run-

UART 1 Modem Control Register Run-

UART 1 Line Status Register Run-

UART 1 Modem Status Register Run-

UART 1 Scratchpad Register Run-

UART 1 Activate Register Con-

UART 1 Configuration Select Register Con-

UART 2 Receive Buffer Register Run-

UART 2 Transmit Buffer Register Run-

UART 2 Programmable Baud Rate Generator LSB Register Run-

UART 2 Programmable Baud Rate Generator MSB Register Run-

UART 2 Interrupt Enable Register Run-

UART 2 FIFO Control Register Run-

UART 2 Interrupt Identification Register Run-

UART 2 Line Control Register Run-

UART 2 Modem Control Register Run-

UART 2 Line Status Register Run-

UART 2 Modem Status Register Run-

UART 2 Scratchpad Register Run-

UART 2 Activate Register Con-

CEC1712

Host
Type

time

time

time

time

time

time

time

time

time

fig

fig

time

time

time

time

time

time

time

time

time

time

time

time

fig

Register
Address

400F2801

400F2801

400F2802

400F2802

400F2803

400F2804

400F2805

400F2806

400F2807

400F2B30

400F2BF0

400F2C00

400F2C00

400F2C00

400F2C01

400F2C01

400F2C02

400F2C02

400F2C03

400F2C04

400F2C05

400F2C06

400F2C07

400F2F30

 2020 Microchip Technology Inc. DS00003416B-page 61

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

UART 2 Configuration Select Register Con-

Real Time Clock 0 Seconds Register Run-

Real Time Clock 0 Seconds Alarm Register Run-

Real Time Clock 0 Minutes Register Run-

Real Time Clock 0 Minutes Alarm Register Run-

Real Time Clock 0 Hours Register Run-

Real Time Clock 0 Hours Alarm Register Run-

Real Time Clock 0 Day of Week Register Run-

Real Time Clock 0 Day of Month Register Run-

Real Time Clock 0 Month Register Run-

Real Time Clock 0 Year Register Run-

Real Time Clock 0 Register A Run-

Real Time Clock 0 Register B Run-

Real Time Clock 0 Register C Run-

Real Time Clock 0 Register D Run-

Real Time Clock 0 Reserved Run-

Real Time Clock 0 Reserved Run-

Real Time Clock 0 RTC Control Register Run-

Real Time Clock 0 Week Alarm Register Run-

Real Time Clock 0 Daylight Savings Forward Register Run-

Real Time Clock 0 Daylight Savings Backward Register Run-

Real Time Clock 0 TEST Run-

Global Configuration 0 Global Configuration Reserved Run-

Global Configuration 0 Control Run-

Host
Type

fig

time

time

time

time

time

time

time

time

time

time

time

time

time

time

time

time

time

time

time

time

time

time

time

Register
Address

400F2FF0

400F5000

400F5001

400F5002

400F5003

400F5004

400F5005

400F5006

400F5007

400F5008

400F5009

400F500A

400F500B

400F500C

400F500D

400F500E

400F500F

400F5010

400F5014

400F5018

400F501C

400F5020

400FFF00

400FFF02

DS00003416B-page 62  2020 Microchip Technology Inc.

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

Global Configuration 0 Logical Device Number Run-

Global Configuration 0 Device Revision Run-

Global Configuration 0 Device Sub ID Run-

Global Configuration 0 Device ID[7:0] Run-

Global Configuration 0 Device ID[15:0] Run-

Global Configuration 0 Legacy Device ID Run-

Global Configuration 0 TEST Run-

Global Configuration 0 TEST Run-

Global Configuration 0 Test0 Run-

Global Configuration 0 Test1 Run-

Global Configuration 0 TEST Run-

Global Configuration 0 TEST Run-

Global Configuration 0 TEST Run-

Global Configuration 0 TEST Run-

ARM M4 0 Auxiliary_Control DFFFE008

ARM M4 0 SystemTick_Ctrl_Status DFFFE010

ARM M4 0 SystemTick_Reload_Value DFFFE014

ARM M4 0 SystemTick_Current_Value DFFFE018

ARM M4 0 SystemTick_Calibration_Value DFFFE01C

ARM M4 0 CPU_ID DFFFED00

ARM M4 0 Interrupt_Ctl_and_State DFFFED04

ARM M4 0 Vector_Table_Offset DFFFED08

ARM M4 0 Application_Interrupt_and_Reset_Ctl DFFFED0C

ARM M4 0 System_Ctl DFFFED10

ARM M4 0 Config_and_Ctl DFFFED14

ARM M4 0 System_Handler_Priority1 DFFFED18

ARM M4 0 System_Handler_Priority2 DFFFED1C

ARM M4 0 System_Handler_Priority3 DFFFED20

ARM M4 0 System_Handler_Ctl_and_State DFFFED24

ARM M4 0 Configurable_Fault_Status DFFFED28

ARM M4 0 Hard_Fault_Status DFFFED2C

ARM M4 0 Debug_Fault_Status DFFFED30

ARM M4 0 Debug_Halting_Ctl_and_Status DFFFEDF0

Host
Type

time

time

time

time

time

time

time

time

time

time

time

time

time

time

Register
Address

400FFF07

400FFF1C

400FFF1D

400FFF1E

400FFF1F

400FFF20

400FFF28

400FFF29

400FFF2A

400FFF2B

400FFF2C

400FFF2D

400FFF2E

400FFF2F

 2020 Microchip Technology Inc. DS00003416B-page 63

CEC1712

TABLE 3-5: REGISTER MAP

Block Instance Register

ARM M4 0 Debug_Core_Register_Selector DFFFEDF4

ARM M4 0 Debug_Core_Register_Data DFFFEDF8

ARM M4 0 Debug_Exception_and_Monitor_Ctl DFFFEDFC

ARM M4 0 Bus_Fault_Address DFFFED38

ARM M4 0 Auxiliary_Fault_Status DFFFED3C

ARM M4 0 Processor_Feature0 DFFFED40

ARM M4 0 Processor_Feature1 DFFFED44

ARM M4 0 Debug_Features0 DFFFED48

ARM M4 0 Auxiliary_Features0 DFFFED4C

ARM M4 0 Memory_Model_Feature0 DFFFED50

ARM M4 0 Memory_Model_Feature1 DFFFED54

ARM M4 0 Memory_Model_Feature2 DFFFED58

ARM M4 0 Memory_Model_Feature3 DFFFED5C

ARM M4 0 Instruction_Set_Attributes0 DFFFED60

ARM M4 0 Instruction_Set_Attributes1 DFFFED64

ARM M4 0 Instruction_Set_Attributes2 DFFFED68

ARM M4 0 Instruction_Set_Attributes3 DFFFED6C

ARM M4 0 Instruction_Set_Attributes4 DFFFED70

ARM M4 0 Coprocessor_Access_Ctl DFFFED88

ARM M4 0 Software_Triggered_Interrupt DFFFEF00

Host
Type

Register
Address

DS00003416B-page 64  2020 Microchip Technology Inc.

CEC1712

4.0 POWER, CLOCKS, AND RESETS

4.1 Introduction

The Power, Clocks, and Resets (PCR) chapter identifies all the power supplies, clock sources, and reset inputs to the
chip and defines all the derived power, clock, and reset signals. In addition, this section identifies Power, Clock, and
Reset events that may be used to generate an interrupt event, as well as, the Chip Power Management Features.

4.2 References

No references have been cited for this chapter.

4.3 Interrupts

The Power, Clocks, and Resets logic generates no events

4.4 Power

TABLE 4-1: POWER SOURCE DEFINITIONS

Power Well

VTR_REG 1.8V - 3.3V This supply is used to derive the chip’s

VTR_ANALOG 3.3V 3.3V Analog Power Supply.

Nominal

Vol tage

Description Source

Pin Interface

core power.

VTR_PLL 3.3V 3.3V Power Supply for the 48MHz PLL.

This must be connected to the same
supply as VTR_ANALOG.

VTR1 3.3V 3.3V System Power Supply.

This is typically connected to the
“Always-on” or “Suspend” supply rails
in system. This supply must be on prior
to the system RSMRST# signal being
deasserted

VTR2 3.3V or 1.8V 3.3V or 1.8V System Power Supply.

This supply is used to power one bank
of I/O pins. See Note 1.

VTR_CORE 1.2V The main power well for internal logic Internal regulator

VBAT 3.0V - 3.3V System Battery Back-up Power Well.

This is the “coin-cell” battery.

GPIOs that share pins with VBAT sig­nals are powered by this supply.

VSS 0V Digital Ground Pin Interface

Note 1: See Section 4.4.1, "I/O Rail Requirements" for connection requirements for VTRx.

2: The source for the Internal regulator is VTR_REG.

3: VTR refers to VTR_REG and VTR_ANALOG.

Pin Interface

Pin Interface

Pin Interface

Pin Interface
VBAT

 2020 Microchip Technology Inc. DS00003416B-page 65

CEC1712

VBAT
to EC

To EC as

VTR

3.0V nom
Coin Cell

RTCﺴRail (PCH, System)

+

(Schottky

Diode)

(Schottky Diode)

3.3V nom,
from AC Source
or Battery Pack

()

Possible

Current Limiter

(1K typ.)

3.3V max with
VTR = 0V,

3.6V max with

VTR = VBAT

4.4.1 I/O RAIL REQUIREMENTS

All pins are powered by the power supply pins: VBAT, VTR1, VTR2. The VBAT supply must be 3V to 3.6V maximum,
as shown in the following section. The VTR1 is fixed 3.3V and VTR2 pins may be connected to either a 3.3V or a 1.8V
power supply as configured by the firmware.

If a power rail is not powered and stable when RESET_SYS is de-asserted and is not required for booting, software can
configure the pins on that bank appropriately by setting the corresponding bit in the GPIO Bank Power Register, once
software can determine that the power supply is up and stable. All GPIOs in the bank must be left in their default state
and not modified until the Bank Power is configured properly.

4.4.2 BATTERY CIRCUIT REQUIREMENTS

VBAT must always be present if VTR_ANALOG is present.

Microchip recommends removing all power sources to the device defined in Table 4-1, "Power Source Definitions" and
all external voltage references defined in Table 4-2, "Voltage Reference Definitions" before removing and replacing the
battery. In addition, upon removing the battery, discharge the battery pin before replacing the battery.

The following external circuit is recommended to fulfill this requirement:

FIGURE 4-1: RECOMMENDED BATTERY CIRCUIT

4.4.3 VOLTAGE REFERENCES

Table 4-2 lists the External Voltage References to which the CEC1712 provides high impedance interfaces.

TABLE 4-2: VOLTAGE REFERENCE DEFINITIONS

Power Well

VREF_VTT Variable n/a Variable Processor Voltage

VREF_ADC Variable n/a Variable ADC Reference Voltage Pin Interface

Note: In order to achieve the lowest leakage current when both PECI and SB TSI are not used, set the

Nominal Input

Voltag e

VREF_VTT Disable bit to 1. This bit is defined in PECI Disable Register bit 0.

Scaling Ratio

Nominal

Monitored

Volt age

Description Source

Pin Interface
External Voltage Reference
Used to scale Processor
Interface signals. (See Note)

DS00003416B-page 66  2020 Microchip Technology Inc.

CEC1712

4.4.4 SYSTEM POWER SEQUENCING

The following table defines the behavior of the main power rails in each of the defined ACPI power states.

TABLE 4-3: TYPICAL POWER SUPPLIES VS. ACPI POWER STATES

ACPI Power State

Supply

Name

VTR1 ON ON ON ON ON OFF “Always-on” Supply

VTR2 ON ON ON ON ON OFF 3.3V/1.8V Power Supply

VBAT ON ON ON ON

Note: This device requires that the VBAT power is on when the VTR(Note 3) power supply is on. External circuitry,

a diode isolation circuit, is implemented on the motherboard to extend the battery life. This external circuitry
ensures the VBAT pin will derive power from the VTR power well when it is on. Therefore, the VBAT supply
will never appear to be off when the VTR rail is on.

4.5 Clocks

S0

(FULL

ON)

S1

(POS)S3(STR)

S4

(STD)

Note

S5

(Soft Off)G3(MECH Off)

ON

Note

ON

Note

Description

for Bank 2

Battery Back-up Supply

The following section defines the clocks that are generated and derived.

4.5.1 RAW CLOCK SOURCES

The table defines raw clocks .

TABLE 4-4: SOURCE CLOCK DEFINITIONS

Clock Name Frequency Description Source

32KHZ_IN 32.768 kHz

(nominal)

32.768 kHz Crystal
Oscillator

32.768 kHz Silicon
Oscillator

32 MHz Ring
Oscillator

48 MHz PLL 48MHz The 48 MHz Phase Locked Loop gen-

32.768 kHz A 32.768 kHz parallel resonant crystal

32.768 kHz 32.768 kHz low power Internal Oscil-

32MHz The 32MHz Ring Oscillator is used to

Single-ended external clock input pin 32KHZ_IN pin

Pin Interface (XTAL1 and XTAL2)
connected between the XTAL1 and
XTAL2 pins. The accuracy of the
clock depends on the accuracy of the
crystal and the characteristics of the
analog components used as part of
the oscillator

The crystal oscillator source can
bypass the crystal with a single­ended clock input. This option is con­figured with the Clock Enable Regis-

ter.

lator. The frequency is 32.768KHz
±2%.

supply a clock for the 48MHz main
clock domain while the 48MHz PLL is
not locked. Its frequency can range
from 12Mhz to 46MHz.

erates a 48MHz clock locked to the

VBAT 32KHz Clock

When used singled-ended, input pin

is XTAL2

Internal Oscillator powered by VBAT.

Powered by VTR_CORE.

Powered by VTR_CORE.

May be stopped by Chip Power Man-

agement Features.

 2020 Microchip Technology Inc. DS00003416B-page 67

CEC1712

4.5.2 CLOCK DOMAINS

TABLE 4-5: CLOCK DOMAIN DEFINITIONS

Clock Domain Description

VBAT 32KHz Clock The clock source used as reference for PLL lock and System Clock

controls.

32KHz The clock source used by internal blocks that require an always-on

low speed clock

48MHz The main clock source used by most internal blocks

100KHz A low-speed clock derived from the 48MHz clock domain. Used as

a time base for PWMs and Tachs.

EC_CLK The clock used by the EC processor. The frequency is determined

by the Processor Clock Control Register.

4.5.3 48MHZ PLL

The 48MHz clock domain is primarily driven by a 48MHz PLL, which derives 48MHz from the VBAT 32KHz Clock
domain. In Heavy Sleep mode, the 48MHz PLL is shut off. When the PLL is started, either from waking from the Heavy
Sleep mode, or after a Power On Reset, the 32MHz ring oscillator becomes the clock source for the 48MHz clock
domain until the PLL is stable. The PLL becomes stable after about 3ms after the VBAT 32KHz Clock is stable; until that
time, the 48MHz clock domain may range from 16MHz to 48MHz, as this is the accuracy range of the 32MHz ring.

The PLL requires its own power 3.3V power supply, VTR_PLL. This power rail must be active and stable no later than
the latest of VTR_REG and VTR_ANALOG. There is no hardware detection of VTR_PLL power good in the reset gen­erator.

4.5.4 32KHZ CLOCK

The 32kHz Clock Domain may be sourced from a crystal oscillator, using an external crystal, by an internal 32kHz oscil­lator, or from a single-ended clock input. The external single-ended clock source can itself be sourced from the
32KHZ_IN signal that is a GPIO alternate function or from the XTAL2 crystal pin. The Clock Enable Register is used to
configure the source for the 32 kHz clock domain.

When VTR_CORE is off, the 32 kHz clock domain can be disabled, for lowest standby power, or it can be kept running
in order to provide a clock for the Real Time Clock or the Week Timer.

An external single-ended clock input for 32KHZ_IN may be supplied by any accurate 32KHz clock source in the system.
The SUSCLK output from the chipset may be used as the 32KHz source. SUSCLK must be present when VTR is on.
See chipset documentation for details on the use of SUSCLK.

If firmware switches the 32KHz clock source, the 48MHz PLL will be shut off and then restarted. The 48MHz clock
domain will become unlocked and be sourced from the 32 MHz Ring Oscillator until the 48MHz PLL is on and locked.

4.5.4.1 VBAT 32KHz Clock

This clock source is used to drive the 48MHz PLL. VBAT 32KHz Clock should remain on while the 48Mhz PLL is ON.
The internal source provides a reference for the Activity Detect that monitors the external clock input, as well as provid­ing a low latency backup clock source when the Activity Detector cannot detect a clock on the external input.

The VBAT 32KHz Clock Internal Clock Source can be driven either by the 32.768 kHz Silicon Oscillator or the 32.768

kHz Crystal Oscillator.

4.5.4.2 External 32KHz Clock Activity Detector

When the EXT_32K field in the Clock Enable Register is set for an external clock source an Activity Detector monitors
the external 32KHz signal at all times. If there is no clock detected on the pin, the 32KHZ clock domain is switched to
the internal 32KHz silicon oscillator. If a clock is again detected on the pin, the 32KHz clock domain is switched to the pin

The following figure illustrates the 32KHz clock domain sourcing.

DS00003416B-page 68  2020 Microchip Technology Inc.

FIGURE 4-2: 32KHZ ACTIVITY DETECTOR

A ctivity

Detector

32 KHz Clock Do m a in

32 KHz

C r yst a l O sc illa to r

0

1

32 KHz

S ilico n O scilla to r

1

0

32 KHz (X TA L2)

XOSEL

0

1

32K_S O URC E

32 KH z (32KH Z_IN)

EX T_32K

Always-on

CEC1712

4.5.4.3 32KHz Crystal Oscillator

If the 32KHz source will never be the crystal oscillator, then the XTAL2 pin should be grounded. The XTAL1 pin should
be left unconnected.

4.6 Resets

TABLE 4-6: DEFINITION OF RESET SIGNALS

RESET_VBAT Internal VBAT Reset signal. This signal is used

RESET_VTR Internal VTR Reset signal. This internal reset signal is asserted as long as

Reset Description Source

RESET_VBAT is a pulse that is asserted at the

to reset VBAT powered registers.

rising edge of VTR power if the VBAT voltage is
below a nominal 1.25V. RESET_VBAT is also
asserted as a level if, while VTR power is not
present, the coin cell is replaced with a new cell
that delivers at least a nominal 1.25V. In this lat­ter case RESET_VBAT is de-asserted when
VTR power is applied. No action is taken if the
coin cell is replaced, or if the VBAT voltage falls
below 1.25 V nominal, while VTR power is pres­ent.

the reset generator determines that the output of
the internal regulator is stable at its target volt­age and that the voltage rail supplying the main
clock PLL is at 3.3V.

Although most VTR_CORE-powered registers
are reset on RESET_SYS, some registers are
only reset on this reset.

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TABLE 4-6: DEFINITION OF RESET SIGNALS (CONTINUED)

Reset Description Source

RESET_SYS Internal Reset signal. This signal is used to reset

VTR_CORE powered registers.

RESET_VCC Performs a reset when Host power (VCC) is

turned off

RESET_HOST Performs a reset when VCC_PWRGD is low This signal is asserted if

WDT Event A WDT Event generates the RESET_SYS

event. This signal resets VTR_CORE powered
registers with the exception of the WDT Event

Count Register register. Note that the glitch pro-

tect circuits do not activate on a WDT reset.

WDT Event does not reset VBAT registers or

logic.

RESET_SYS_n
WDT

Internal Reset signal. This signal is used to reset

VTR_CORE powered registers not effected by a
WDT Event

RESET_SYS is the main global reset signal.

This reset signal will be asserted if:

• RESET_VTR is asserted

• The nRESET_IN pin asserted

•A WDT Event event is asserted

• A soft reset is asserted by the SOFT_SYS-

_RESET bit in the System Reset Register

• ARM M4 SYSRESETREQ

This signal is asserted if

Note: RESET_SYS is asserted

• RESET_SYS is asserted

• VCC_PWRGD is low

•The PWR_INV bit in the Power Reset Con-

trol Register is ‘1b’1

This reset signal will be asserted if:

•A WDT Event event is asserted

This event is indicated by the WDT bit in the

Power-Fail and Reset Status Register

This reset signal will be asserted if:

• RESET_VTR is asserted

• The nRESET_IN pin asserted

A RESET_SYS_nWDT is used to reset registers
that need to be preserved through a WDT Event
like a WDT Event Count Register.

RESET_EC Internal reset signal to reset the processor in the

EC Subsystem.

RESET_BLOCK
_N

Each IP block in the device may be configured to
be reset by setting the RESET_ENABLE regis­ter.

This reset is a stretched version of

RESET_SYS. This reset asserts at the same

time that RESET_SYS asserts and is held
asserted for 1ms after

This reset signal will be asserted if Block N
RESET_ENABLE is set to 1 and Peripheral

Reset Enable n Register is unlocked.

RESET_SYS deasserts.

DS00003416B-page 70  2020 Microchip Technology Inc.

FIGURE 4-3: RESETS BLOCK DIAGRAM

RESET_VTR

SOFT_SYS_RESET

1

TEST_VTR_RESET

3

RESET_SYS

VCC_PWRGD

RESET_HOST

Note1:SOFT_SYS_RESETisimplementedinbit[8]oftheSystemResetRegist er
Note2:PWR_INVisimplementedinbit[0]ofthePowerResetControlRegister

Note3:TEST_VTR_RESETisimplementedinbit[1]oftheHostGlo balTes t R egi s ter

1ms

Delay

RESET_EC

RESETI

PWROK

PWR_INV

2

RESET_VCC

PWR_INV

2

WDT

CORTEXM4_RESET

Reset

Enable

Register

RESET_SYS_nWDT

E.g.WDTEventCount

RESET_BLOCK_N

WDT_Even t

CEC1712

4.7 Chip Power Management Features

This device is designed to always operate in its lowest power state during normal operation. In addition, this device
offers additional programmable options to put individual logical blocks to sleep as defined in the following section,

Section 4.7.1.

4.7.1 BLOCK LOW POWER MODES

All power related control signals are generated and monitored centrally in the chip’s Power, Clocks, and Resets (PCR)
block. The power manager of the PCR block uses a sleep interface to communicate with all the blocks. The sleep inter­face consists of three signals:

• SLEEP_ENABLE (request to sleep the block)
nals are generated for every clock segment. Each group consists of a SLEEP_ENABLE signal for every block in
that clock segment.

• CLOCK_REQUIRED (request clock on)

is generated by the PCR block. A group of SLEEP_ENABLE sig-

is generated by every block. They are grouped by blocks on the same

clock segment. The PCR monitors these signals to see when it can gate off clocks.

A block can always drive CLOCK_REQUIRED low synchronously, but it must

nal clocks are gated and it has to assume that the clock input itself is gated. Therefore the block can only drive
CLOCK_REQUIRED high as a result of a register access or some other input signal.

drive it high asynchronously since its inter-

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The following table defines a block’s power management protocol:

TABLE 4-7: POWER MANAGEMENT PROTOCOL

Power State SLEEP_ENABLE CLOCK_REQUIRED Description

Normal operation Low Low Block is idle and NOT requesting clocks. The block

gates its own internal clock.

Normal operation Low High Block is NOT idle and requests clocks.

Request sleep Rising Edge Low Block is IDLE and enters sleep mode immediately. The

block gates its own internal clock. The block cannot
request clocks again until SLEEP_ENABLE goes low.

Request sleep Rising Edge High then Low Block is not IDLE and will stop requesting clocks and

enter sleep when it finishes what it is doing. This delay
is block specific, but should be less than 1 ms. The
block gates its own internal clock. After driving
CLOCK_REQUIRED low, the block cannot request
clocks again until SLEEP_ENABLE goes low.

Register Access X High Register access to a block is always available regard-

less of SLEEP_ENABLE. Therefore the block ungates
its internal clock and drives CLOCK_REQUIRED high
during the access. The block will regate its internal
clock and drive CLOCK_REQUIRED low when the
access is done.

A wake event clears all SLEEP_ENABLE bits momentarily, and then returns the SLEEP_ENABLE bits back to their orig­inal state. The block that needs to respond to the wake event will do so.

The Sleep Enable, Clock Required and Reset Enable Registers are defined in Section 4.8.

4.7.2 CONFIGURING THE CHIP’S SLEEP STATES

The chip supports two sleep states: LIGHT SLEEP and HEAVY SLEEP. The chip will enter one of these two sleep states
only when all the blocks have been commanded to sleep and none of them require a 48MHz clock source (i.e., all
CLOCK_REQUIRED status bits are 0), and the processor has executed its sleep instruction. These sleep states must
be selected by firmware via the System Sleep Control bits implemented in the System Sleep Control Register prior to
issuing the sleep instruction. Table 4-9, "System Sleep Modes" defines each of these sleep states.

There are two ways to command the chip blocks to enter sleep.

1. Assert the SLEEP_ALL bit located in the System Sleep Control Register

2. Assert all the individual block sleep enable bits

Blocks will only enter sleep after their sleep signal is asserted and they no longer require the 48MHz source. Each block
has a corresponding clock required status bit indicating when the block has entered sleep. The general operation is that
a block will keep the 48MHz clock source on until it completes its current transaction. Once the block has completed its
work, it deasserts its clock required signal. Blocks like timers, PWMs, etc. will de-assert their clock required signals
immediately. See the individual block Low Power Mode sections to determine how each individual block enters sleep.

4.7.3 DETERMINING WHEN THE CHIP IS SLEEPING

The TST_CLK_OUT pin can be used to verify the chip’s clock has stopped, which indicates the device is in LIGHT
SLEEP or HEAVY SLEEP, as determined by the System Sleep Control Register. If the clock is toggling the chip is in the
full on running state. if the clock is not toggling the chip has entered the programmed sleep state.

4.7.4 WAKING THE CHIP FROM SLEEPING STATE

The chip will remain in the configured sleep state until it detects either a wake event or a full VTR_CORE POR. A wake
event occurs when a wake-capable interrupt is enabled and triggered. Interrupts that are not wake-capable cannot occur
while the system is in LIGHT SLEEP or HEAVY SLEEP.

In LIGHT SLEEP, the 48MHz clock domain is gated off, but the 48 MHz PLL remains operational and locked to the

32KHz clock domain. On wake, the PLL output is ungated and the 48MHz clock domain starts immediately, with the
PLL_LOCK bit in the Oscillator ID Register set to ‘1’. Any device that requires an accurate clock, such as a UART, may

be used immediately on wake.

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CEC1712

In HEAVY SLEEP, the 48 MHz PLL is shut down. On wake, the 32 MHz Ring Oscillator is used to provide a clock so urce
for the 48MHz clock domain until the PLL locks to the 32KHz clock domain. The ring oscillator starts immediately on
wake, so there is no latency for the EC to start after a wake, However, the ring oscillator is only accurate to ±50%, so
any device that requires an accurate 48MHz clock will not operate correctly until the PLL locks.The time to lock latency
for the PLL is shown in Table 4-9, "System Sleep Modes".

The SLEEP_ALL bit is automatically cleared when the processor responds to an interrupt. This applies to non-wake
interrupts as well as wake interrupts, in the event an interrupt occurs between the time the processor issued a WAIT
FOR INTERRUPT instruction and the time the system completely enters the sleep state.

Any JTAG access to the ARM/STAP will cause a pseudo-wake event where the clocks are turned on, but the CHip is
still in sleep (SLEEP_EN's and SLEEP_ALL stay in the same state).This way the access can occur over JTAG, without
changing the parts state, and the part can go back to sleep once the JTAG access is over.

4.7.4.1 Wake-Only Events

Some devices which respond to an external master require the 48MHz clock domain to operate but do not necessarily
require and immediate processing by the EC. Wake-only events provide the means to start the 48MHz clock domain
without triggering an EC interrupt service routine. This events are grouped into a single GIRQ, GIRQ22. Events that are
enabled in that GIRQ will start the clock domain when the event occurs, but will not invoke an EC interrupt. The
SLEEP_ENABLE flags all remain asserted. If the activity for the event does not in turn trigger another EC interrupt, the
CLOCK_REQUIRED for the block will re-assert and the configured sleep state will be re-entered.

4.8 EC Registers

Registers for this block are shown in the following summary table. Addresses for each register are determined by adding
the offset to the Base Address for the Power, Clocks, and Resets Block in the Block Overview and Base Address Table
in Section 3.0, "Device Inventory".

TABLE 4-8: REGISTER SUMMARY

Offset Name

0h System Sleep Control Register
4h Processor Clock Control Register
8h Slow Clock Control Register

Ch Oscillator ID Register
10h PCR Power Reset Status Register
14h Power Reset Control Register
18h System Reset Register
1Ch Reserved
20h TEST
30h Sleep Enable 0 Register
34h Sleep Enable 1 Register
38h Sleep Enable 2 Register
3Ch Sleep Enable 3 Register
40h Sleep Enable 4 Register
50h Clock Required 0 Register
54h Clock Required 1 Register
58h Clock Required 2 Register
5Ch Clock Required 3 Register
60h Clock Required 4 Register
70h Reset Enable 0 Register
74h Reset Enable 1 Register
78h Reset Enable 2 Register
7Ch Reset Enable 3 Register
80h Reset Enable 4 Register
84h Peripheral Reset Lock Register

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All register addresses are naturally aligned on 32-bit boundaries. Offsets for registers that are smaller than 32 bits are
reserved and must not be used for any other purpose.

The bit definitions for the Sleep Enable, Clock Required and Reset Enable Registers are defined in the Sleep Enable
Register Assignments Table in Section 3.0, "Device Inventory".

4.9 Sleep Enable n Registers

4.9.1 SLEEP ENABLE N REGISTER

Offset

Bits Description Type Default

31:0 SLEEP_ENABLE

See Sleep Enable Register Assignments Table in Section 3.0, "Device Inventory"

R/W 0h RESET

1=Block is commanded to sleep at next available moment
0=Block is free to use clocks as necessary

Unassigned bits are reserved. They must be set to ‘1b’ when writ­ten. When read, unassigned bits return the last value written.

4.9.2 CLOCK REQUIRED N REGISTER

Offset

Bits Description Type Default

31:0 CLOCK_REQUIRED

See Sleep Enable Register Assignments Table in Section 3.0, "Device Inventory"

R0hRESET

1=Bock requires clocks
0=Block does not require clocks

Reset
Event

_SYS

Reset
Event

_SYS

Unassigned bits are reserved and always return 0 when read.

4.9.3 PERIPHERAL RESET ENABLE N REGISTER

Offset

Bits Description Type Default

31:0 PERIPHERAL_RESET_ENABLE

DS00003416B-page 74  2020 Microchip Technology Inc.

See Sleep Enable Register Assignments Table in Section 3.0, "Device Inventory"

Reset
Event

W0hRESET

_SYS

1= Will allow issue parallel reset to the peripherals. This is self
clearing bit.

4.9.4 SYSTEM SLEEP CONTROL REGISTER

CEC1712

Offset

Bits Description Type Default

0h

31:9 Reserved RES - -

8 SLEEP_IMMEDIATE

0 = System will only allow entry into sleep after PLL locks.
1 = System will allow entry into Heavy Sleep before PLL locks.

Heavy Sleep : Any sleep state where the PLL is OFF.
Light Sleep : Any sleep state where the PLL is ON.

7:4 Reserved RES - -

3 SLEEP_ALL

By setting this bit to ‘1b’ and then issuing a WAIT FOR INTER­RUPT instruction, the EC can initiate the System Sleep mode.
When no device requires the main system clock, the system enters
the sleep mode defined by the field SLEEP_MODE.

This bit is automatically cleared when the processor vectors to an
interrupt.

1=Assert all sleep enables
0=Do not sleep all

R/W 0h RESET

R/W 0h RESET

Reset
Event

_SYS

_SYS

2 TEST

Test bit. Should always be written with a ‘0b’.

1 Reserved RES - -

0 SLEEP_MODE

Sleep modes differ only in the time it takes for the 48MHz clock
domain to lock to 48MHz. The wake latency in all sleep modes is
0ms. Table 4-9 shows the time to lock latency for the different sleep
modes.

1=Heavy Sleep
0=Light Sleep

TABLE 4-9: SYSTEM SLEEP MODES

SLEEP_MODE Sleep State

0 LIGHT SLEEP 0 Output of the PLL is gated in sleep. The PLL remains on.

1 HEAVY SLEEP 3ms The PLL is shut down while in sleep.

Latency to

Lock

R/W 0h RESET

_SYS

R/W 0h RESET

_SYS

Description

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4.9.5 PROCESSOR CLOCK CONTROL REGISTER

Offset

Bits Description Type Default

31:8 Reserved RES - -

04h

7:0 PROCESSOR_CLOCK_DIVIDE

The following list shows examples of settings for this field and the
resulting EC clock rate.

48=divide the 48MHz clock by 48 (1MHz processor clock)
16=divide the 48MHz clock by 16 (4MHz processor clock)
4=divide the 48MHz clock by 4 (12MHz processor clock)
3=divide the 48MHz clock by 3 (16MHz processor clock)
1=divide the 48MHz clock by 1 (48MHz processor clock)
No other values are supported.

R/W 4h RESET

4.9.6 SLOW CLOCK CONTROL REGISTER

Offset

Bits Description Type Default

08h

Reset
Event

_SYS

Reset
Event

31:10 Reserved RES - -

9:0 SLOW_CLOCK_DIVIDE

Configures the 100KHz clock domain.

n=Divide by n
0=Clock off

The default setting is for 100KHz.

R/W 1E0h RESET

4.9.7 OSCILLATOR ID REGISTER

Offset

Bits Description Type Default

31:9 Reserved RES - -

0Ch

8 PLL_LOCK

Phase Lock Loop Lock Status

7:0 TEST R N/A RESET

R0hRESET

_SYS

Reset
Event

_SYS

_SYS

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4.9.8 PCR POWER RESET STATUS REGISTER

CEC1712

Offset

Bits Description Type Default

31:12 Reserved RES - -

10h

10 32K_ACTIVE

1=The 32K clock input is present. The internal 32K clock is derived

from the pin and the ring oscillator is synchronized to the exter­nal 32K clock

0=The 32K clock input is not present. The internal 32K clock is

derived from the ring oscillator

9 Reserved RES - -

8 WDT_EVENT

This bit allows the application code to determine WDT_EVENT
against RESET_VTR

7JTAG_RST#

Indicates the JTAG_RST# pin status.

The JTAG TRST# input is gated off low when Boundary scan mode
is enabled and will not be set in this mode.

R-RESET

R/W1C 0h RESET

R-RESET

Reset
Event

_SYS

_SYS-

_nWDT

_SYS

6 RESET_SYS_STATUS

Indicates the status of RESET_SYS.

The bit will not clear if a write 1 is attempted at the same time that a
RESET_VTR occurs; this way a reset event is never missed.

1=A reset occurred
0=No reset occurred since the last time this bit was cleared

5 VBAT_RESET_STATUS

Indicates the status of RESET_VBAT.

The bit will not clear if a write of ‘1’b is attempted at the same time
that a VBAT_RST_N occurs, this way a reset event is never
missed.

1=A reset occurred
0=No reset occurred while VTR_CORE was off or since the last

time this bit was cleared

4 RESET_VTR_STATUS

Indicates the status of RESET_VTR event.

Note 1: This read-only status bit always reflects the current status of the event and is not affected by any Reset

events.

R/WC 1h RESET

_SYS

R/WC - RESET

_SYS

R/W1C 1h RESET

_VTR

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Offset

Bits Description Type Default

Note 1: This read-only status bit always reflects the current status of the event and is not affected by any Reset

10h

3 RESET_HOST_STATUS

Indicates the status of RESET_HOST.

1=Reset not active
0=Reset active

1:0 Reserved RES - -

events.

R-Note 1

4.9.9 POWER RESET CONTROL REGISTER

Offset

Bits Description Type Default

14h

31: Reserved RES - -

Reset
Event

Reset
Event

7: Reserved RES - -

0PWR_INV

This bit allows firmware to control when the Host receives an indi­cation that the VCC power is valid, by controlling the state of the
PWROK pin.

R /

R/W

4.9.10 SYSTEM RESET REGISTER

Offset

Bits Description Type Default

31:9 Reserved RES - -

18h

8 SOFT_SYS_RESET

A write of a ‘1’ to this bit will force an assertion of the RESET_SYS
reset signal, resetting the device. A write of a ‘0’ has no effect.

Reads always return ‘0’.

7:0 Reserved RES - -

W- -

1h RESET

_SYS

Reset
Event

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4.9.11 PERIPHERAL RESET LOCK REGISTER

CEC1712

Offset

Bits Description Type Default

84h

31:0 PCR_RST_EN _LOCK

If the lock is enabled, the peripherals cannot be reset by writing to
the Reset enable register. Once Unlocked the Registers remain in
the unlocked state until FW re-locks it with the Lock pattern

0xA6382D4Dh = Lock Pattern
0xA6382D4Ch = Unlock Pattern

RW A6382D4DhRESET

Reset
Event

_SYS

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5.0 ARM M4 BASED EMBEDDED CONTROLLER

5.1 Introduction

This chapter contains a description of the ARM M4 Embedded Controller (EC).

®

The EC is built around an ARM
M4 is a full-featured 32-bit embedded processor, implementing the ARMv7-M THUMB instruction set in hardware.

The ARM M4 IP is configured as a Von Neumann, Byte-Addressable, Little-Endian architecture. It provides a single uni­fied 32-bit byte-level address, for a total direct addressing space of 4GByte. It has multiple bus interfaces, but these
express priorities of access to the chip-level resources (Instruction Fetch vs. Data RAM vs. others), and they do not
represent separate addressing spaces.

The ARM M4 is configured as follows.

• Little-Endian byte ordering is selected at all times

• Bit Banding is included for efficient bit-level access

• Debug features are included at “Ex+” level, defined as follows:

- DWT Unit provides 4 Data Watchpoint comparators and Execution Monitoring

• Trace features are included at “Full” level, defined as follows:

- DWT for reporting breakpoints and watchpoints

- ITM for profiling and to timestamp and output messages from instrumented firmware builds

- ETM for instruction tracing, and for enhanced reporting of Core and DWT events

- The ARM-defined HTM trace feature is not included

• NVIC Interrupt controller with 8 priority levels and up to 240 individually-vectored interrupt inputs

- A Microchip-defined Interrupt Aggregator function (at chip level) may be used to group multiple interrupts onto
single NVIC inputs

- The ARM-defined WIC feature is not included. The Microchip Interrupt Aggregator function (at chip level)
provides Wake control

• Single entry Write Buffer is incorporated

Cortex®-M4 Processor provided by Arm Ltd. (the “ARM M4 IP”). The ARM Cortex®

5.2 References

1. ARM Limited: Cortex®-M4 Technical Reference Manual, DDI0439C, 29 June 2010

2. ARM Limited: ARM®v7-M Architecture Reference Manual, DDI0403D, November 2010

3. NOTE: Filename DDI0403D_arm_architecture_v7m_reference_manual_errata_markup_1_0.pdf

4. ARM® Generic Interrupt Controller Architecture version 1.0 Architecture Specification, IHI0048A, September
2008

5. ARM Limited: AMBA® Specification (Rev 2.0), IHI0011A, 13 May 1999

6. ARM Limited: AMBA® 3 AHB-Lite Protocol Specification, IHI0033A, 6 June 2006

7. ARM Limited: AMBA® 3 ATB Protocol Specification, IHI0032A, 19 June 2006

8. ARM Limited: Cortex-M™ System Design Kit Technical Reference Manual, DDI0479B, 16 June 2011

9. ARM Limited: CoreSight™ v1.0 Architecture Specification, IHI0029B, 24 March 2005

10. ARM Limited: CoreSight™ Components Technical Reference Manual, DDI0314H, 10 July 2009

11. ARM Limited: ARM® Debug Interface v5 Architecture Specification, IHI0031A, 8 February 2006

12. ARM Limited: ARM® Debug Interface v5 Architecture Specification ADIv5.1 Supplement, DSA09-PRDC-008772,
17 August 2009

13. ARM Limited: Embedded Trace Macrocell™ (ETMv1.0 to ETMv3.5) Architecture Specification, IHI0014Q, 23
September 2011

14. ARM Limited: CoreSight™ ETM™-M4 Technical Reference Manual, DDI0440C, 29 June 2010

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CEC1712

5.3 Terminology

5.3.1 ARM IP TERMS AND ACRONYMS

•AHB

Advanced High-Performance Bus, a system-level on-chip AMBA 2 bus standard. See Reference[5], ARM Lim-

ited: AMBA® Specification (Rev 2.0), IHI0011A, 13 May 1999.

•AHB-AP

AHB Access Port, the AP option selected by Microchip for the DAP

• AHB-Lite

A Single-Master subset of the AHB bus standard: defined in the AMBA 3 bus standard. See Reference[6], ARM

Limited: AMBA® 3 AHB-Lite Protocol Specification, IHI0033A, 6 June 2006.

•AMBA

The collective term for bus standards originated by ARM Limited.

AMBA 3 defines the IP’s AHB-Lite and ATB bus interfaces.

AMBA 2 (AMBA Rev. 2.0) defines the EC’s AHB bus interface.

•AP

Any of the ports on the DAP subblock for accessing on-chip resources on behalf of the Debugger, independent
of processor operations. A single AHB-AP option is currently selected for this function.

• APB

Advanced Peripheral Bus, a limited 32-bit-only bus defined in AMBA 2 for I/O register accesses. This term is
relevant only to describe the PPB bus internal to the EC core. See Reference [5], ARM Limited: AMBA® Speci-

fication (Rev 2.0), IHI0011A, 13 May 1999.

• ARMv7

The identifying name for the general architecture implemented by the Cortex-M family of IP products.

The ARMv7 architecture has no relationship to the older “ARM 7” product line, which is classified as an “ARMv3”
architecture, and is very different.

•ATB

Interface standard for Trace data to the TPIU from ETM and/or ITM blocks, Defined in AMBA 3. See Refer­ence[7], ARM Limited: AMBA® 3 ATB Protocol Specification, IHI0032A, 19 June 2006.

• Cortex-M4

The ARM designation for the specific IP selected for this product: a Cortex M4 processor core

•DAP

Debug Access Port, a subblock consisting of

•DP

Any of the ports in the DAP subblock for connection to an off-chip Debugger. A single SWJ-DP option is currently
selected for this function, providing JTAG connectivity.

•DWT

Data Watchdog and Trace subblock. This contains comparators and counters used for data watchpoints and
Core activity tracing.

•ETM

Embedded Trace Macrocell subblock. Provides enhancements for Trace output reporting, mostly from the DWT
subblock. It adds enhanced instruction tracing, filtering, triggering and timestamping.

•FPB

FLASH Patch Breakpoint subblock. Provides either Remapping (Address substitution) or Breakpointing (Excep­tion or Halt) for a set of Instruction addresses and Data addresses. See Section 8.3 of Reference [1], ARM Lim-

ited: Cortex®-M4 Technical Reference Manual, DDI0439C, 29 June 2010.

DP and AP subblocks.

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•HTM

AHB Trace Macrocell. This is an optional subblock that is not included.

•ITM

Instrumentation Trace Macrocell subblock. Provides a HW Trace interface for “printf”-style reports from instru­mented firmware builds, with timestamping also provided.

• MEM-AP

A generic term for an AP that connects to a memory-mapped bus on-chip. For this product, this term is synony­mous with the AHB Access Port, AHB-AP.

•NVIC

Nested Vectored Interrupt Controller subblock. Accepts external interrupt inputs. See References [2], ARM Lim-

ited: ARM®v7-M Architecture Reference Manual, DDI0403D, November 2010 and [4], ARM® Generic Interrupt
Controller Architecture version 1.0 Architecture Specification, IHI0048A, September 2008.

• PPB

Private Peripheral Bus: A specific APB bus with local connectivity within the EC.

•ROM Table

A ROM-based data structure in the Debug section that allows an external Debugger and/or a FW monitor to
determine which of the Debug features are present.

•SWJ-DP

Serial Wire / JTAG Debug Port, the DP option selected by Microchip for the DAP.

•TPA

Trace Port Analyzer: any off-chip device that uses the TPIU output.

•TPIU

Trace Port Interface Unit subblock. Multiplexes and buffers Trace reports from the ETM and ITM subblocks.

•WIC

Wake-Up Interrupt Controller. This is an optional subblock that is not included.

5.3.2 MICROCHIP TERMS AND ACRONYMS

• Interrupt Aggregator

This is a module that may be present at the chip level, which can combine multiple interrupt sources onto single
interrupt inputs at the EC, causing them to share a vector.

•PMU

Processor Memory Unit, this is a module that may be present at the chip level containing any memory resources
that are closely-coupled to the CEC1712 EC. It manages accesses from both the EC processor and chip-level
bus masters.

5.4 ARM M4 IP Interfaces

This section defines only the interfaces to the ARM IP itself. For the interfaces of the entire block, see Section 5.5, "Block

External Interfaces".

The CEC1712 IP has the following major external interfaces, as shown in Figure 5-1, "ARM M4 Based Embedded Con-

troller I/O Block Diagram":

• ICode AHB-Lite Interface

• DCode AHB-Lite Interface

• System AHB-Lite Interface

• Debug (JTAG) Interface

• Trace Port Interface

• Interrupt Interface

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CEC1712

The EC operates on the model of a single 32-bit addressing space of byte addresses (4Gbytes, Von Neumann archi­tecture) with Little-Endian byte ordering. On the basis of an internal decoder (part of the Bus Matrix shown in Figure 5-

1), it routes Read/Write/Fetch accesses to one of three external interfaces, or in some cases internally (shown as the

PPB interface).

The EC executes instructions out of closely-coupled memory via the ICode Interface. Data accesses to closely-coupled
memory are handled via the DCode Interface. The EC accesses the rest of the on-chip address space via the System
AHB-Lite interface. The Debugger program in the host can probe the EC and all EC addressable memory via the JTAG
debug interface.

Aliased addressing spaces are provided at the chip level so that specific bus interfaces can be selected explicitly where
needed. For example, the EC’s Bit Banding feature uses the System AHB-Lite bus to access resources normally
accessed via the DCode or ICode interface.

Note: The EC executes most instructions in one clock cycle. If an instruction accesses code and data that are in

different RAM blocks, then it takes one clock cycle to access both code and data (done in
parallel). However, if the code and data blocks are in the same RAM block, then it takes two clock cycles
(one clock for code access and one clock for data access) since it must do it sequentially.

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CEC1712

ICode

Interface

(AHB-Lite)

DCode

Interface

(AHB-Lite)

System

Interface

(AHB-Lite)

NVIC

Nested
Vectored
Interrupt

Controller

TPIU

Trace Port Interface

ARM_M4 IP

Chip-Level

System Bus

(AMBA 2 AHB)

Processor

Core

Misc. Sideband

DAP

Debug Access Port

Mux

Chip-level JTAG TAP

ETM / ITM

Trace Outputs

Debug

Host

AMBA 2

AHB Adapt

Memory

Bus Adapt

Memory

Bus Adapt

PMC Block

(RAM / ROM)

Data

Port

Code

Port

AHB

Port

ARM_M4 EC Block

Interrupt

Aggregator

Grouped

(Summary)

Interrupts

Directly Vectored

Connections

Interrupts

Optionally

Grouped

Inputs

Unconditionally

Grouped Inputs

Processor

Clock

Divider

Chip-Level

Clock

Pulse
Sync &
Stretch

Clock

Gate

Processor Reset

Core Reset (POR)

5.5 Block External Interfaces

FIGURE 5-1: ARM M4 BASED EMBEDDED CONTROLLER I/O BLOCK DIAGRAM

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CEC1712

5.6 Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

5.6.1 POWER DOMAINS

TABLE 5-1: POWER SOURCES

Name Description

VTR_CORE The ARM M4 Based Embedded Controller is powered by VTR_CORE.

5.6.2 CLOCK INPUTS

5.6.2.1 Basic Clocking

The basic clocking comes from a free-running Clock signal provided from the chip level.

TABLE 5-2: CLOCK INPUTS

Name Description

48MHz The clock source to the EC. Division of the clock rate is determined by

the PROCESSOR_CLOCK_DIVIDE field in the Processor Clock Control

Register.

5.6.2.2 System Tick Clocking

The System Tick clocking is controlled by a signal from chip-level logic. It is the 48MHz divided by the following:

-((PROCESSOR_CLOCK_DIVIDE)x2)+1

5.6.2.3 Debug JTAG Clocking

The Debug JTAG clocking comes from chip-level logic, which may multiplex or gate this clock. See Section 5.10,

"Debugger Access Support".

5.6.2.4 Trace Clocking

The Clock for the Trace interface is identical to the 48MHz input.

5.6.3 RESETS

The reset interface from the chip level is given below.

TABLE 5-3: RESET SIGNALS

Name Description

RESET_EC The ARM M4 Based Embedded Controller is reset by RESET_EC.

5.7 Interrupts

The ARM M4 Based Embedded Controller is equipped with an Interrupt Interface to respond to interrupts. These inputs
go to the IP’s NVIC block after a small amount of hardware processing to ensure their detection at varying clock rates.
See Figure 5-1, "ARM M4 Based Embedded Controller I/O Block Diagram".

As shown in Figure 5-1, an Interrupt Aggregator block may exist at the chip level, to allow multiple related interrupts to
be grouped onto the same NVIC input, and so allowing them to be serviced using the same vector. This may allow the
same interrupt handler to be invoked for a group of related interrupt inputs. It may also be used to expand the total num­ber of interrupt inputs that can be serviced.

The NMI (Non-Maskable Interrupt) connection is tied off and not used.

5.7.1 NVIC INTERRUPT INTERFACE

The NVIC interrupt unit can be wired to up to 240 interrupt inputs from the chip level. The interrupts that are actually
connected from the chip level are defined in the Interrupt section.

All NVIC interrupt inputs can be programmed as either pulse or level triggered. They can also be individually masked,
and individually assigned to their own hardware-managed priority level.

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CEC1712

5.7.2 NVIC RELATIONSHIP TO EXCEPTION VECTOR TABLE ENTRIES

The Vector Table consists of 4-byte entries, one per vector. Entry 0 is not a vector, but provides an initial Reset value
for the Main Stack Pointer. Vectors start with the Reset vector, at Entry #1. Entries up through #15 are dedicated for
internal exceptions, and do not involve the NVIC.

NVIC entries in the Vector Table start with Entry #16, so that NVIC Interrupt #0 is at Entry #16, and all NVIC interrupt
numbers are incremented by 16 before accessing the Vector Table.

The number of connections to the NVIC determines the necessary minimum size of the Vector Table, as shown below.
It can extend as far as 256 entries (255 vectors, plus the non-vector entry #0).

A Vector entry is used to load the Program Counter (PC) and the EPSR.T bit. Since the Program Counter only expresses
code addresses in units of two-byte Halfwords, bit[0] of the vector location is used to load the EPSR.T bit instead, select­ing THUMB mode for exception handling. Bit[0] must be ‘1’ in all vectors, otherwise a UsageFault exception will be
posted (INVSTATE, unimplemented instruction set). If the Reset vector is at fault, the exception posted will be HardFault
instead.

TABLE 5-4: EXCEPTION AND INTERRUPT VECTOR TABLE LAYOUT

Tab le Ent ry

0 (none) Holds Reset Value for the Main Stack Pointer. Not a Vector.

1 1 Reset Vector (PC + EPSR.T bit)

2 2 NMI (Non-Maskable Interrupt) Vector

3 3 HardFault Vector

4 4 MemManage Vector

5 5 BusFault Vector

6 6 UsageFault Vector

7 (none) (Reserved by ARM Ltd.)

8 (none) (Reserved by ARM Ltd.)

9 (none) (Reserved by ARM Ltd.)

10 (none) (Reserved by ARM Ltd.)

11 11 SVCal l Vector

12 12 Debug Monitor Vector

13 (none) (Reserved by ARM Ltd.)

14 14 PendSV Vector

15 15 SysTick Vector

16 16 NVIC Interrupt #0 Vector

.
.
.

n + 16 n + 16 NVIC Interrupt #n Vector

.
.
.

max + 16 max + 16 NVIC Interrupt #max Vector (Highest-numbered NVIC connection.)

.
.
.

255 255 NVIC Interrupt #239 (Architectural Limit of Exception Table)

Exception

Number

.
.
.

.
.
.

.
.
.

Exception

Special Entry for Reset Stack Pointer

Core Internal Exception Vectors start here

NVIC Interrupt Vectors start here

.
.
.

.
.
.

. Table size may (but need not) extend further.
.
.

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CEC1712

5.8 Low Power Modes

The ARM processor can enter Sleep or Deep Sleep modes internally. This action will cause an output signal Clock
Required to be turned off, allowing clocks to be stopped from the chip level. However, Clock Required will still be held
active, or set to active, unless all of the following conditions exist:

• No interrupt is pending.

• An input signal Sleep Enable from the chip level is active.

• The Debug JTAG port is inactive (reset or configured not present).

In addition, regardless of the above conditions, a chip-level input signal Force Halt may halt the processor and remove
Clock Required.

5.9 Description

5.9.1 BUS CONNECTIONS

There are three bus connections used from CEC1712 EC block, which are directly related to the IP bus ports. See

Figure 5-1, "ARM M4 Based Embedded Controller I/O Block Diagram".

For the mapping of addresses at the chip level, see Section 3.0, "Device Inventory".

5.9.1.1 Closely Coupled Instruction Fetch Bus

As shown in Figure 5-1, the AHB-Lite ICode port from the IP is converted to a more conventional SRAM memory-style
bus and connected to the on-chip memory resources with routing priority appropriate to Instruction Fetches.

5.9.1.2 Closely Coupled Data Bus

As shown in Figure 5-1, the AHB-Lite DCode port from the IP is converted to a more conventional SRAM memory-style
bus and connected to the on-chip memory resources with routing priority appropriate to fast Data Read/Write accesses.

5.9.1.3 Chip-Level System Bus

As shown in Figure 5-1, the AHB-Lite System port from the IP is converted from AHB-Lite to fully arbitrated multi-master
capability (the AMBA 2 defined AHB bus: see Reference [5], ARM Limited: AMBA® Specification (Rev 2.0), IHI0011A,

13 May 1999). Using this bus, all addressable on-chip resources are available. The multi-mastering capability supports

the Microchip DMA and EMI features if present, as well as the Bit-Banding feature of the IP itself.

As also shown in Figure 5-1, the Closely-Coupled memory resources are also available through this bus connection
using aliased addresses. This is required in order to allow Bit Banding to be used in these regions, but it also allows
them to be accessed by DMA and other bus masters at the chip level.

Note: Registers with properties such as Write-1-to-Clear (W1C), Read-to-Clear and FIFOs need to be handled

with appropriate care when being used with the bit band alias addressing scheme. Accessing such a reg­ister through a bit band alias address will cause the hardware to perform a read-modify-write, and if a W1C­type bit is set, it will get cleared with such an access. For example, using a bit band access to the Interrupt
Aggregator, including the Interrupt Enables and Block Interrupt Status to clear an IRQ will clear all active
IRQs.

5.9.2 INSTRUCTION PIPELINING

There are no special considerations except as defined by ARM documentation.

5.10 Debugger Access Support

An external Debugger accesses the chip through a JTAG standard interface. The ARM Debug Access Port supports
both the 2-pin SWD (Serial Wire Debug) interface and the 4-pin JTAG interface.

As shown in Figure 5-1, "ARM M4 Based Embedded Controller I/O Block Diagram", other resources at the chip level
that share the JTAG port pins; for example chip-level Boundary Scan.

By default, debug access is disabled when the EC begins executing code. EC code enables debugging by writing the

Debug Enable Register in the EC Subsystem Registers block.

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CEC1712

TABLE 5-5: ARM JTAG ID

ARM Debug Mode JTAG ID

SW-DP (2-wire) 0x2BA01477

JTAG (4-wire) 0x4BA00477

5.10.1 DEBUG AND ACCESS PORTS (SWJ-DP AND AHB-AP SUBBLOCKS)

These two subblocks work together to provide access to the chip for the Debugger using the Debug JTAG connection,
as described in Chapter 4 of the ARM Limited: ARM® Debug Interface v5 Architecture Specification, IHI0031A, 8 Feb-

ruary 2006.

5.10.2 BREAKPOINT, WATCHPOINT AND TRACE SUPPORT

See References [11], ARM Limited: ARM® Debug Interface v5 Architecture Specification, IHI0031A, 8 February 2006
and [12], ARM Limited: ARM® Debug Interface v5 Architecture Specification ADIv5.1 Supplement, DSA09-PRDC-

008772, 17 August 2009. A summary of functionality follows.

Breakpoint and Watchpoint facilities can be programmed to do one of the following:

• Halt the processor. This means that the external Debugger will detect the event by periodically polling the state of
the EC.

• Transfer control to an internal Debug Monitor firmware routine, by triggering the Debug Monitor exception (see

Table 5-4, "Exception and Interrupt Vector Table Layout").

5.10.2.1 Instrumentation Support (ITM Subblock)

The Instrumentation Trace Macrocell (ITM) is for profiling software. This uses non-blocking register accesses, with a
fixed low-intrusion overhead, and can be added to a Real-Time Operating System (RTOS), application, or exception
handler. If necessary, product code can retain the register access instructions, avoiding probe effects.

5.10.2.2 HW Breakpoints and ROM Patching (FPB Subblock)

The Flash Patch and Breakpoint (FPB) block. This block can remap sections of ROM, typically Flash memory, to regions
of RAM, and can set breakpoints on code in ROM. This block can be used for debug, and to provide a code or data
patch to an application that requires field updates to a product in ROM.

5.10.2.3 Data Watchpoints and Trace (DWT Subblock)

The Debug Watchpoint and Trace (DWT) block provides watchpoint support, program counter sampling for performance
monitoring, and embedded trace trigger control.

5.10.2.4 Trace Interface (ETM and TPIU)

The Embedded Trace Macrocell (ETM) provides instruction tracing capability. For details of functionality and usage, see
References [13], ARM Limited: Embedded Trace Macrocell™ (ETMv1.0 to ETMv3.5) Architecture Specification,

IHI0014Q, 23 September 2011 and [14], ARM Limited: CoreSight™ ETM™-M4 Technical Reference Manual,
DDI0440C, 29 June 2010.

The Trace Port Interface Unit (TPIU) provides the external interface for the ITM, DWT and ETM.

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5.11 Delay Register

5.11.1 DELAY REGISTER

CEC1712

Offset

Bits Description Type Default

1000_0000h

31:5 Reserved RES - -

4:0 DELAY

Writing a value n, from 0h to 31h, to this register will cause the ARM
processor to stall for (n+1) microseconds (that is, from 1µS to 32µS).

Reads will return the last value read immediately. There is no delay.

R/W 0h RESET_

Reset
Event

SYS

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CEC1712

6.0 RAM AND ROM

6.1 SRAM

The CEC1712 contains two blocks of SRAM. The two SRAM blocks in the CEC1712 total 256KB. Both SRAM blocks
can be used for either program or data accesses. Performance is enhanced when program fetches and data accesses
are to different SRAM blocks, but a program will operate correctly even if both program and data accesses are targeting
the same block simultaneously.

• The first SRAM, which is optimized for code access, is 224KB

• The second SRAM, which is optimized for data access, is32KB

6.2 ROM

The CEC1712 contains a 64KB block of ROM, located at address 00000000h in the ARM address space. The ROM
contains boot code that is executed after the de-assertion of RESET_SYS. The boot code loads an executable code
image into SRAM. The ROM also includes a set of API functions that can be used for cryptographic functions, as well
as loading SRAM with programs or data.

6.3 Additional Memory Regions

6.3.1 ALIAS RAM

The Alias RAM region, starting at address 20000000h, is an alias of the SRAM located at 118000h, and is the same
size as that SRAM block. EC software can access memory in either the primary address or in the alias region; however,
access is considerably slower to the alias region. The alias region exists in order to enable the ARM bit-band region
located at address 20000000h.

6.3.2 RAM BIT-BAND REGION

The RAM bit-band region is an alias of the SRAM located at 118000h, except that each bit is aliased to bit 0 of a 32-bit
doubleword in the bit-band region. The upper 31 bits in each doubleword of the bit-band region are always 0. The bit­band region is therefore 32 times the size of the SRAM region. It can be used for atomic updates of individual bits of the
SRAM, and is a feature of the ARM architecture.

The bit-band region can only be accessed by the ARM processor. Accesses by any other bus master will cause a mem­ory fault.

6.3.3 CRYPTOGRAPHIC RAM

The cryptographic RAM is used by the cryptographic API functions in the ROM

6.3.4 REGISTER BIT-BAND REGION

The Register bit-band region is an 32-to-1 alias of the device register space starting at address 40000000h and ending
with the Host register space at 400FFFFF. Every bit in the register space is aliased to a byte in the Register bit-band
region, and like the RAM bit-band region, can be used by EC software to read and write individual register bits. Only the
EC Device Registers and the GPIO Registers can be accessed via the bit-band region.

A one bit write operation to a register bit in the bit-band region is implemented by the ARM processor by performing a
read, a bit modification, followed by a write back to the same register. Software must be careful when using bit-banding
if a register contains bits have side effects triggered by a read.

The bit-band region can only be accessed by the ARM processor. Accesses by any other bus master will cause a mem­ory fault.

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6.4 Memory Map

32KB RAM

224KB RAM

64KB Boot ROM

0x0000_0000

0x0011_8000

0x0000_FFFF

0x2000_0000

0x4000_0000

0x4001_FFFF

32KB Alias RAM

EC Device

Registers

1MB

ARM Bit Band

Alias RAM Region

0x2200_0000

Crypto RAM

0x4010_0000

0x4010_57FF

0x000E_0000

25 6 KB mo d el sta rt ad d re s s

0x0011_FFFF

256KB end address

0x4008_0000

0x4008_FFFF

GPIO Registers

0x400F_0000

0x400F_FFFF

Host Device

Registers

32MB

ARM Bit Band

Register Space

0x4200_0000

0x43FF_FFFF

0x2000_7FFF

256KB end address

0x220F_FFFF

256KB model end address

0x4007_0000

0x4007_1FFF

ESPI Protected

Segment

The memory map of the RAM and ROM is represented as follows:

FIGURE 6-1: MEMORY LAYOUT

CEC1712

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CEC1712

7.0 INTERNAL DMA CONTROLLER

7.1 Introduction

The Internal DMA Controller transfers data to/from the source from/to the destination. The firmware is responsible for
setting up each channel. Afterwards either the firmware or the hardware may perform the flow control. The hardware
flow control exists entirely inside the source device. Each transfer may be 1, 2, or 4 bytes in size, so long as the device
supports a transfer of that size. Every device must be on the internal 32-bit address space.

7.2 References

No references have been cited for this chapter.

7.3 Terminology

TABLE 7-1: TERMINOLOGY

Term Definition

DMA Transfer This is a complete DMA Transfer which is done after the Master Device

terminates the transfer, the Firmware Aborts the transfer or the DMA
reaches its transfer limit.
A DMA Transfer may consist of one or more data packets.

Data Packet Each data packet may be composed of 1, 2, or 4 bytes. The size of the data

packet is limited by the max size supported by both the source and the des­tination. Both source and destination will transfer the same number of bytes
per packet.

Channel The Channel is responsible for end-to-end (source-to-destination) Data

Packet delivery.

Device A Device may refer to a Master or Slave connected to the DMA Channel.

Each DMA Channel may be assigned one or more devices.

Master Device This is the master of the DMA, which determines when it is active.

The Firmware is the master while operating in Firmware Flow Control.
The Hardware is the master while operating in Hardware Flow Control.

The Master Device in Hardware Mode is selected by DMA Channel Con-
trol:Hardware Flow Control Device. It is the index of the Flow Control
Port.

Slave Device The Slave Device is defined as the device associated with the targeted

Memory Address.

Source The DMA Controller moves data from the Source to the Destination. The

Source provides the data. The Source may be either the Master or Slave
Controller.

Destination The DMA Controller moves data from the Source to the Destination. The

Destination receives the data. The Destination may be either the Master or
Slave Controller.

DS00003416B-page 92  2020 Microchip Technology Inc.

7.4 Interface

Internal DMA Controller

Power, Clocks and Reset

Interrupts

DMA Interface

Host Interface

Signal interface

This block is designed to be accessed internally via a registered host interface.

FIGURE 7-1: INTERNAL DMA CONTROLLER I/O DIAGRAM

CEC1712

7.5 Signal interface

This block doesn’t have any external signals that may be routed to the pin interface. This DMA Controller is intended to
be used internally to transfer large amounts of data without the embedded controller being actively involved in the trans­fer.

7.6 Host Interface

The registers defined for the Internal DMA Controller are accessible by the various hosts as indicated in Section 3.2,

"Block Overview and Base Addresses".

7.7 DMA Interface

Each DMA Master Device that may engage in a DMA transfer must have a compliant DMA interface. The following table
lists the DMA Devices in the CEC1712.

TABLE 7-2: DMA CONTROLLER DEVICE SELECTION

SMB-I2C 0 Controller 0 Slave

SMB-I2C 1 Controller 2 Slave

SMB-I2C 2 Controller 4 Slave

SMB-I2C 3 Controller 6 Slave

SMB-I2C 4Controller 8 Transmit

Note 1: The Device Number is programmed into field HARDWARE_FLOW_CONTROL_DEVICE of the DMA

Device Name

Channel N Control Register register.

Device Number

(Note 1)

1Master

3Master

5Master

7Master

9Receive

Controller Source

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CEC1712

TABLE 7-2: DMA CONTROLLER DEVICE SELECTION (CONTINUED)

Device Name

QMSPI Controller 10 Transmit

Note 1: The Device Number is programmed into field HARDWARE_FLOW_CONTROL_DEVICE of the DMA

Channel N Control Register register.

TABLE 7-3: DMA CONTROLLER MASTER DEVICES SIGNAL LIST

Device Name

SMB-I2C 0 Controller 0 SMB-I2C_SD-

SMB-I2C 1 Controller 2 SMB-I2C_SD-

SMB-I2C 2 Controller 4 SMB-I2C_SD-

Dev

Num

Device Signal Name Direction Description

MA_Req

SMB-I2C_SD-

MA_Term

SMB-I2C_SDMA_-

Done

1 SMB-I2C_MD-

MA_Req

SMB-I2C_MD-

MA_Term

SMB-I2C_MDMA_-

Done

MA_Req

SMB-I2C_SD-

MA_Term

SMB-I2C_SDMA_-

Done

3 SMB-I2C_MD-

MA_Req

SMB-I2C_MD-

MA_Term

SMB-I2C_MDMA_-

Done

MA_Req

SMB-I2C_SD-

MA_Term

SMB-I2C_SDMA_-

Done

5 SMB-I2C_MD-

MA_Req

SMB-I2C_MD-

MA_Term

SMB-I2C_MDMA_-

Done

Device Number

(Note 1)

11 Receive

INPUT DMA request control from SMB-I2C Slave

INPUT DMA termination control from SMB-I2C

OUTPUT DMA termination control from DMA Con-

INPUT DMA request control from SMB-I2C Mas-

INPUT DMA termination control from SMB-I2C

OUTPUT DMA termination control from DMA Con-

INPUT DMA request control from SMB-I2C Slave

INPUT DMA termination control from SMB-I2C

OUTPUT DMA termination control from DMA Con-

INPUT DMA request control from SMB-I2C Mas-

INPUT DMA termination control from SMB-I2C

OUTPUT DMA termination control from DMA Con-

INPUT DMA request control from SMB-I2C Slave

INPUT DMA termination control from SMB-I2C

OUTPUT DMA termination control from DMA Con-

INPUT DMA request control from SMB-I2C Mas-

INPUT DMA termination control from SMB-I2C

OUTPUT DMA termination control from DMA Con-

Controller Source

channel.

Slave channel.

troller to Slave channel.

ter channel.

Master channel.

troller to Master channel.

channel.

Slave channel.

troller to Slave channel.

ter channel.

Master channel.

troller to Master channel.

channel.

Slave channel.

troller to Slave channel.

ter channel.

Master channel.

troller to Master channel.

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CEC1712

TABLE 7-3: DMA CONTROLLER MASTER DEVICES SIGNAL LIST (CONTINUED)

Device Name

SMB-I2C 3 Controller 6 SMB-I2C_SD-

SMB-I2C 4 Controller 8 SMB-I2C_SD-

Quad SPI Controller 10 QSPI_TDMA_Req INPUT DMA request control from Quad SPI TX

Dev

Num

Device Signal Name Direction Description

INPUT DMA request control from SMB-I2C Slave

MA_Req

SMB-I2C_SD-

MA_Term

SMB-I2C_SDMA_-

Done

7 SMB-I2C_MD-

MA_Req

SMB-I2C_MD-

MA_Term

SMB-I2C_MDMA_-

Done

MA_Req

SMB-I2C_SD-

MA_Term

SMB-I2C_SDMA_-

Done

9 SMB-I2C_MD-

MA_Req

SMB-I2C_MD-

MA_Term

SMB-I2C_MDMA_-

Done

QSPI_TDMA_Term INPUT DMA termination control from Quad SPI

QMSPI_TDMA_-

Done

11 QSPI_RDMA_Req INPUT DMA request control from Quad SPI RX

QSPI_RDMA_Term INPUT DMA termination control from Quad SPI

QMSPI_RDMA_-

Done

INPUT DMA termination control from SMB-I2C

OUTPUT DMA termination control from DMA Con-

INPUT DMA request control from SMB-I2C Mas-

INPUT DMA termination control from SMB-I2C

OUTPUT DMA termination control from DMA Con-

INPUT DMA request control from SMB-I2C Slave

INPUT DMA termination control from SMB-I2C

OUTPUT DMA termination control from DMA Con-

INPUT DMA request control from SMB-I2C Mas-

INPUT DMA termination control from SMB-I2C

OUTPUT DMA termination control from DMA Con-

OUTPUT DMA termination control from DMA Con-

OUTPUT DMA termination control from DMA Con-

channel.

Slave channel.

troller to Slave channel.

ter channel.

Master channel.

troller to Master channel.

channel.

Slave channel.

troller to Slave channel.

ter channel.

Master channel.

troller to Master channel.

channel.

TX channel.

troller to Quad SPI TDMA Channel.

channel.

RX channel.

troller to Quad SPI RDMA Channel.

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CEC1712

7.8 Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

7.8.1 POWER DOMAINS

TABLE 7-4: POWER SOURCES

Name Description

VTR_CORE This power well sources the registers and logic in this block.

7.8.2 CLOCK INPUTS

TABLE 7-5: CLOCK INPUTS

Name Description

48MHz This clock signal drives selected logic (e.g., counters).

7.8.3 RESETS

TABLE 7-6: RESET SIGNALS

Name Description

RESET_SYS This reset signal resets all of the registers and logic in this block.

RESET This reset is generated if either the RESET_SYS is asserted or the

SOFT_RESET bit is asserted.

7.9 Interrupts

This section defines the Interrupt Sources generated from this block.

TABLE 7-7: INTERRUPTS

Source Description

DMAx Direct Memory Access Channel x

This signal is generated by the STATUS_DONE bit.

7.10 Low Power Modes

The Internal DMA Controller may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.

When the block is commanded to go to sleep it will place the DMA block into sleep mode only after all transactions on
the DMA have been completed. For Firmware Flow Controlled transactions, the DMA will wait until it hits its terminal
count and clears the Go control bit. For Hardware Flow Control, the DMA will go to sleep after either the terminal count
is hit, or the Master device flags the terminate signal.

7.11 Description

The CEC1712 features a 12 channel DMA controller. The DMA controller can autonomously move data from/to any
DMA capable master device to/from any populated memory location. This mechanism allows hardware IP blocks to
transfer large amounts of data into or out of memory without EC intervention.

The DMA has the following characteristics:

• Data is only moved 1 Data Packet at a time

• Data only moves between devices that are accessible via the internal 32-bit address space

• The DMA Controller has 12 DMA Channels

• Each DMA Channel may be configured to communicate with any DMA capable device on the 32-bit internal
address space. Each device has been assigned a device number. See Section 7.7, "DMA Interface".

The controller will access SRAM buffers only with incrementing addresses (that is, it cannot start at the top of a buffer,
nor does it handle circular buffers automatically). The controller does not handle chaining (that is, automatically starting
a new DMA transfer when one finishes).

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CEC1712

7.11.1 CONFIGURATION

The DMA Controller is enabled via the AC TIVATE bit in DMA Main Control Register register.

Each DMA Channel must also be individually enabled via the CHANNEL_ACTIVATE bit in the DMA Channel N Activate

Register to be operational.

Before starting a DMA transaction on a DMA Channel the host must assign a DMA Master to the channel via HARD-

WARE_FLOW_CONTROL_DEVICE. The host must not configure two different channels to the same DMA Master at

the same time.

Data will be transfered between the DMA Master, starting at the programmed DEVICE_ADDRESS, and the targeted
memory location, starting at the MEMORY_START_ADDRESS. The address for either the DMA Master or the targeted
memory location may remain static or it may increment. To enable the DMA Master to increment its address set the

INCREMENT_DEVICE_ADDRESS bit. To enable the targeted memory location to increment its addresses set the
INCREMENT_MEMORY_ADDRESS. The DMA transfer will continue as long as the target memory address being

accessed is less than the MEMORY_END_ADDRESS. If the DMA Controller detects that the memory location it is
attempting to access on the Target is equal to the MEMORY_END_ADDRESS it will notify the DMA Master that the
transaction is done. Otherwise the Data will be transferred in packets. The size of the packet is determined by the

TRANSFER_SIZE.

7.11.2 OPERATION

The DMA Controller is designed to move data from one memory location to another.

7.11.2.1 Establishing a Connection

A DMA Master will initiate a DMA Transaction by requesting access to a channel. The DMA arbiter, which evaluates
each channel request using a basic round robin algorithm, will grant access to the DMA master. Once granted, the chan­nel will hold the grant until it decides to release it, by notifying the DMA Controller that it is done.

If Firmware wants to prevent any other channels from being granted while it is active it can set the LOCK_CHANNEL bit.

7.11.2.2 Initiating a Transfer

Once a connection is established the DMA Master will issue a DMA request to start a DMA transfer. If Firmware wants
to have a transfer request serviced it must set the RUN bit to have its transfer requests serviced.

Firmware can initiate a transaction by setting the TRANSFER_GO bit. The DMA transfer will remain active until either
the Master issues a Terminate or the DMA Controller signals that the transfer is DONE. Firmware may terminate a trans-
action by setting the TRANSFER_ABORT bit.

Note: Before initiating a DMA transaction via firmware the hardware flow control must be disabled via the DIS-

ABLE_HARDWARE_FLOW_CONTROL bit.

Data may be moved from the DMA Master to the targeted Memory address or from the targeted Memory Address to the
DMA Master. The direction of the transfer is determined by the TRANSFER_DIRECTION bit.

Once a transaction has been initiated firmware can use the STATUS_DONE bit to determine when the transaction is
completed. This status bit is routed to the interrupt interface. In the same register there are additional status bits that
indicate if the transaction completed successfully or with errors. These bits are OR’d together with the STATUS_DONE
bit to generate the interrupt event. Each status be may be individually enabled/disabled from generating this event.

7.11.2.3 Reusing a DMA Channel

After a DMA Channel controller has completed, firmware must clear both the DMA Channel N Control Register and the

DMA Channel N Interrupt Status Register. After both have been cleared to 0, the Channel Control Register can then be

configured for the next transaction.

7.11.2.4 CRC Generation

A CRC generator can be attached to a DMA channel in order to generate a CRC on the data as it is transfered from the
source to the destination. The CRC used is the CRC-32 algorithm used in IEEE 802.3 and many other protocols, using
the polynomial x
place in parallel with the data transfer; enabling CRC will not increase the time to complete a DMA transaction. The CRC
generator has the optional ability to automatically transfer the generated CRC to the destination after the data transfer
has completed.

32

+ x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1. The CRC generation takes

 2020 Microchip Technology Inc. DS00003416B-page 97

CEC1712

CRC generation is subject to a number of restrictions:

• The CRC is only generated on channels that have the CRC hardware. See Table 7-10, "Channel Register Sum-

mary" for a definition of which channels have the ability to generate a CRC

• The DMA transfer must be 32-bits

• If CRC is enabled, DMA interrupts are inhibited until the CRC is completed, including the optional post-transfer
copy of it is enabled

• The CRC must be initialized by firmware. The value FFFFFFFFh must be written to the Data Register in order to
initialize the generator for the standard CRC-32-IEEE algorithm

• The CRC will

7.11.2.5 Block Fill Option

A Fill engine can be attached to a DMA channel in order to provide a fast mechanism to set a block of memory to a fixed
value (for example, clearing a block of memory to zero). The block fill operation runs approximately twice as fast as a
memory-to-memory copy.

In order to fill memory with a constant value, firmware must configure the channel in the following order:

1. Set the DMA Channel N Fill Data Register to the desired fill value

2. Set the DMA Channel N Fill Enable Register to ‘1b’, enabling the Fill engine

3. Set the DMA Channel N Control Register to the following values:

- RUN = 0

- TRANSFER_DIRECTION = 0 (memory destination)

- INCREMENT_MEMORY_ADDRESS = 1 (increment memory address after each transfer)

- INCREMENT_DEVICE_ADDRESS = 1

- DISABLE_HARDWARE_FLOW_CONTROL = 1 (no hardware flow control)

- TRANSFER_SIZE = 1, 2 or 4 (as required)

- TRANSFER_ABORT = 0

- TRANSFER_GO = 1 (this starts the transfer)

bebit‐orderreversedandinvertedas required by the CRC algorithm

7.12 EC Registers

The DMA Controller consists of a Main Block and a number of Channels. Table 7-9, "Main Register Summary" lists the
registers in the Main Block and Table 7-10, "Channel Register Summary" lists the registers in each channel. Addresses
for each register are determined by adding the offset to the Base Address for the DMA Controller Block in the Block
Overview and Base Address Table in Section 3.0, "Device Inventory".

Registers are listed separately for the Main Block of the DMA Controller and for a DMA Channel. Each Channel has the
same set of registers. The absolute register address for registers in each channel are defined by adding the Base
Address for the DMA Controller Block, the Offset for the Channel shown in Table 7-8, "DMA Channel Offsets" to the
offsets listed in Table 7-9, "Main Register Summary" or Table 7-10, "Channel Register Summary".

:

TABLE 7-8: DMA CHANNEL OFFSETS

Instance Name Channel Number Offset

DMA Controller Main Block 000h

DMA Controller 0 040h

DMA Controller 1 080h

DMA Controller 2 0C0h

DMA Controller 3 100h

DMA Controller 4 140h

DMA Controller 5 180h

DMA Controller 6 1C0h

DMA Controller 7 200h

DMA Controller 8 240h

DMA Controller 9 280h

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TABLE 7-8: DMA CHANNEL OFFSETS (CONTINUED)

Instance Name Channel Number Offset

DMA Controller 10 2C0h

DMA Controller 11 300h

TABLE 7-9: MAIN REGISTER SUMMARY

Offset Register Name

00h DMA Main Control Register

04h DMA Data Packet Register

7.12.1 DMA MAIN CONTROL REGISTER

CEC1712

Offset

Bits Description Type Default

00h

7:2 Reserved RES - -

1 SOFT_RESET

Soft reset the entire module.

This bit is self-clearing.

0 ACTI VATE

Enable the blocks operation.

1=Enable block. Each individual channel must be enabled separately.
0=Disable all channels.

W0b -

R/WS 0b RESET

7.12.2 DMA DATA PACKET REGISTER

Offset

Bits Description Type Default

04h

31:0 DATA_PACKET

Debug register that has the data that is stored in the Data Packet.
This data is read data from the currently active transfer source.

R 0000h -

Reset
Event

Reset
Event

TABLE 7-10: CHANNEL REGISTER SUMMARY

Offset

00h DMA Channel N Activate Register

04h DMA Channel N Memory Start Address Register

08h DMA Channel N Memory End Address Register

0Ch DMA Channel N Device Address

10h DMA Channel N Control Register

14h DMA Channel N Interrupt Status Register

Note 1: The letter ‘N’ following DMA Channel indicates the Channel Number. Each Channel

implemented will have these registers to determine that channel’s operation.

2: These registers are only present on DMA Channel 0. They are reserved on all other

channels.

3: These registers are only present on DMA Channel 1. They are reserved on all other

channels.

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Register Name

(Note 1)

CEC1712

TABLE 7-10: CHANNEL REGISTER SUMMARY (CONTINUED)

Offset

18h DMA Channel N Interrupt Enable Register

1Ch TEST

20h

(Note 2)

24h

(Note 2)

28h

(Note 2)

2Ch

(Note 2)

20h

(Note 3)

24h

(Note 3)

28h

(Note 3)

2Ch

(Note 3)

Note 1: The letter ‘N’ following DMA Channel indicates the Channel Number. Each Channel

2: These registers are only present on DMA Channel 0. They are reserved on all other

3: These registers are only present on DMA Channel 1. They are reserved on all other

DMA Channel N CRC Enable Register

DMA Channel N CRC Data Register

DMA Channel N CRC Post Status Register

TEST

DMA Channel N Fill Enable Register

DMA Channel N Fill Data Register

DMA Channel N Fill Status Register

TEST

implemented will have these registers to determine that channel’s operation.

channels.

channels.

Register Name

(Note 1)

7.12.3 DMA CHANNEL N ACTIVATE REGISTER

Offset

Bits Description Type Default

00h

7:1 Reserved RES - -

0 CHANNEL_ACTIVATE

Enable this channel for operation.
The DMA Main Control:Activate must also be enabled for this chan­nel to be operational.

R/W 0h RESET

Reset
Event

DS00003416B-page 100  2020 Microchip Technology Inc.