Page 1
March 1997
CDP1883,
CDP1883C
CMOS 7-Bit Latch
and Decoder Memory Interfaces
Features
• Performs Memory Address Latch and Decoder Functions Multiplexed or Non-Multiplexed
• Interfaces Directly with the CDP1800-Series Microprocessors
• Allows Decoding for Systems Up to 32K Bytes
Ordering Information
TEMP.
5V 10V
CDP1883CE CDP1883E -40oC to
RANGE PACKAGE
+85oC
PDIP E20.3
PKG.
NO.
Pinout
Description
The CDP1883 is a CMOS 7-bit memory latch and decoder
circuit intended for use in CDP1800-series microprocessor
systems. It can serve as a direct interface between the multiplexed address bus of this system and up to four 8K x 8-bit
memories to implement a 32K-byte memory system. With
four 4K x 8-bit memories, a 16K-byte system can be
decoded.
The device is also compatible with non-multiplexed address
bus microprocessors. By connecting the clock input to V
the latches are in the data-following mode and the decoded
outputs can be used in general-purpose memory-system
applications.
The CDP1833 is compatible with CDP1800-series microprocessors operating at maximum clock frequency.
The CDP1883 and CDP1883C are functionally identical.
They differ in that the CDP1883 has a recommended operating voltage range of 4V to 10.5V and the C version has a
recommended operating voltage range of 4V to 6.5V.
The CDP1883 and CDP1883C are supplied in 20 lead dualin-line plastic packages (E Suffix).
DD
,
CDP1883, CDP1883C
MA0
MA1
MA2
MA3
MA4
MA5
MA6
CE
V
SS
1
2
3
4
5
6
7
8
9
10
CLOCK
(PDIP)
TOP VIEW
V
20
DD
A8
19
A9
18
A10
17
A11
16
A12
15
CS0
14
CS1
13
12
CS2
CS3
11
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
4-129
File Number 1507.2
Page 2
CDP1883, CDP1883C
Absolute Maximum Ratings Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1883C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
Thermal Resistance (Typical) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Device Dissipation Per Output Transistor
TA = Full Package Temperature Range. . . . . . . . . . . . . . .100mW
Operating Temperature Range (TA)
Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC
Storage Temperature Range (T
). . . . . . . . . . . .-65oC to +150oC
STG
Lead Temperature (During Soldering)
At distance 1/16 ±1/32 In. (1.59 ± 0.79mm)
from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Recommended Operating Conditions At T
= Full Package Temperature Range. For maximum reliability, operating conditions
A
should be selected so that operation is always within the following ranges:
CDP1883 CDP1883C
PARAMETER SYMBOL
UNITSMIN MAX MIN MAX
DC Operating Voltage Range 4 10.5 4 6.5 V
Input Voltage Range V
Static Electrical Specifications At T
= -40oC to +85oC, VDD± 5%, Except as Noted:
A
SS
V
DD
V
SS
V
DD
CONDITIONS CDP1883 CDP1883C
PARAMETER SYMBOL
Quiescent Device
I
DD
V
O
(V)
- 0, 5 5 - 1 10 - 5 50 µA
V
(V)
V
IN
DD
(V) MIN
(NOTE 1)
TYP MAX MIN
(NOTE 1)
TYP MAX
Current
- 0, 10 10 - 10 100 - - - µA
Output Low Drive
I
OL
0.4 0, 5 5 1.6 3.2 - 1.6 3.2 - mA
(Sink) Current
0.5 0, 10 10 3.2 6.4 - - - - mA
Output High Drive
I
OH
4.6 0, 5 5 -1.15 -2.3 - -1.15 -2.3 - mA
(Source) Current
9.5 0, 10 10 -2.3 -4.6 - - - - mA
Output Voltage
V
OL
- 0, 5 5 - 0 0.1 - 0 0.1 V
Low-Level (Note 2)
- 0, 10 10 - 0 0.1 - - - V
V
UNITS
Output Voltage
High-Level (Note 2)
Input Low Voltage V
Input High Voltage V
Input Leakage Current I
Operating Current
(Note 3)
V
I
DD1
OH
- 0, 5 5 4.9 5 - 4.9 5 - V
- 0, 10 10 9.9 10 - - - - V
0.5, 4.5 - 5 - - 1.5 - - 1.5 V
IL
0.5, 9.5 - 10 - - 3 - - - V
0.5, 4.5 - 5 3.5 - - 3.5 - - V
IH
0.5, 9.5 - 10 7 - - - - - V
IN
Any
0, 5 5 - - ±1- - ±1 µA
Input
0, 10 10 - - ±2- - -µA
0, 5 0, 5 5 - - 2 - - 2 mA
0, 10 0, 10 10 - - 4 - - - mA
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Page 3
CDP1883, CDP1883C
Static Electrical Specifications At T
= -40oC to +85oC, VDD± 5%, Except as Noted: (Continued)
A
CONDITIONS CDP1883 CDP1883C
PARAMETER SYMBOL
Minimum Data
V
O
(V)
V
DR
V
IN
(V)
VDD = V
V
DR
DD
(V) MIN
- 2 2.4 - 2 2.4 V
(NOTE 1)
TYP MAX MIN
Retention Voltage
Data Retention Current I
Input Capacitance C
Output Capacitance C
DR
IN
OUT
VDD = 2.4V - 0.01 1 - 0.5 5 µA
- - - - 5 7.5 - 5 7.5 pF
- - - - 10 15 - 10 15 pF
NOTES:
1. Typical values are for TA = +25oC.
2. IOL = IOH = µA
3. Operating current measured at 200kHz for VDD = 5V and 400kHz for VDD = 10V, with outputs open circuit.
Functional Diagram
2
MA0
(NOTE 1)
TYP MAX
A8
19DCQ
UNITS
MA1
MA2
MA3
MA4
MA5
MA6
CLOCK
3
4
5
6
7
8
1
DCQ
DCQ
DCQ
DCQ
DCQ
Q
DCQ
Q
A9
18
A10
17
A11
16
A12
15
CS0
14
13
CS1
12
CS2
11
CS3
CE
V
20
=
DD
9
V
10
=
SS
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Page 4
CDP1883, CDP1883C
Signal Descriptions/Pin Functions
CLOCK: Latch Input Control - a high on the clock input will
allow data to pass through the latch to the output pin. Data is
latched on the high-to-low transition of the clock input. This
pin is connected to TPA in CDP1800-series systems and tied
to V
for other applications.
DD
MA0 - MA4: Address inputs to the high-byte address
latches.
MA5 - MA6: High byte address inputs decoded to produce
chip selects
CE: CHIP ENABLE input - A low on this pin will enable the
chip select decoder. A high on this pin forces
CS2, and CS3 outputs to a high (false) state.
A8 - A12: Latched high-byte address outputs.
CS0 - CS3: One of four latched and decoded Chip Select
outputs.
V
, VSS: Power and ground pins, respectively.
DD
CE CLK MA5 MA6 CS0 CS1 CS2 CS3
01000111
01101011
01011101
01111110
CS0 - CS3.
CS0, CS1,
TRUTH TABLE
INPUTS OUTPUTS
TRUTH TABLE
INPUTS OUTPUTS
CE CLK MA0 - 4 A8 - A12
X11 1
X10 0
X 0 X Previous State
X = Don’t Care
Application Information
The CDP1883 and CDP1883C can be interfaced, without
external components, with CDP1800-series microprocessor
systems. These microprocessors feature a multiplexed
address bus and provide an address latch signal (TPA) that
is used as the clock input of the CDP1883. See Figure 2 and
Figure 3.
This signal is used to latch 7 bits of the high-order address.
The lower five high-order address inputs are latched and
held to be used with the eight lower-order address inputs to
access an 8K x 8-bit memory. The two upper high-order
address inputs are latched and decoded for use as chip
selects.
The latched address and decoding functions of the
CDP1883 and CDP1883C allow them to operate with 32Kbyte memory systems. In addition, smaller memory systems
can be configured with 4K x 8-bit or smaller memories, or a
mix of memory sizes up to 8K x 8-bit.
0 0 X X Previous State
1XXX1111
Dynamic Electrical Specifications T
PARAMETER
Minimum Setup Time,
Memory Address to CLOCK
Minimum Hold Time,
Memory Address After CLOCK
Minimum CLOCK Pulse Width t
PROPAGATION DELAY TIMES
Chip Enable to Chip Select t
CLOCK to Chip Select t
= -40oC to +85oC, VDD± 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF.
A
See Figure 1
V
DD
(V)
t
MACL
t
CLMA
CLCL
CECS
CLCS
5 - 10 35 - 10 35 ns
10 - 8 25 - - - ns
5-825-825ns
10 - 8 25 - - - ns
5 - 50 75 - 50 75 ns
10 - 25 40 - - - ns
5 - 75 150 - 75 150 ns
10 - 45 100 - - - ns
5 - 100 175 - 100 175 ns
10 - 65 125 - - - ns
CDP1883 CDP1883C
(NOTE 1)
TYP
(NOTE 2)
MAX MIN
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITSMIN
4-132
Page 5
CDP1883, CDP1883C
Dynamic Electrical Specifications T
= -40oC to +85oC, VDD± 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF.
A
See Figure 1 (Continued)
CDP1883 CDP1883C
PARAMETER
CLOCK to Address t
CLA
V
DD
(V)
5 - 100 175 - 100 175 ns
(NOTE 1)
TYP
(NOTE 2)
MAX MIN
10 - 65 125 - - - ns
Memory Address to Chip Select t
MACS
5 - 100 175 - 100 175 ns
10 - 75 125 - - - ns
Memory Address to Address t
MAA
5 - 80 125 - 80 125 ns
10 - 40 60 - - - ns
NOTES:
1. Typical values are for TA= 25oC.
2. Maximum limits of minimum characteristics are the values above which all devices function.
CE
CS0, CS1, CS2, CS3
CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY
(A)
VALID CHIP ENABLE
t
CECS
t
CECS
(NOTE 1)
TYP
(NOTE 2)
MAX
UNITSMIN
MA0 - MA5
t
CLOCK
CS0, CS1, CS2, CS3
A8 - A12
MACL
t
CLCL
t
CLA
(B) MEMORY ADDRESS SETUP AND HOLD TIME
t
CLMA
t
CLCS
t
MACS
t
MAA
t
MAA
t
MACS
FIGURE 1. CDP1883 TIMING WAVEFORMS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-133
Page 6
CDP1883, CDP1883C
ADDRESS BUS
WAIT
CLR
CDP1800
SERIES
CPU
MRD
MWR
TPA
A0 - A7
TPA
CDP1837C
4K x 8
ROM
CEO
MRD
DATA BUS
A0 - A6
CLK
CDP1883
LATCH/
DECODER
CE
CS0
CS1
CS2
CS3
A8 - A12
A0 - A7
CDM6264
8K x 8
RAM
CE
OE
WE
FIGURE 2. MINIMUM CDP1800-SYSTEM USING THE CDP1883 INTERFACE WITH AN 8K X 8-BIT MEMORY
CDP1883
LATCH/
DECODER
CS3
CLK
CE
MA0 - MA6
CS2
CS1
CS0
A8 - A12
CLR
TPA
CDP1800
SERIES
CPU
MRD
WAIT
ADDRESS BUS
ADDRESS BUS
A8 - A12
CE
A0 - A7
CDM5364
8K x 8
ROM
A8 - A12
A0 - A7
CDM5364
8K x 8
DATA BUS
ROM
CE
A8 - A12
CE
A0 - A7
CDM5364
8K x 8
ROM
FIGURE 3. 32K-BYTE ROM SYSTEM USING THE CDP1883
4-134
A8 - A12
CE
A0 - A7
CDM5364
8K x 8
ROM
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