Datasheet CDP1822C, CDP1822 Datasheet (Intersil Corporation)

March 1997

CDP1822,

CDP1822C

256-Word x 4-Bit

LSI Static RAM

Features

• Low Operating Current

= 5V, Cycle Time 1µs . . . . . . . . . . . . . . . . . . 8mA

-V

DD

• Industry Standard Pinout

• Two Chip-Select Inputs-Simple Memory Expansion

• Memory Retention for Standby Battery Voltage of 2V
Minimum

• Output-Disable for Common I/O Systems

• Three-State Data Output for Bus-Oriented Systems

• Separate Data Inputs and Outputs

Ordering Information

5V 10V P ACKAGE TEMP. RANGE

o

CDP1822CE CDP1822E PDIP -40
CDP1822CEX CDP1822EX Burn-In
CDP1822CD CDP1822D SBDIP -40oC to +85oC
CDP1822CDX - Burn-In

C to +85oC

PKG.

NO.

E22.4
E22.4
D22.4A
D22.4A

Description

The CDP1822 and CDP1822C are 256-word by 4-bit static
random-access memories designed for use in memory sys­tems where high speed, low operating current, and simplicity
in use are desirable. The CDP1822 features high speed and
a wide operating voltage range. Both types have separate
data inputs and outputs and utilize single power supplies of
4V to 6.5V for the CDP1822C and 4V to 10.5V for the
CDP1822.

Two Chip-Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output sys­tems. The Output Disable input allows these RAMs to be
used in common data Input/Output systems by forcing the
output into a high-impedance state during a write operation
independent of the Chip-Select input condition. The output
assumes a high-impedance state when the Output Disable is
at high level or when the chip is deselected by
CS2.

The high noise immunity of the CMOS technology is pre­served in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.

CS1 and/or

Pinout

CDP1822, CDP1822C

(PDIP, SBDIP)

TOP VIEW

1

A3

2

A2

3

A1

4

A0

5

A5

6

A6

7

A7

8

V

SS

9

DI1

10

DO1

11

DI2

OPERATIONAL MODES

INPUTS

CHIP

V

22

DD

21

A4
R/

W

20
19

CS1

18

O. D.

17

CS2

16

DO4

15

DI4

14

DO3

13

DI3

12

DO2

MODE

Read 0 1 0 1 Read
Write 0 1 0 0 Data In
Write 0 1 1 0 High

Standby 1 X X X High

Standby X 0 X X High

Output
Disable

NOTE:
Logic 1 = High, Logic 0 = Low, X = Don’t Care.

SELECT

1

(CS1)

X X 1 X High

CHIP

SELECT

2

(CS2)

OUTPUT

DISABLE

(OD)

READ/
WRITE

(R/W)

OUTPUT

Imped­ance

Imped­ance

Imped­ance

Imped­ance

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

6-11

File Number 1074.2

CDP1822, CDP1822C

Absolute Maximum Ratings Thermal Information

DC Supply Voltage Range, (VDD)

(All Voltages Referenced to VSS Terminal)

CDP1822 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V

CDP1822C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Recommended Operating Conditions At T

= Full Package Temperature Range. For maximum reliability, operating conditions

A

should be selected so that operation is always within the following ranges:

Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 75 N/A

SBDIP Package. . . . . . . . . . . . . . . . . . 80 21

Maximum Operating Temperature Range (TA)

Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC

Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC

Maximum Junction Temperature

Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC

Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

Storage Temperature Range (T

TA = -40oC to +60oC (Package Type E) . . . . . . . . . . . . . . 500mW

TA = +60oC to +85oC (Package Type E). . . . . .Derate Linearly at

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12mW/oC to 200mW

Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . . 300oC

LIMITS

CDP1822 CDP1822C

). . . . . . . . . . . .-65oC to +150oC

STG

PARAMETER SYMBOL

MIN MAX MIN MAX

UNITS

DC Operating Voltage Range 4 10.5 4 6.5 V
Input Voltage Range V

Static Electrical Specifications At T

= -40oC to +85oC, Except as Noted

A

SS

V

DD

V

SS

V

DD

CONDITIONS LIMITS

CDP1822 CDP1822C

PARAMETER SYMBOL

Quiescent Device
Current

Output Low (Sink)
Current

Output High (Source)
Current

Output Voltage
Low-Level

Output Voltage
High-Level

Input Low Voltage V

V

O

(V)

I

DD

- 0, 5 5 - - 500 - - 500 µA

- 0, 10 10 - - 1000 - - - µA

I

OL

0.4 0, 5 5 2 4 - 2 4 - mA

0.5 0, 10 10 4.5 9 - - - - mA

I

OH

4.6 0, 5 5 -1 -2 - -1 -2 - mA

9.5 0, 10 10 -2.2 -4.4 - - - - mA

V

OL

- 0, 5 5 - 0 0.1 - 0 0.1 V

- 0, 10 10 - 0 0.1 - - - V

V

OH

- 0, 5 5 4.9 5 - 4.9 5 - V

- 0, 10 10 9.9 10 - - - - V

0.5, 4.5 - 5 - - 1.5 - - 1.5 V

IL

V

(V)

V

IN

DD

(V)

MIN

(NOTE 1)

TYP MAX MIN

(NOTE 1)

TYP MAX

0.5, 9.5 - 10 - - 3 - - - V

Input High Voltage V

0.5, 9.5 - 5 3.5 - - 3.5 - - V

IH

0.5, 9.5 - 10 7 - - - - - V

Input Leakage Current I

IN

- 0, 5 5 - - ±5- - ±5 µA

- 0, 10 10 - - ±10 - - - µA

V

UNITS

6-12

CDP1822, CDP1822C

Static Electrical Specifications At T

= -40oC to +85oC, Except as Noted (Continued)

A

CONDITIONS LIMITS

PARAMETER SYMBOL

Operating Current
(Note 2)

Three-State Output
Leakage Current

Input Capacitance C
Output Capacitance C

I

DD1

I

OUT

OUT

V

O

(V)

- 0, 5 5 - 4 8 - 4 8 mA

- 0, 10 10 - 8 16 - - - mA

0, 5 0, 5 5 - - ±5- - ±5 µA

0, 10 0, 10 10 - - ±10 - - - µA

IN

----57.5-57.5pF

----1015-1015pF

V

(V)

IN

NOTES:

1. Typical values are for TA = +25oC and nominal VDD.

2. Outputs open circuited; Cycle time = 1µs.

Dynamic Electrical Specifications At T

+ -40 to +85oC, VDD±5%, Input tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD,

A

CL = 100 pF

TEST

CONDITIONS LIMITS

V

PARAMETER

DD

(V)

Read Cycle Times (Figure 1)
Read Cycle t

RC

5 450 - - 450 - - ns

10 250 - - - - - ns

Access from Address t

AA

5 - 250 450 - 250 450 ns

10 - 150 250 - - - ns

Output Valid from Chip-Select 1 t

DOA1

5 - 250 450 - 250 450 ns

10 - 150 250 - - - ns

Output Valid from Chip-Select 2 t

DOA2

5 - 250 450 - 250 450 ns

10 - 150 250 - - - ns

Output Valid from Output Disable t

DOA3

5 - - 200 - - 200 ns

10 - - 110 - - - ns

Output Hold from Chip-Select 1 t

DOH1

520--20--ns

10 20 - - - - - ns

Output Hold from Chip-Select 2 t

DOH2

520--20--ns

10 20 - - - - - ns

Output Hold from Output Disable t

DOH3

520--20--ns

10 20 - - - - - ns

NOTES:

1. Time required by a limit device to allow for indicated function.

2. Typical values are for TA = 25oC and nominal VDD.

V

DD

(V)

(NOTE 1)

MIN

CDP1822 CDP1822C

(NOTE 1)

MIN

TYP MAX MIN

CD1822 CDP1822C

(NOTE 2)

TYP MAX

(NOTE 1)

MIN

(NOTE 2)

(NOTE 1)

TYP MAX

TYP MAX

UNITS

UNITS

6-13

A0 - A7

CHIP-SELECT 1

CDP1822, CDP1822C

t

RC

t

DOA1

t

DOH1

CHIP-SELECT 2

OUTPUT DISABLE

WRITE

READ/

DATA OUT

HIGH

IMPEDANCE

FIGURE 1. READ CYCLE TIMING WAVEFORMS

Dynamic Electrical Specifications At T

CL = 100 pF.

TEST

CONDITIONS

V

DD

PARAMETER

Read Cycle Times (Figure 2)
Write Cycle t

Address Setup t

Write Recovery t

Write Width t

Input Data Setup Time t

Data Hold t

Chip-Select 1 Setup t

Chip-Select 2 Setup t

WC

AS

WR

WRW

DS

DH

CS1S

CS2S

(V)

5 500 - - 500 - - ns

10 300 - - - - - ns

5 200 - - 200 - - ns

10 110 - - - - - ns

550--50--ns

10 40 - - - - - ns

5 250 - - 250 - - ns

10 150 - - - - - ns

5 250 - - 250 - - ns

10 150 - - - - - ns

550--50--ns

10 40 - - - - - ns

5 200 - - 200 - - ns

10 110 - - - - - ns

5 200 - - 200 - - ns

10 110 - - - - - ns

VALID

t

DOH3

t

DOH2

HIGH

IMPEDANCE

t

DOA2

t

DOA3

t

AA

DATA OUT

+ -40 to +85oC, VDD±5%, Input tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD,

A

LIMITS

CD1822 CDP1822C

(NOTE 1)

MIN

(NOTE 2)

TYP MAX

(NOTE 1)

MIN

(NOTE 2)

TYP MAX

UNITS

6-14

CDP1822, CDP1822C

Dynamic Electrical Specifications At T

+ -40 to +85oC, VDD±5%, Input tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD,

A

CL = 100 pF. (Continued)

TEST

CONDITIONS

PARAMETER

Chip-Select 1 Hold t

CS1H

V

DD

(V)

50--0--ns

(NOTE 1)

MIN

10 0 - - 0 - - ns

Chip-Select 2 Hold t

CS2H

50--0--ns

10 0 - - 0 - - ns

Output Disable Set-Up t

ODS

5 200 - - 200 - - ns

10 110 - - - - - ns

NOTES:

1. Time required by a limit device to allow for indicated function.

2. Typical values are for TA = 25oC and nominal VDD.

LIMITS

CD1822 CDP1822C

(NOTE 2)

TYP MAX

t

WC

(NOTE 1)

MIN

(NOTE 2)

TYP MAX

t

WR

UNITS

NOTE: t

A0-A7

t

t

AS

CSIS

(NOTE)

t

ODS

t

CS2S

DON’T CARE

DATA IN STABLE

t

WRW

CHIP-SELECT 1

CHIP-SELECT 2

OUTPUT DISABLE

DI1-DI4

READ/

WRITE

is required for common I/O operation only. For separate I/O operations, output disable is don’t care.

ODS

t

CSIH

t

CS2H

t

DS

FIGURE 2. WRITE CYCLE TIME WAVEFORMS

t

DH

6-15

CDP1822, CDP1822C

Data Retention Specifications At T

= -40 to +85oC, see Figure 3.

A

TEST CONDITIONS

V

PARAMETER

Min. Data Retention Voltage V
Data Retention Quiescent

Current I

DD

Chip Deselect to Data Retention
Time t

CDR

Recovery to Normal Operation
Time t

RC

VDD to VDR Rise and Fall Time tR,t

DR

F

DR

(V)

- - - 1.5 2 - 1.5 2 V

2 - - 30 100 - 30 100 µA

- 5 600 - - 600 - - ns

- 10300---- -ns

- 5 600 - - 600 - - ns

- 10300---- -ns

251--1--µA

NOTE: Typical values are for TA = 25oC and nominal VDD.

DATA RETENTION

DD

MODE

0.95 V

DD

V

DR

t

f

t

r

V

C

DD

t

CDR
S2

V

IH

V

IL

0.95 V

V

DD

(V) MIN

t

RC

V

IH

V

IL

LIMITS

CDP1822 CDP1822C

(NOTE 1)

TYP MAX MIN

DATA IN

WRITE
ADDRESS
DECODER

(NOTE 1)

TYP MAX

V

DD

V

SS

READ

ADDRESS

DECODER

UNITS

DATA OUT

V

DD

FIGURE 3. LOW VDD DATA RETENTION TIME WAVEFORMS FIGURE 4. MEMORY CELL CONFIGURATION

6-16

A0
A1
A2
A3
A4

CDP1822, CDP1822C

†

4

†

3

†

2

†

1

†

21

(5)

INPUT

BUFFERS

AND
ALL ROWS
DESELECT

FUNCTION

(32)

ROW

DECODERS

†††

22

V

DD

DI1
DI2
DI3
DI4

A5
A6
A7

R/W

CSI

CS2

OD

†

9

†

11

†

13

†

15

†

5

†

6

†

7

†

20

†

19

†

17

†

18

(4)

GATES

(3)

INPUT

BUFFERS

AND

ALL COLUMNS

DESELECT

FUNCTION

CONTROL

A

V

DD

CONTROL

B

(8 x 32)

STORAGE

ARRAY

BIT (1)

(8)

COLUMN

DECODERS

CONTROL

C

V

DD

(8 x 32)

STORAGE

ARRAY

BIT (2)

(8)

COLUMN

DECODERS

(8 x 32)

STORAGE

ARRAY

BIT (3)

(8)

COLUMN

DECODERS

V

DD

(8 x 32)

STORAGE

ARRAY

BIT (4)

(8)

COLUMN

DECODERS

BITS
(1-4)

(4)

BUFFER

DRIVERS

††

10

D01

††

12

D02

††

14

D03

††

16

D04

†††

8

V

SS

V

SS

INPUT PROTECTION

† †† †††

NETWORK

V

SS

OUTPUT
PROTECTION
CIRCUIT

FIGURE 5. FUNCTIONAL BLOCK DIAGRAM FOR CDP1822 AND CDP1822C

6-17

V

SS

OVER VOLTAGE
PROTECTION
CIRCUIT

CDP1822, CDP1822CS

C

CONTROL A

CS1

19

CS2

17

CONTROL B

W

R/

20

CONTROL C

OUTPUT

DISABLE

18

FIGURE 6. LOGIC DIAGRAM OF CONTROLS FOR CDP1822 AND CDP1822C

A
CHIP-SELECT
CONTROL

B
CHIP-SELECT AND

W CONTROL

R/

C
OUTPUT
DISABLE

CONTROL

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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
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