Page 1
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D
Distributes One Clock Input to One Bank of
Ten Outputs
D
Single Output Enable Terminal Controls All
Ten Outputs
D
External Feedback (FBIN) Pin Is Used to
Synchronize the Outputs to the Clock Input
D
On-Chip Series Damping Resistors
D
No External RC Network Required
D
Operates at 3.3-V V
CC
D
Packaged in Plastic 24-Pin Thin Shrink
Small-Outline Package
description
The CDC2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver . It uses a PLL to
precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It
is specifically designed for use with synchronous DRAMs. The CDC2510 operates at 3.3-V V
CC
and provides
integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL can be bypassed for test purposes by strapping AV
CC
to ground.
The CDC2510 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
G CLK
1Y
(0:9)
FBOUT
X L L L
L HLH
H H H H
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CLK
AV
CC
V
CC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
V
CC
FBIN
1
2
3
4
5
6
7
8
9
10
11
12
AGND
V
CC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
CC
G
FBOUT
24
23
22
21
20
19
18
17
16
15
14
13
PW PACKAGE
(TOP VIEW)
Page 2
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
1Y2
1Y1
1Y0
PLL
FBIN
AV
CC
CLK
G
1Y7
1Y6
1Y5
1Y8
FBOUT
1Y3
1Y4
11
24
13
23
3
4
5
8
9
15
16
17
20
12
1Y9
21
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(PW)
0°C to 70°C CDC2510PWR
Page 3
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
TYPE
DESCRIPTION
CLK 24 I
Clock input. CLK provides the clock signal to be distributed by the CDC2510 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
FBIN 13 I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
G 11 I
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same
frequency as CLK.
FBOUT 12 O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
and integrated 25-Ω series-damping resistor.
1Y (0:9)
3, 4, 5, 8, 9
15, 16, 17, 20,
21
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
Each output has an integrated 25-Ω series-damping resistor.
AV
CC
23 Power
Analog power supply . A VCC provides the power reference for the analog circuitry. In addition, A V
CC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK is buffered directly to the device outputs.
AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry.
V
CC
2, 10, 14, 22 Power Power supply
GND 6, 7, 18, 19 Ground Ground
Page 4
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high
or low state, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3) 0.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
application note in the
ABT Advanced BiCMOS T echnology Data
Book
, literature number SCBD002.
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
Supply voltage 3 3.6 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
V
I
Input voltage 0 V
CC
V
I
OH
High-level output current –12 mA
I
OL
Low-level output current 12 mA
T
A
Operating free-air temperature 0 70 °C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP‡MAX UNIT
V
IK
II = –18 mA 3 V –1.2 V
IOH = –100 µA MIN to MAX VCC–0.2
V
OH
IOH = –12 mA 3 V 2.1
V
IOH = –6 mA 3 V 2.4
IOL = 100 µA MIN to MAX 0.2
V
OL
IOL = 12 mA 3 V 0.8
V
IOL = 6 mA 3 V 0.55
I
I
VI = VCC or GND 3.6 V ±5 µA
I
CC
§
VI = VCC or GND, IO = 0, Outputs: low or high 3.6 V 10 µA
∆I
CC
One input at VCC – 0.6 V, Other inputs at VCC or GND 3.3 V to 3.6 V 500 µA
C
i
VI = VCC or GND 3.3 V 4 pF
C
o
VO = VCC or GND 3.3 V 6 pF
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§
For ICC of AVCC, see Figure 5.
Page 5
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN MAX UNIT
f
clock
Clock frequency 25 125 MHz
Input clock duty cycle 40% 60%
Stabilization time
†
1 ms
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency , fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew ,
and jitter parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 30 pF (see Note 5 and Figures 1 and 2)
‡
PARAMETER
FROM
TO
VCC = 3.3 V
± 0.165 V
VCC = 3.3 V
± 0.3 V
(INPUT)
(OUTPUT)
MIN TYP MAX MIN TYP MAX
t
phase error
,
reference
(see Figure 3)
66 MHz < CLKIN↑ < 100 MHz FBIN↑ –0.7...0.1 ns
t
phase error
– jitter
(see Note 6)
CLKIN↑ = 100 MHz FBIN↑ –500 –50 –310 ps
t
sk(o)
§
Any Y or FBOUT Any Y or FBOUT 200 ps
Jitter
(pk-pk)
F(clkin > 66 MHz) Any Y or FBOUT –100 100 ps
Duty cycle
reference
(see Figure 4)
Any Y or FBOUT 43% 55%
t
r
Any Y or FBOUT 1.3 1.9 0.8 2.1 ns
t
f
Any Y or FBOUT 1.7 2.3 1.2 2.5 ns
‡
These parameters are not production tested.
§
The t
sk(o)
specification is only valid for equal loading of all outputs.
NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
6. Phase error does not include jitter. The total phase error is –600 ps to 50 ps for the 5% VCC range.
Page 6
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
pd
50% V
CC
3 V
0 V
V
OH
V
OL
Input
0.4 V
2 V
t
r
t
f
0.4 V
2 V
Output
500
W
50% V
CC
30 pF
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
t
sk(o)
t
sk(o)
t
phase error
CLKIN
FBIN
Any Y
Any Y
Any Y
FBOUT
Figure 2. Phase Error and Skew Calculations
Page 7
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 3
PHASE ERROR
vs
CLOCK FREQUENCY
35
–0.3
–0.5
–0.7
–0.9
45 55 65 95 105
f
clk
– Clock Frequency – MHz
85
–0.2
–0.4
–0.6
–0.8
75 115 125
VDD = 3.3 V
TA = 25°C
–0.1
0
25
Phase Error – ns
Figure 4
VDD = 3.3 V
CL = 30 pF
OUTPUT DUTY CYCLE
vs
CLOCK FREQUENCY
57%
53%
51%
47%
43%
55%
49%
45%
Output Duty Cycle
40 50 60 70 100 110
f
clk
– Clock Frequency – MHz
9080 120 13030
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
35
6
4
2
0
45 55 65 95 105
f
clk
– Clock Frequency – MHz
85
7
Analog Supply Current – mA
5
3
1
75 115 125
VDD = 3.3 V
TA = 25°C
8
9
25
Figure 5
Page 8
CDC2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS597 – DECEMBER 1997
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040064/E 08/96
14 PIN SHOWN
Seating Plane
0,05 MIN
1,20 MAX
1
A
7
14
0,19
4,50
4,30
8
6,20
6,60
0,30
0,75
0,50
0,25
Gage Plane
0,15 NOM
0,65
M
0,10
0°–8°
0,10
PINS **
A MIN
A MAX
DIM
2,90
3,10
8
4,90
5,10
14
6,60
6,404,90
5,10
16
7,70
20
7,90
24
9,60
9,80
28
NOTES: D. All linear dimensions are in millimeters.
E. This drawing is subject to change without notice.
F. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
G. Falls within JEDEC MO-153
Page 9
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
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Copyright 1998, Texas Instruments Incorporated
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