Datasheet CD74HC93EE4 Specification

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Page 1

Data sheet acquired from Harris Semiconductor

[ ( H C H ) / j ( S C L 4 B R C r

SCHS138C

August 1997 - Revised September 2003

CD74HC93,

CD74HCT93

High-Speed CMOS Logic

4-Bit Binary Ripple Counter

/Title CD74

C93, D74 CT93

Subect High

peed

MOS

ogic

-Bit inary ipple ounte

)

Features

• Can Be Conﬁgured to Divide By 2, 8, and 16

• Asynchronous Master Reset

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

≤ 1µA at VOL, V

C to 125oC

Pinout

CD74HC93 (PDIP, SOIC) CD74HCT93

(PDIP)

TOP VIEW

CP1 MR1 MR2

NC NC

1 2 3 4 5 6 7

CPO

14 13

GND

Description

The CD74HC93and CD74HCT93 are high-speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL). These 4-bit binary ripple counters consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide- by-eight section. Each section has a separate clock input ( initiate state changes of the counter on the HIGH to LOW clock transition. State changes of the Q simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes.

A gated AND asynchronous master reset (MR1 and MR2 is provided which overrides both clocks and resets (clears) all ﬂip-ﬂops.

Because the output from the divide by two section is not internally connected to the succeeding stages, the device may be operated in various counting modes.

In a 4-bit ripple counter the output Q externally to input to clock input 8, and 16 are performed at the Q as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input

Simultaneous frequency divisions of 2, 4, and 8 are available at the Q ﬂop is available if the reset function coincides with the reset of the 3-bit ripple-through counter.

1,Q2,Q3

CP1. The input count pulses are applied

CP0. Simultaneous frequency divisions of 2, 4,

0,Q1,Q2

outputs. Independent use of the ﬁrst ﬂip-

CP0 and CP1) to

outputs do not occur

must be connected

CP1.

Ordering Information

TEMP. RANGE

PART NUMBER

CD74HC93E -55 to 125 14 Ld PDIP CD74HC93M -55 to 125 14 Ld SOIC CD74HC93MT -55 to 125 14 Ld SOIC CD74HC93M96 -55 to 125 14 Ld SOIC CD74HCT93E -55 to 125 14 Ld PDIP

(oC) PACKAGE

, and Q3outputs

NOTE: When ordering,use the entire part number.The sufﬁx 96 denotes tape and reel. The sufﬁx T denotes a small-quantity reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

Page 2

CD74HC93, CD74HCT93

TRUTH TABLE

OUTPUTS

COUNT

0LLLL 1HLLL 2LHLL 3HHLL 4LLHL 5HLHL 6LHHL 7HHHL 8LLLH

9HLLH 10LHLH 11 H H L H 12 L L H H 13 H L H H 14LHHH 15HHHH

H = High Voltage Level, L = Low Voltage Level

MODE SELECTION

RESET OUTPUTS OUTPUTS MR1 MR2 Q

HHLLLL

L H Count Count Count Count

H = High Voltage Level, L = Low Voltage Level

Page 3

CD74HC93, CD74HCT93

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

DC Electrical Speciﬁcations

PARAMETER SYMBOL

HC TYPES

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage CMOS Loads

High Level Output Voltage TTL Loads

Low Level Output Voltage CMOS Loads

Low Level Output Voltage TTL Loads

Input Leakage Current

Quiescent Device Current

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V

VIH or

-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

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CD74HC93, CD74HCT93

DC Electrical Speciﬁcations (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage CMOS Loads

High Level Output Voltage TTL Loads

Low Level Output Voltage CMOS Loads

Low Level Output Voltage TTL Loads

Input Leakage Current

Quiescent Device Current

Additional Quiescent Device Current Per Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

∆I

(Note 2)

- - 4.5 to

VIH or

VCC to

GND

VCC or

GND

-2.1

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VCC (V)

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

5.5

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

CP0, CP1 0.6

MR1, MR2 0.4

NOTE: Unit Load is ∆ICClimit speciﬁed in DC Electrical Speciﬁcations table, e.g. 360µA max at 25oC.

Prerequisite For Switching Speciﬁcations

TEST CONDITIONS

PARAMETER SYMBOL

HC TYPES

Maximum Clock Frequency f

Clock Pulse Width CP0, CP1

MAX

VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN MAX MIN MAX MIN MAX

2 6-5-4-MHz

4.5 30 - 24 - 20 - MHz 6 35 - 28 - 24 - MHz 2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns 6 14-17-20-ns

Page 5

CD74HC93, CD74HCT93

Prerequisite For Switching Speciﬁcations (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL

Reset Pulse Width t

TEST CONDITIONS

VCC (V)

2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns 6 14-17-20-ns

Reset Removal Time t

REM

2 50-65-75-ns

4.5 10 - 13 - 15 - ns 6 9 - 11 - 13 - ns

HCT TYPES

Maximum Clock Frequency f Clock Pulse Width

MAX

4.5 30 - 24 - 20 - mHz

4.5 16 - 20 - 24 - ns

CP0, CP1 Reset Pulse Width t Reset Removal Time t

REM

Switching Speciﬁcations Input t

, tf = 6ns

4.5 16 - 20 - 24 - ns

4.5 10 - 13 - 15 - ns

-55oC TO

PARAMETER SYMBOL

TEST

CONDITIONS

25oC -40oC TO 85oC

(V)

125oC

HC TYPES

Propagation Delay Time t

PLH

, t

PHLCL

= 50pF 2 - - 125 - 155 - 190 ns

CP0 to Q0 CL= 50pF 4.5 - - 25 - 31 - 38 ns

CL= 15pF 5 - 10 ----ns CL= 50pF 6 - - 21 - 26 - 32 ns

CP1 to Q1 t

PLH

, t

PHLCL

= 50pF 2 - 135 - 170 - 205 ns CL= 50pF 4.5 - 27 - 34 - 41 ns CL= 50pF 6 - 23 - 29 - 35 ns

CP1 to Q2 t

PLH

, t

PHLCL

= 50pF 2 - 185 - 230 - 280 ns CL= 50pF 4.5 - 37 - 46 - 56 ns CL= 50pF 6 - 31 - 39 - 48 ns

CP1 to Q3 t

PLH

, t

PHLCL

= 50pF 2 - 245 - 305 - 370 ns CL= 50pF 4.5 - 49 - 61 - 74 ns CL= 15pF 5 - 21 - ----ns CL= 50pF 6 - - 42 - 52 - 63 ns

MR1, MR2 to Qn t

PLH

, t

PHLCL

= 50pF 2 - 155 - 195 - 235 ns CL= 50pF 4.5 - 31 - 39 - 47 ns CL= 15pF 5 - 13 - - - ns CL= 50pF 6 - 26 - 33 - 40 ns

Output Transition Time t

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns

Input Capacitance C Power Dissipation Capacitance C

CL= 50pF - - - 10 - 10 - 10 pF

- - - 25 - - 10 - 19 pF

UNITSMIN MAX MIN MAX MIN MAX

UNITSMIN TYP MAX MIN MAX MIN MAX

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CD74HC93, CD74HCT93

Switching Speciﬁcations Input t

, tf = 6ns (Continued)

-55oC TO

PARAMETER SYMBOL

TEST

CONDITIONS

25oC -40oC TO 85oC

(V)

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HCT TYPES

Propagation Delay Time t

PLH

, t

PHLCL

= 50pF 4.5 - - 34 - 43 - 51 ns CP0 to Q0 CL= 15pF 5 - 14 - ----ns CP1 to Q1 t

PLH

, t

PHLCL

= 50pF 4.5 - - 34 - 43 - 51 ns

CL= 15pF 5 - - - ----ns

CP1 to Q2 t

PLH

, t

PHLCL

= 50pF 4.5 - - 46 - 58 - 69 ns

CL= 15pF 5 - - - ----ns

CP1 to Q3 t

PLH

, t

PHLCL

= 50pF 4.5 - - 58 - 73 - 87 ns

CL= 15pF 5 - 24 - ----ns

MR1, MR2 to Qn t

PLH

, t

PHLCL

= 50pF 4.5 - - 33 - 41 - 50 ns

CL= 15pF 5 - 13 - ----ns Output Transition Time t Input Capacitance C Power Dissipation Capacitance C

TLH

, t

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

CL= 50pF - - - 10 - 10 - 10 pF

- --25-----pF

Test Circuits and Waveforms

90%

PLH

TLH

tfC

50%

H(L)

SU(L)

THL

90%

50%

10% t

PHL

50pF

GND

50% GND

GND

CLOCK

INPUT

DAT A

INPUT

SU(H)

OUTPUT

REM

SET, RESET OR PRESET

trC

90%

10%

H(H)

50%

FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVALTIME,

AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS

CLOCK

INPUT

DAT A

INPUT

SU(H)

OUTPUT

REM

3V SET, RESET OR PRESET

trC

2.7V

0.3V

H(H)

1.3V

90%

PLH

1.3V

TLH

tfC

1.3V

H(L)

1.3V

SU(L)

THL

90%

1.3V 10%

PHL

50pF

GND

FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS

Page 7

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

PACKAGING INFORMATION

Orderable Device Status

CD74HC93E ACTIVE PDIP N 14 25 Pb-Free

CD74HC93EE4 ACTIVE PDIP N 14 25 Pb-Free

CD74HC93M ACTIVE SOIC D 14 50 Green (RoHS

CD74HC93M96 ACTIVE SOIC D 14 2500 Green (RoHS

CD74HC93M96G4 ACTIVE SOIC D 14 2500 Green (RoHS

CD74HC93MT ACTIVE SOIC D 14 250 Green (RoHS

CD74HCT93E ACTIVE PDIP N 14 25 Pb-Free

CD74HCT93EE4 ACTIVE PDIP N 14 25 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

(RoHS)

& no Sb/Br)

(RoHS)

Lead/Ball Finish

(6)

CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC93E

CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC93M

CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT93E

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Samples

Addendum-Page 1

Page 8

PACKAGE OPTION ADDENDUM

www.ti.com

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

10-Jun-2014

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

Page 9

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

CD74HC93M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD74HC93MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

Page 10

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type PackageDrawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC93M96 SOIC D 14 2500 367.0 367.0 38.0

CD74HC93MT SOIC D 14 250 367.0 367.0 38.0

Pack Materials-Page 2

Page 11

Page 12

Page 13

Page 14

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