Datasheet CD74HC194N Specification

Data sheet acquired from Harris Semiconductor

[
(
H
C
C
/
j
(
S
C
L
4

SCHS164G

September 1997 - Revised May 2006

CD54HC194, CD74HC194,

CD74HCT194

High-Speed CMOS Logic

4-Bit Bidirectional Universal Shift Register

/Title
CD74

C194,
D74H

T194)
Sub­ect
High-

peed

MOS

ogic

-Bit

Features

• Four Operating Modes

- Shift Right, Shift Left, Hold and Reset

• Synchronous Parallel or Serial Operation

• Typical f
T

= 25oC

A

• Asynchronous Master Reset

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 60MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

OH

Description

The ’HC194 and CD74HCT194 are 4-bit shift registers with
Asynchronous Master Reset (

MR). In the parallel mode (S0
and S1 are high), data is loaded into the associated flip-flop
and appears at the output after the positive transition of the
clock input (CP). During parallel loading serial data flow is
inhibited. Shift left and shift right are accomplished
synchronously on the positive clock edge with serial data
entered at the shift left (DSL) serial input for the shift left
mode, and at the shift right (DSR) serial input for the shift
right mode. Clearing the register is accomplished by a Low
applied to the Master Reset (

MR) pin.

Ordering Information

TEMP. RANGE

CC

PART NUMBER

CD54HC194F3A -55 to 125 16 Ld CERDIP
CD74HC194E -55 to 125 16 Ld PDIP
CD74HC194M -55 to 125 16 Ld SOIC
CD74HC194MT -55 to 125 16 Ld SOIC
CD74HC194M96 -55 to 125 16 Ld SOIC
CD74HC194NSR -55 to 125 16 Ld SOP
CD74HC194PW -55 to 125 16 Ld TSSOP
CD74HC194PWR -55 to 125 16 Ld TSSOP

(oC) PACKAGE

Pinout

CD54HC194 (CERDIP)

CD74HC194 (PDIP, SOIC, SOP, TSSOP)

CD74HCT194 (PDIP)

TOP VIEW

V

1

MR

DSR

2

D

3

0

4

D

1

5

D

2

6

D

3

7

DSL

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2006, Texas Instruments Incorporated

16

CC

15

Q

0

14

Q

1

13

Q

2

12

Q

3

11

CP
S1

10

S0

9

CD74HC194PWT -55 to 125 16 Ld TSSOP
CD74HCT194E -55 to 125 16 Ld PDIP

NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.

1

Functional Diagram

CD54HC194, CD74HC194, CD74HCT194

D

D

D

D

DSL

DSR

S0
S1

MR

CP

3

0

4

1

5

2

6

3

2 9 10 1 11

7

15

Q

14

Q

13

Q

12

Q

GND = 8
VCC= 16

0

1

2

3

TRUTH TABLE

INPUTS OUTPUT

OPERATING

MODE

CP MR S1 S0 DSR DSL D

n

Q

Q

0

Q

1

Q

2

3

Reset (Clear) X L X X X X X LLLL
Hold (Do Nothing) X H l l X X X q

0

Shift Left ↑ H h l XlXq1q

↑ Hh lXhXq1q

Shift Right ↑ Hl hlXXLq0q

↑ Hl hhXXHq0q

Parallel Load ↑ Hh hXXdnd

0

q

1

2

2

d

1

q

2

q

3

q

3

1

1

d

2

q

3

L

H

q

2

q

2

d

3

H = High Voltage Level,
h = High Voltage Level One Set-up Time Prior To The Low to High Clock Transition,
L = Low Voltage Level,
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition,
dn(qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low To High Clock
Transition,
X = Don’t Care,
↑ = Transition from Low to High Level

2

CD54HC194, CD74HC194, CD74HCT194

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Package Thermal Impedance, θJA(see Note 2):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

V

IH

V

IL

V

OH

V

OL

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

Low Level Output
Voltage
TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

3

CD54HC194, CD74HC194, CD74HCT194

DC Electrical Specifications (Continued)

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL

Input Leakage
Current

Quiescent Device
Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

VCC (V)

I

VCC or

I

-6--±0.1 - ±1-±1 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

GND

I

CC

VCC or

0 6 - - 8 - 80 - 160 µA

GND

V

IH

- - 4.5 to

2-- 2 - 2 - V

5.5

V

IL

- - 4.5 to

- - 0.8 - 0.8 - 0.8 V

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

I

I

CC

∆I

CC

(Note 3)

VCC to

GND

VCC or

GND

V

CC

-2.1

0 5.5 - - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS

CP 0.6
MR 0.55

DSL, DSR, D

n

Sn 1.10

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.

0.25

4

CD54HC194, CD74HC194, CD74HCT194

Prerequisite For Switching Function

PARAMETER SYMBOL

HC TYPES

Max. Clock Frequency
(Figure 1)

MR Pulse Width
(Figure 2)

Clock Pulse Width
(Figure 1)

Set-up Time
Data to Clock (Figure 3)

Removal Time,
MR to Clock (Figure 2)

f

MAX

t

t

t

t

REM

W

W

SU

TEST

25oC -40oC TO 85oC -55oC TO 125oC

CONDITIONS VCC (V)

- 26-5-4-MHz

4.5 30 - 24 - 20 - MHz
6 35 - 28 - 23 - MHz

- 2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
614-17-20-ns

- 2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
614-17-20-ns

- 2 70 - 90 - 105 - ns

4.5 14 - 18 - 21 - ns
612-15-19-ns

- 2 60 - 75 - 90 - ns

4.5 12 - 15 - 18 - ns

UNITSMIN MAX MIN MAX MIN MAX

Set-Up Time
S1, S0 to Clock (Figure 4)

Set-up Time
DSL, DSR to Clock (Figure 4)

Hold Time
S1, S0 to Clock (Figure 4)

Hold Time
Data to Clock (Figure 3)

HCT TYPES

Max. Clock Frequency (Figure 1) f
MR Pulse Width (Figure 2) t
Clock Pulse Width (Figure 1) t
Set-up Time, Data to Clock

(Figure 3)

t

SU

t

SU

t

H

t

H

MAX

W
W

t

SU

610-13-15-ns

- 2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
614-17-20-ns

- 2 70 - 90 - 105 - ns

4.5 14 - 18 - 21 - ns
612-15-18-ns

- 20-0-0-ns

4.50-0-0-ns
60-0-0-ns

- 20-0-0-ns

4.50-0-0-ns
60-0-0-ns

- 4.5 27 - 22 - 18 - MHz

- 4.5 16 - 20 - 24 - ns

- 4.5 16 - 20 - 24 - ns

- 4.5 14 - 18 - 21 - ns

Removal Time MR to Clock
(Figure 2)

t

REM

- 4.5 12 - 15 - 18 - ns

5

Prerequisite For Switching Function (Continued)

TEST

PARAMETER SYMBOL

Set-up Time

t

SU

CONDITIONS VCC (V)

- 4.5 20 - 25 - 30 - ns

S1, S0 to Clock (Figure 4)
Set-up Time

t

SU

- 4.5 14 - 18 - 21 - ns

DSL, DSR to Clock (Figure 4)
Hold Time

t

H

- 4.50-0-0-ns

S1, S0 to Clock (Figure 4)
Hold Time

t

H

- 4.50-0-0-ns

Data to Clock (Figure 3)

Switching Specifications Input t

PARAMETER SYMBOL

, tf = 6ns

r

CONDITIONS

TEST

V

CC

(V)

HC TYPES

Propagation Delay,
Clock to Output (Figure 1)

t

PLH

, t

PHLCL

= 50pF 2 - 175 220 265 ns

4.5 - 35 44 53 ns
6 - 30 37 45 ns

Propagation Delay,

t

PLH

, t

PHL

- 5 14 - - - ns

Clock to Q
Output Transition Time

(Figure 1)

t

TLH

, t

THLCL

= 50pF 2 - 75 95 110 ns

4.5 - 15 19 22 ns
6 - 13 16 19 ns

Propagation Delay,
MR to Output (Figure 2)

t

PHL

CL= 50pF 2 - 140 175 210 ns

4.5 - 28 35 42 ns
6 - 24 30 36 ns

Input Capacitance C
Maximum Clock Frequency f
Power Dissipation

MAX

C

IN

PD

---1010 10pF

- 5 60 - - - MHz

- 5 55 - - - pF

Capacitance (Notes 4, 5)

HCT TYPES

Propagation Delay,

t

PLH

, t

PHLCL

= 50pF 4.5 - 37 46 56 ns

Clock to Output (Figure 1)
Propagation Delay,

t

PLH

, t

PHL

- 5 15 - - - ns

Clock to Q
Output Transition Times

t

TLH

, t

THLCL

= 50pF 4.5 - 15 19 22 ns

(Figure 1)
Propagation Delay,

t

PHL

CL= 50pF 4.5 - 40 50 60 ns

MR to Output (Figure 2)
Input Capacitance C
Maximum Clock Frequency f
Power Dissipation

MAX

C

IN

PD

---1010 10pF

- 5 50 - - - MHz

- 5 60 - - - pF

Capacitance (Notes 4, 5)

NOTES:

3. CPD is used to determine the dynamic power consumption, per gate.

4. PD = V

2

fi + ∑ (CL V

CC

2

) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN MAX MIN MAX MIN MAX

25oC -40oC TO 85oC -55oC TO 125oC

UNITSTYP MAX MAX MAX

6

Test Circuits and Waveforms

I

D

NPUT LEVEL

CP

10%

90%
V

S

t

t

PHL

r

t

W

V

t

S

10%

f

V

Q

V

S

t

THL

FIGURE 1. CLOCK PREREQUISITE TIMES AND

PROPAGATION AND OUTPUT TRANSITION TIMES

VALID

DAT A

CP

V

S

t

SU

t

H

V

S

INPUT LEVEL
GND
INPUT LEVEL

GND

FIGURE 3. DATA PREREQUISITE TIMES FIGURE 4. PARALLELLOADOR SHIFT-LEFT/SHIFT-RIGHT

S

GN

t

PLH

90%

V

S

10%

t

TLH

MR

CP

V

t

PHL

Q

V

S

t

S

W

t

REM

V

S

V

S

INPUT LEVEL
GND

INPUT LEVEL
GND

FIGURE 2. MASTER RESET PREREQUISITE TIMES AND

PROPAGATION DELAYS

VALID

S OR DS

CP

V

S

t

SU

t

H

V

S

INPUT LEVEL
GND

INPUT LEVEL
GND

PREREQUISITE TIMES

7

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-8682601EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8682601EA

CD54HC194F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8682601EA

CD74HC194E ACTIVE PDIP N 16 25 Pb-Free

CD74HC194M ACTIVE SOIC D 16 40 Green (RoHS

CD74HC194M96 ACTIVE SOIC D 16 2500 Green (RoHS

CD74HC194PW ACTIVE TSSOP PW 16 90 Green (RoHS

CD74HC194PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS

CD74HC194PWR ACTIVE TSSOP PW 16 2000 Green (RoHS

CD74HC194PWT ACTIVE TSSOP PW 16 250 Green (RoHS

CD74HCT194E ACTIVE PDIP N 16 25 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

(RoHS)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

& no Sb/Br)

(RoHS)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

CD54HC194F3A

CD54HC194F3A

CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC194E

CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC194M

CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC194M

CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ194

CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ194

CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ194

CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ194

CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT194E

(4/5)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

3-Sep-2015

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC194, CD74HC194 :

Catalog: CD74HC194

•

Military: CD54HC194

•

3-Sep-2015

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Sep-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

CD74HC194M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC194PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC194PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Sep-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC194M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HC194PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC194PWT TSSOP PW 16 250 367.0 367.0 35.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright © 2015, Texas Instruments Incorporated