Datasheet CD74HC192Ε Specification

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Page 1

Data sheet acquired from Harris Semiconductor

[ ( H , C H , C H 3 / j ( S C L P

SCHS163F

September 1997 - Revised October 2003

CD54/74HC192,

CD54/74HC193, CD54/74HCT193

High-Speed CMOS Logic

Presettable Synchronous 4-Bit Up/Down Counters

/Title CD74

C192

D74 C193

D74 CT19

) Subect High

peed

MOS ogic reset-

Features

• Synchronous Counting and Asynchronous Loading

• Two Outputs for N-Bit Cascading

• Look-Ahead Carry for High-Speed Counting

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

≤ 1µA at VOL, V

C to 125oC

Description

The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.

Presetting thecounter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input ( transition of the Clock-Up input (and a high level on the ClockDown input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its z ero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode lik ewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and Clock-Down inputs, respectively, of the next most significant counter.

If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.

PL). The counter is incremented on the low-to-high

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC192F3A -55 to 125 16 Ld CERDIP CD54HC193F3A -55 to 125 16 Ld CERDIP CD54HCT193F3A -55 to 125 16 Ld CERDIP CD74HC192E -55 to 125 16 Ld PDIP CD74HC192NSR -55 to 125 16 Ld SOP

(oC) PACKAGE

Pinout

CD54HC192, CD54HC193, CD54HCT193 (CERDIP)

CD74HC192 (PDIP, SOP, TSSOP)

CD74HC193 (PDIP, SOIC)

CD74HCT193 (PDIP)

TOP VIEW

CPD

CPU

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

TCD

TCU

CD74HC192PW -55 to 125 16 Ld TSSOP CD74HC192PWR -55 to 125 16 Ld TSSOP CD74HC192PWT -55 to 125 16 Ld TSSOP CD74HC193E -55 to 125 16 Ld PDIP CD74HC193M -55 to 125 16 Ld SOIC CD74HC193MT -55 to 125 16 Ld SOIC CD74HC193M96 -55 to 125 16 Ld SOIC CD74HCT193E -55 to 125 16 Ld PDIP

NOTE: When ordering, use the entire part number. The sufﬁxes 96 and R denote tape and reel. The sufﬁx T denotes a small-quantity reel of 250.

Page 2

Functional Diagram

CD54/74HC192, CD54/74HC193, CD54/74HCT193

BCD/BINARY

PRESET

P0 P1 P2 P3

15 1 10 9

TERMINAL COUNT UP

TERMINAL COUNT DOWN

BCD (192) BINARY (193) OUTPUTS

ASYN.

PARALLEL

LOAD

ENABLE

MASTER

RESET

CLOCK UP

CLOCK DOWN

TRUTH TABLE

CLOCK UP

CLOCK

DOWN RESET

PARALLEL

LOAD FUNCTION

↑ H L H Count Up H ↑ L H Count Down X X H X Reset X X L L Load Preset Inputs

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level

Page 3

CD54/74HC192, CD54/74HC193, CD54/74HCT193

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

Package Thermal Impedance, θJA(see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

DC Electrical Speciﬁcations

PARAMETER SYMBOL

HC TYPES

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage CMOS Loads

High Level Output Voltage TTL Loads

Low Level Output Voltage CMOS Loads

Low Level Output Voltage TTL Loads

Input Leakage Current

Quiescent Device Current

TEST

CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V

VIH or

-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

UNITSVI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX

Page 4

CD54/74HC192, CD54/74HC193, CD54/74HCT193

DC Electrical Speciﬁcations (Continued)

TEST

CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL

HCT TYPES

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage CMOS Loads

High Level Output Voltage TTL Loads

Low Level Output Voltage CMOS Loads

Low Level Output Voltage TTL Loads

Input Leakage Current

Quiescent Device Current

Additional Quiescent Device Current Per Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

∆I

(Note 2)

- - 4.5 to

VIH or

VCC to

GND

VCC or

GND

- 2.1

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

- 5.5 - - ±0.1 - ±1-±1 µA

- 5.5 - - 8 - 80 - 160 µA

- 4.5 to

2-- 2 - 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 100 360 - 450 - 490 µA

5.5

UNITSVI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

P0-P3 0.4

MR 1.45

PL 0.85

CPU, CPD 1.45

NOTE: Unit Load is ∆ICClimit speciﬁed in DC Electrical Speciﬁcations table, e.g. 360µA max at 25oC.

Page 5

CD54/74HC192, CD54/74HC193, CD54/74HCT193

Prerequisite For Switching Speciﬁcations

PARAMETER SYMBOL

(V)

HC TYPES

Pulse Width t

2 115 - - 145 - 175 - ns

CPU, CPD 4.5 23 - - 29 - 35 - ns

192 6 20 - - 25 - 30 - ns

2 100 - - 125 - 150 - ns

CPU, CPD 4.5 20 - - 25 - 30 - ns

193 6 17 - - 21 - 26 - ns

PL t

2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns

MR t

2 100 - - 125 - 150 - ns

4.5 20 - - 25 - 30 - ns 6 17 - - 21 - 26 - ns

Set-up Time t

2 80 - - 100 - 120 - ns

Pn to PL 4.5 16 - - 20 - 24 - ns

6 14 - - 17 - 20 - ns

Hold Time t

2 0--0-0-ns

Pn to PL 4.5 0 - - 0 - 0 - ns

6 0--0-0-ns

Hold Time t

2 80 - - 100 - 120 - ns

CPD to CPU or 4.5 16 - - 20 - 24 - ns CPU to CPD 6 14 - - 17 - 20 - ns

Recovery Time t

REC

2 80 - - 100 - 120 - ns

PL to CPU, CPD 4.5 16 - - 20 - 24 - ns

6 14 - - 17 - 20 - ns

MR to CPU, CPD t

REC

2 5--5-5-ns

4.5 5--5-5-ns 6 5--5-5-ns

Maximum Frequency f

MAX

2 5--4-3-MHz

CPU, CPD 4.5 22 - - 18 - 15 - MHz

192 6 24 - - 21 - 18 - MHz

MAX

2 5--4-3-MHz

CPU, CPD 4.5 25 - - 20 - 17 - MHz

193 6 29 - - 24 - 20 - MHz

HCT TYPES

Pulse Width t

2 -------ns

CPU, CPD 4.5 23 - - 29 - 35 - ns

192 6 -------ns

CPU, CPD t

2 -------ns

193 4.5 23 - - 29 - 35 - ns

6 -------ns

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Page 6

CD54/74HC192, CD54/74HC193, CD54/74HCT193

Prerequisite For Switching Speciﬁcations (Continued)

PARAMETER SYMBOL

PL t

(V)

2 -------ns

4.5 16 - - 20 - 24 - ns 6 -------ns

MR t

2 -------ns

4.5 20 - - 25 - 30 - ns 6 -------ns

Set-up Time t

2 -------ns

Pn to PL 4.5 15 - - 19 - 22 - ns

6 -------ns

Hold Time t

2 -------ns

Pn to PL 4.5 0 - - 0 - 0 - ns

6 -------ns

Hold Time t

2 -------ns

CPD to CPU or 4.5 16 - - 20 - 24 - ns CPU to CPD 6 - - - - - - - ns

Recovery Time t

REC

2 -------ns

PL to CPU, CPD 4.5 15 - - 19 - 22 - ns

6 -------ns

MR to CPU, CPD t

REC

2 -------ns

4.5 5--5-5-ns 6 -------ns

Maximum Frequency f

MAX

2 -------MHz

CPU, CPD 4.5 22 - - 18 - 15 - MHz

192 6 -------MHz

CPU, CPD f

MAX

2 -------MHz

193 4.5 22 - - 18 - 15 - MHz

6 -------MHz

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Switching Speciﬁcations Input t

PARAMETER SYMBOL

, tf = 6ns

TEST

CONDITIONS

(V)

25oC -40oC TO 85oC -55oC TO 125oC

HC TYPES

Propagation Delay t

PLH

, t

PHLCL

= 50pF 2 - - 125 - 155 - 190 ns

CPU to TCU CL= 50pF 4.5 - - 25 - 31 - 38 ns

CL= 15pF 5 - 10 - ----ns CL= 50pF 6 - 21 - 26 - 32 ns

CPD to TCD t

PLH

, t

PHLCL

= 50pF 2 - - 125 - 155 - 190 ns CL= 50pF 4.5 - - 25 - 31 - 38 ns CL= 15pF 5 - 10 - ----ns CL= 50pF 6 - - 21 - 26 - 32 ns

CPU to Q

PLH

, t

PHLCL

= 50pF 2 - - 220 - 270 - 325 ns CL= 50pF 4.5 - - 43 - 54 - 65 ns CL= 15pF 5 - 18 - ----ns CL= 50pF 6 - - 37 - 46 - 55 ns

UNITSMIN TYP MAX MIN MAX MIN MAX

Page 7

CD54/74HC192, CD54/74HC193, CD54/74HCT193

Switching Speciﬁcations Input t

PARAMETER SYMBOL

CPD to Q

, tf = 6ns (Continued)

TEST

CONDITIONS

PLH

, t

PHLCL

= 50pF 2 - - 220 - 270 - 325 ns

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CL= 50pF 4.5 - - 43 - 54 - 65 ns CL= 15pF 5 - 18 - - - - ns CL= 50pF 6 - - 37 - 46 - 55 ns

PL to Q

PLH

, t

PHLCL

= 50pF 2 - - 220 - 275 - 330 ns CL= 50pF 4.5 - - 44 - 55 - 66 ns CL= 15pF 5 - 18 - ----ns CL= 50pF 6 - - 37 - 47 - 56 ns

MR to Q

PHL

CL= 50pF 2 - - 200 - 250 - 300 ns CL= 50pF 4.5 - - 40 - 50 - 60 ns CL= 15pF 5 - 17 - ----ns CL= 50pF 6 - - 34 - 43 - 51 ns

Transition Time t

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 - 110 ns

Q, TCU, TCD 4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns Input Capacitance C Power Dissipation Capacitance

CL= 50pF - - - 10 - 10 - 10 pF

CL= 15pF 5 - 40 - ----pF

(Notes 3, 4)

HCT TYPES

Propagation Delay t

PLH

, t

PHLCL

= 50pF 4.5 - - 27 - 34 - 41 ns CPU to TCU CL= 15pF 5 - 11 - ----ns CPU to TCD t

PLH

, t

PHLCL

= 50pF 4.5 - - 27 - 34 - 41 ns

CL= 15pF 5 - 11 - ----ns

CPU to Q

PLH

, t

PHLCL

= 50pF 4.5 - - 40 - 50 - 60 ns

CL= 15pF 5 - 17 - ----ns

CPD to Q

PLH

, t

PHLCL

= 50pF 4.5 - - 40 - 50 - 60 ns

CL= 15pF 5 - 17 - ----ns

PL to Q

PLH

, t

PHLCL

= 50pF 4.5 - - 46 - 58 - 69 ns

CL= 15pF 5 - 21 - ----ns

MR to Q

PHL

CL= 50pF 4.5 - - 43 - 54 - 65 ns CL= 15pF 5 - 18 - ----ns

Transition Time t

TLH

, t

THLCL

= 50pF Q, TCU, TCD 4.5 - - 15 - 19 - 22 ns

Input Capacitance C Power Dissipation Capacitance

CL= 50pF - - - 10 - 10 - 10 pF

CL= 15pF 5 - 50 - ----pF

(Notes 3, 4)

NOTES:

3. CPD is used to determine the dynamic power consumption, per gate.

4. PD = V

fi + ∑ (CL V

) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Page 8

CD54/74HC192, CD54/74HC193, CD54/74HCT193

Test Circuits and Waveforms

MASTER RESET

ASYNCHRONOUS PARALLEL LOAD

PRESET DATA

SEQUENCES:

1. RESET OUTPUTS TO ZERO.

2. LOAD (PRESET) TO BCD SEVEN.

3. COUNT UP TO EIGHT, NINE, TERMINAL COUNT UP, ZERO,

ONE AND TWO.

4. COUNT DOWN TO ONE, ZERO,

TERMINAL COUNT DOWN, NINE, EIGHT AND SEVEN.

TERMINAL COUNT UP

TERMINAL COUNT DOWN

CLOCK DOWN

OUTPUTS

CLOCK UP

PRESET

89012

10987

COUNT DOWNCOUNT UPRESET

FIGURE 1. ’HC192 SYNCHRONOUS DECADE COUNTERS, TYPICAL RESET, PRESET AND COUNT SEQUENCES

Page 9

CD54/74HC192, CD54/74HC193, CD54/74HCT193

Test Circuits and Waveforms (Continued)

MASTER RESET

ASYNCHRONOUS PARALLEL LOAD

PRESET DATA

SEQUENCES:

1. RESET OUTPUTS TO ZERO.

2. LOAD (PRESET) TO BINARY THIRTEEN.

CLOCK UP

3. COUNT UP TO FOURTEEN,

FIFTEEN, TERMINAL COUNT UP,

CLOCK DOWN

ZERO, ONE AND TWO.

4. COUNT DOWN TO ONE, ZERO,

TERMINAL COUNT DOWN, FIFTEEN, FOURTEEN AND THIRTEEN.

OUTPUTS

TERMINAL COUNT UP

TERMINAL COUNT DOWN

NOTES:

1. Master reset overrides load data and clock inputs.

2. When counting up, clock-down input must be high. When counting down, clock-up input must be high.

FIGURE 2. ’HC193 SYNCHRONOUS BINARY COUNTERS, TYPICAL RESET, PRESET AND COUNT SEQUENCES

013

PRESET

14 15 0 1 2

1 0 15 14 13

COUNT DOWNCOUNT UPRESET

CPU OR CPD

MAX

PHL

PLH

INPUT LEVEL

l/f

FIGURE 3. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE

WIDTH

INPUT LEVEL t

REC

PHL

INPUT LEVEL

INPUT LEVE

CPU OR CPD

PLH

FIGURE 5. PARALLELLOAD PULSE WIDTH, PARALLEL

LOAD TO OUTPUT DELAYS, AND PARALLEL LOAD TO CLOCK RECOVERY TIME

CPU OR CPD

TCU OR TCD

PHL

PLH

FIGURE 4. CLOCK TO TERMINAL COUNT DELAYS

INPUT LEVEL

REC

INPUT LEVEL

CPU OR CPD

PHL

FIGURE 6. MASTER RESET PULSE WIDTH, MASTER RESET

TO OUTPUT DELAY AND MASTER RESET TO CLOCK RECOVERY TIME

Page 10

Test Circuits and Waveforms (Continued)

FIGURE 7. SET-UP AND HOLD TIMES DATA TO PARALLEL LOAD (PL)

UP CLOCK

DOWN CLOCK

ASYNCHRONOUS,

PARALLEL LOAD

FIGURE 8. CASCADED UP/DOWN COUNTER WITH PARALLEL LOAD

234

RESET

PL Q

Q = p

(H)

P0 P1 P2 P3 CPU CPD PL

0Q1Q2Q3

tSU(L)

TCU

TCD

DATA INPUT

CPU CPD PL

OUTPUT

INPUT LEVEL

Q = p

P0 P1 P2 P3

0Q1Q2Q3

TCU TCD

BORROW CARRY

234

COUNT UP

89101112

COUNT DOWN

89101112

NOTE: Illegal states in BCD counters corrected in one count. NOTE: Illegal states in BCD counters corrected in one or two counts.

FIGURE 9. ’HC192, ’HCT193 STATE DIAGRAMS

Page 11

PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device

5962-8780801EA ACTIVE CDIP J 16 1 TBD Call TI Call TI

5962-9084801MEA ACTIVE CDIP J 16 1 TBD Call TI Call TI

9084801MEAS2035 OBSOLETE CDIP J 16 TBD Call TI Call TI

CD54HC192F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type CD54HC193F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type

CD54HCT193F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type

CD74HC192E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HC192EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HC192NSR ACTIVE SO NS 16 2000 Green (RoHS

CD74HC192NSRE4 ACTIVE SO NS 16 2000 Green (RoHS

CD74HC192NSRG4 ACTIVE SO NS 16 2000 Green (RoHS

CD74HC192PWR ACTIVE TSSOP PW 16 2000 Green (RoHS

CD74HC192PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS

CD74HC192PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS

CD74HC192PWT ACTIVE TSSOP PW 16 250 Green (RoHS

CD74HC192PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS

CD74HC192PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS

CD74HC193E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HC193EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HC193M ACTIVE SOIC D 16 40 Green (RoHS

CD74HC193M96 ACTIVE SOIC D 16 2500 Green (RoHS

Status

(1)

Package Type Package

Drawing

Pins Package Qty

Eco Plan

& no Sb/Br)

(2)

Lead/

Ball Finish

CU NIPDAU Level-1-260C-UNLIM

MSL Peak Temp

5-Sep-2011

(3)

Samples

(Requires Login)

Addendum-Page 1

Page 12

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device

CD74HC193M96E4 ACTIVE SOIC D 16 2500 Green (RoHS

CD74HC193M96G4 ACTIVE SOIC D 16 2500 Green (RoHS

CD74HC193ME4 ACTIVE SOIC D 16 40 Green (RoHS

CD74HC193MG4 ACTIVE SOIC D 16 40 Green (RoHS

CD74HC193MT ACTIVE SOIC D 16 250 Green (RoHS

CD74HC193MTE4 ACTIVE SOIC D 16 250 Green (RoHS

CD74HC193MTG4 ACTIVE SOIC D 16 250 Green (RoHS

CD74HCT193E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT193EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Status

(1)

Package Type Package

Drawing

Pins Package Qty

Eco Plan

& no Sb/Br)

(2)

Lead/

Ball Finish

CU NIPDAU Level-1-260C-UNLIM

MSL Peak Temp

(3)

(Requires Login)

5-Sep-2011

Samples

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 2

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PACKAGE OPTION ADDENDUM

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continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

5-Sep-2011

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC192, CD54HC193, CD54HCT193, CD74HC192, CD74HC193, CD74HCT193 :

Catalog: CD74HC192, CD74HC193, CD74HCT193

•

Military: CD54HC192, CD54HC193, CD54HCT193

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 3

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PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

CD74HC192NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC192PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC192PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD74HC193M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

Page 15

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width(mm) Height (mm)

CD74HC192NSR SO NS 16 2000 367.0 367.0 38.0

CD74HC192PWR TSSOP PW 16 2000 367.0 367.0 35.0

CD74HC192PWT TSSOP PW 16 250 367.0 367.0 35.0

CD74HC193M96 SOIC D 16 2500 333.2 345.9 28.6

Pack Materials-Page 2

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Datasheet CD74HC192Ε Specification

Specifications and Main Features

Frequently Asked Questions

User Manual