Datasheet CD4538BCWMX, CD4538BCWM, CD4538BCN, CD4538BCMX, CD4538BCM Datasheet (Fairchild Semiconductor)

October 1987
Revised January 1999

CD4538BC Dual Precision Monostable

© 1999 Fairchild Semiconductor Corporation DS006000.prf www.fairchildsemi.com

CD4538BC
Dual Precision Monostable

General Description

The CD4538BC is a dual, precision monostable multivibra­tor with independent t ri gger and re set con trols. The device
is retriggerable and resettable, and the contro l inputs are
internally latched. Two trigger inputs are provided to allow
either rising or falling edge triggering. The reset inputs are
active LOW and prevent triggering while active. Precise
control of output pulse-w idth has been achieved using lin­ear CMOS techniques. The pu lse duration and accuracy
are determined by exter nal components R

X

and CX. The

device does not allow the timing capacitor to discharge
through the timing pi n on power-down condition. For this
reason, no external protect ion resistor is r equire d in se ries
with the timing pin. Input protection from static discharge is
provided on all pins.

Features

■ Wide supply voltage range: 3.0V to 15V

■ High noise immunity: 0.45 V

CC

(typ.)

■ Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS

■ New formula: PW

OUT

= RC (PW in seconds, R in Ohms,

C in Farads)

■ ±1.0% pulse-width variation from part to part (typ.)

■ Wide pulse-width range: 1 µs to ∞

■ Separate latched reset inputs

■ Symmetrical output sink and source capability

■ Low standby current: 5 nA (typ.) @ 5 V

DC

■ Pin compatible to CD4528BC

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.

Connection Diagram

Pin Assignments for DIP and SOIC

Top View

Truth Table

H = HIGH Level
L = LOW Level

↑ = Transition from LOW-to-HIGH
↓ = Transition from HIGH-to-LOW



= One HIGH Level Pulse



= One LOW Level Pulse

X = Irrelevant

Order Number Package Number Package Description

CD4538BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CD4538BCWM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
CD4538BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Inputs Outputs

Clear A B Q Q

LXXLH
XHXLH
XXLLH
HL↓



H ↑ H



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CD4538BC

Block Diagram

RX and CX are External Com ponents
V

DD

= Pin 16

V

SS

= Pin 8

Logic Diagram

FIGURE 1.

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CD4538BC

Theory of Operation

FIGURE 2.

Trigger Operation

The block diagram of the CD4538B C is shown in Figure 1,
with circuit operation following.

As shown in Figure 1 and Fi gure 2, before an in put tr igger
occurs, the monostable is in the quiescent stat e with the Q
output low, and the timing capacitor C

X

completely charged

to V

DD

. When the trigger input A goes from VSS to V

DD

(while inputs B and CD are held to VDD) a valid trigger is
recognized, which turns on compara tor C1 and N-Chan nel
transistor N1

(1)

. At the same time the outp ut latch is set.

With transistor N1 on, the ca pacitor C

X

rapidly discharges

toward V

SS

until V

REF1

is reached. At th is point th e output

of comparator C1 changes state and transistor N1 turns off.
Comparator C1 then tu rn s off w hile at the sa me ti me com ­parator C2 turns on. With transistor N1 off, the capacitor C

X

begins to charge thr ough the timing resistor, RX, toward
V

DD

. When the voltage across CX equals V

REF2

, compara-

tor C2 changes state causing the output latch to reset (Q
goes low) while at the same time disabling comparator C2.
This ends the timing cycle with the mono stable in the qui­escent state, waiting for the next trigger.

A valid trigger is also recognized when trigger input B goes
from V

DD

to VSS (while input A is at VSS and input CD is at

V

DD

)

(2)

.

It should be noted that in the quiescent state C

X

is fully

charged to V

DD

, causing the current throu gh res istor RX to

be zero. Both comparators are “off” wi th the total device
current due only to r everse junction leakages. An a dded
feature of the CD4538BC is that th e output latch is set via
the input trigger withou t regard to the capacitor voltage.

Thus, propagation delay from trigger to Q is independent of
the value of C

X

, RX, or the duty cycle of the inpu t wave-

for m.

Retrigger Operation

The CD4538BC is retriggered if a valid trigger occurs

(3)

fol-

lowed by another valid t rigger

(4)

before the Q output has
returned to the quiescent (zero) state. Any retrigger, after
the timing node voltage at pin 2 or 14 has begun to r ise
from V

REF1

, but has not yet reached V

REF2

, will cause an
increase in output pulse width T. When a valid retrigger is
initiated

(4)

, the voltage at T2 will again drop to V

REF1

before

progressing along the RC charg ing cur ve toward V

DD

. The

Q output will remain high until time T, after the last valid
retrigger.

Reset Operation

The CD4538BC may be reset dur ing t he generatio n of the
output pulse. In the reset mode of operation, an input pulse
on C

D

sets the reset latch an d causes the c apacitor to be

fast charged to V

DD

by turning on transistor Q1

(5)

. When

the voltage on the capacitor r each es V

REF2

, the reset latch

will clear and then be ready to accept another pulse. If the
C

D

input is held low, any trigger inputs that occur will be

inhibited and the Q and Q

outputs of the output la tch will
not change. Since the Q output is reset when an input low
level is detected on the C

D

input, the output pulse T can be

made significantly shor ter than the minimum pulse width
specification.

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CD4538BC

FIGURE 3. Retriggerable Monostables Circuitry

FIGURE 4. Non-Retriggerable Monostables Circuitry

FIGURE 5. Connection of Unused Sections

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CD4538BC

Absolute Maximum Ratings(Note 1)

(Note 2)

Recommended Operating
Conditions

(Note 2)

Note 1: “Absolute Maximum Rat ings” are tho se values beyond which the
safety of the device cannot be guaranteed, they are not meant to imply that
the devices should be o perated at these limits. The tables of “R ecom­mended Operating Conditions” and “Electrical Characteristics” provide con­ditions for actual device operat ion.

Note 2: V

SS

= 0V unless otherw is e s pecified.

DC Electrical Characteristics (Note 2)

Note 3: IOH and IOL are tested one output at a ti m e.

DC Supply Voltage (VDD) −0.5 to +18 V

DC

Input Voltage (VIN) −0.5V to VDD + 0.5 V

DC

Storage Temperature Range (TS) −65°C to +150°C
Power Dissipation (P

D

)
Dual-In-Line 700 mW
Small Outline 500 mW

Lead Temperature (T

L

)
(Soldering, 10 seconds) 260°C

DC Supply Voltage (V

DD

) 3 to 15 V

DC

Input Voltage (VIN) 0 to VDD V

DC

Operating Temperature Range (TA) −40°C to +85°C

Symbol Parameter Conditions

−40°C +25°C +85°C

Units

Min Max Min Typ Max Min Max

I

DD

Quiescent VDD = 5V VIH = V

DD

20 0.005 20 150 µA

Device Current VDD = 10V VIL = V

SS

40 0.010 40 300 µA

VDD = 15V All Outputs Open 80 0.015 80 600 µA

V

OL

LOW Level VDD = 5V |IO| < 1 µA 0.05 0 0.05 0.05 V
Output Voltage VDD = 10V VIH = VDD, VIL = V

SS

0.05 0 0.05 0.05 V

VDD = 15V 0.05 0 0.05 0.05 V

V

OH

HIGH Level VDD = 5V |IO| < 1 µA 4.95 4.95 5 4.95 V
Output Voltage VDD = 10V VIH = VDD, VIL = VSS9.95 9.95 10 9.95 V

VDD = 15V 14.95 14.95 15 14.95 V

V

IL

LOW Level |IO| < 1 µA
Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 V

VDD = 10V, VO = 1.0V or 9.0V 3.0 4.50 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0 V

V

IH

HIGH Level |IO| < 1 µA
Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 V

VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 5.50 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0 V

I

OL

LOW Level VDD = 5V, VO = 0.4V VIH = VDD0.52 0.44 0.88 0.36 mA
Output Current VDD = 10V, VO = 0.5V VIL = VSS1.3 1.1 2.25 0.9 mA
(Note 3) VD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA

I

OH

HIGH Level VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
Output Current VDD = 10V, VO = 9.5V VIL = VSS−1.3 −1.1 −2.25 −0.9 mA
(Note 3) VD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA

I

IN

Input Current, VDD = 15V, VIN = 0V or 15V ±0.02 ±10−5±0.05 ±0.5 µA
Pin 2 or 14

I

IN

Input Current VDD = 15V, VIN = 0V or 15V ±0.3 ±10−5±0.3 ±1.0 µA
Other Inputs

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CD4538BC

AC Electrical Charac teristics (Note 4)

TA = 25°C, CL = 50 pF, and tr = tf = 20 ns unless otherwise specified

Note 4: AC parameters ar e guaranteed by DC correla te d t es t ing.
Note 5: The maximum us able resista nce R

X

is a function of the leak age of t he C apa cit or CX, leakage of t he C D4 538BC, a nd leak age du e t o boa rd layout,

surface resistance, etc.

Symbol Parameter Conditions Min Typ Max Units

t

TLH

, t

THL

Output Transition Time VDD = 5V 100 200 ns

VDD = 10V 50 100 ns
VDD = 15V 40 80 ns

t

PLH

, t

PHL

Propagation Delay Time Trigger Operation—

A or B to Q or Q
VDD = 5V 300 600 ns
VDD = 10V 150 300 ns
VDD = 15V 100 220 ns
Reset Operation—

CD to Q or Q
VDD = 5V 250 500 ns
VDD = 10V 125 250 ns
VDD = 15V 95 190 ns

tWL, t

WH

Minimum Input Pulse Width VDD = 5V 35 70 ns
A, B, or C

D

VDD = 10V 30 60 ns
VDD = 15V 25 50 ns

t

RR

Minimum Retrigger Time VDD = 5V 0 ns

VDD = 10V 0 0 ns
VDD = 15V 0 ns

C

IN

Input Capacitance Pin 2 or 14 10 pF

Other Inputs 5 7.5 pF

PW

OUT

Output Pulse Width (Q or Q)

RX = 100 kΩ

VDD = 5V 208 226 244 µs

(Note: For Typical Distribution, CX = 0.002 µFV

DD

= 10V 211 230 248 µs

see Figure 6) VDD = 15V 216 235 254 µs

RX = 100 kΩ VDD = 5V 8.83 9.60 10.37 ms
CX = 0.1 µFV

DD

= 10V 9.02 9.80 10.59 ms

VDD = 15V 9.20 10.00 10.80 ms
RX = 100 kΩ VDD = 5V 0.87 0.95 1.03 s
CX = 10.0 µFV

DD

= 10V 0.89 0.97 1.05 s

VDD = 15V 0.91 0.99 1.07 s

Pulse Width Match between RX = 100 kΩ VDD = 5V ±1%
Circuits in the Same Package CX = 0.1 µFV

DD

= 10V ±1%

CX = 0.1 µF, RX = 100 kΩ VDD = 15V ±1%

Operating Conditions

R

X

External Timing Resistance 5.0 (Note 5) kΩ

C

X

External Timing Capacitance 0 No Limit pF

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CD4538BC

Typical Applications

FIGURE 6. Typical Normalized Distribution of Units

for Output Pulse Width

FIGURE 7. Typical Pulse Width Variation as a

Function of Supply Voltage V

DD

FIGURE 8. Typical Total Supply Current Versus

Output Duty Cycle, R

X

= 100 kΩ, CL = 50 pF,

C

X

= 100 pF, One Monostable Switching Only

FIGURE 9. Typical Pulse Width Error

Versus Temperature

FIGURE 10. Typical Pulse Width Error

Versus Temperature

FIGURE 11. Typical Pulse Width Versus

Timing RC Product

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CD4538BC

Test Circuits and Waveforms

FIGURE 12. Switching Test Waveforms

*CL = 50 pF

Input Connections

*Includes capac ita nc e of probes, wiring, an d f ix tu re parasitic

Note: Switching test waveforms for PG1, PG2, PG3 are shown in Figure 12.

FIGURE 13. Switching Test Circuit

Characteristics CD A B

t

PLH

, t

PHL

, t

TLH

, t

THL

VDDPG1 V

DD

PW

OUT

, tWH, t

WL

t

PLH

, t

PHL

, t

TLH

, t

THL

VDDVSSPG2

PW

OUT

, tWH, t

WL

t

PLH(R)

, t

PHL(R)

, PG3 PG1 PG2

t

WH

, t

WL

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CD4538BC

RX = RX′ = 100 kΩ
C

X

= CX′ = 100 pF

C

1

= C2 = 0.1 µF

Duty Cycle = 50%

FIGURE 14. Power Dissipation Test

Circuit and Waveforms

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CD4538BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

Package Number M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M16B

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are i mplied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

CD4538BC Dual Precision Monostable

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant injur y to the
user.

2. A critical compon ent in any com ponent of a li fe support
device or system whose failure to p erform can be r ea­sonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E