Datasheet CD4532BMS Datasheet (Intersil Corporation)

CD4532BMS

December 1992

Features

• High Voltage Type (20V Rating)

• Converts From 1 of 8 to Binary

• Provides Cascading Feature to Handle Any Number of
Inputs

• Group Select Indicates One or More Priority Inputs

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Pack­age Temperature Range; 100nA at 18V and +25

• Noise Margin (Over Full Package/Temperature Range)

- 0.5V at VDD = 5V

- 1.5V at VDD = 10V

- 1.5V at VDD = 15V

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”

Applications

CMOS 8-Bit Priority Encoder

Pinout

CD4532BMS

TOP VIEW

VDD

1

D4

2

D5
D6

3
4

D7

5

EI

Q2

6

o

C

Q1

VSS

7
8

Functional Diagram

D7

PRIORITY

SELECT

16

E0

15

GS

14

D3

13

D2

12

D1

11

D0

10

Q0

9

ENCODER

Q2
Q1
Q0

• Priority Encoder

• Binary or BCD Encoder (Keyboard Encoding)

• Floating Point Arithmetic

Description

CD4532BMS consists of combinational logic that encodes
the highest priority input (D7 - D0) to a 3-bit binary code. The
eight inputs, D7 through D0, each have an assigned priority;
D7 is the highest priority and D0 is the lowest. The priority
encoder is inhibited when the chip-enable input E1 is low.
When E1 is high, the binary representation of the highest­priority input appears on output lines Q2 - Q0, and the group
select line GS is high to indicate that priority inputs are
present. The enable-out (EO) is high when no priority inputs
are present. If any one input is high, EO is low and all cas­caded lower-order stages are disabled.

The CD4532BMS is supplied in these 16-lead outline packages:
Braze Seal DIP H4T

Frit Seal DIP H1E
Ceramic Flatpack H6W

D0

E1

E0

GS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

7-1227

File Number

3344

Specifications CD4532BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC

Package Types D, F, K, H

Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA

VDD = 18V, VIN = VDD or GND 3 -55oC-10µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low
(Note 2)

Input Voltage High
(Note 2)

Input Voltage Low
(Note 2)

Input Voltage High
(Note 2)

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs.

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

Thermal Resistance . . . . . . . . . . . . . . . . θ

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW

For TA = +100oC to +125oC (Package Type D, F, K). . . . . .Derate

Linearity at 12mW/oC to 200mW

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

GROUP A

SUBGROUPS TEMPERATURE

2 +125oC - 1000 µA

2 +125oC -1000 - nA

2 +125oC - 1000 nA

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.

ja

LIMITS

VDD/2

VOL <
VDD/2

θ

jc

UNITSMIN MAX

V

7-1228

Specifications CD4532BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A

PARAMETER SYMBOL CONDITIONS (NOTE 1, 2)

Propagation Delay
E1 to E0
E1 to GS

Propagation Delay
E1 to QM
DN to GS

Propagation Delay
DN to QM

Transition Time TTHL

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,

TPHL1
TPLH1

TPHL2
TPLH2

TPHL3
TPLH3

TTLH

VDD = 5V, VIN = VDD or GND 9 +25oC - 220 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 340 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 440 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

SUBGROUPS TEMPERATURE

10, 11 +125oC, -55oC - 297 ns

10, 11 +125oC, -55oC - 459 ns

10, 11 +125oC, -55oC - 594 ns

10, 11 +125oC, -55oC - 270 ns

+125oC - 150 µA

+125oC - 300 µA

+125oC - 600 µA

-55oC

-55oC

-55oC

-55oC

-55oC 0.64 - mA

-55oC 1.6 - mA

-55oC 4.2 - mA

-55oC - -0.64 mA

-55oC - -2.0 mA

-55oC - -1.6 mA

-55oC - -4.2 mA

-55oC

LIMITS

UNITSMIN MAX

LIMITS

UNITSMIN MAX

-50mV

-50mV

4.95 - V

9.95 - V

-3V

7-1229

Specifications CD4532BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

+7 - V

-55oC

o

Propagation Delay
E1 to E0
E1 to GS

TPHL1
TPLH1

Propagation Delay
E1 to QM
DN to GS

Propagation Delay
DN to QM

TPHL2
TPLH2

TPLH3
TPHL3

Transition Time TTHL

TTLH

VDD = 10V 1, 2, 3 +25
VDD = 15V 1, 2, 3 +25

VDD = 10V 1, 2, 3 +25oC - 170 ns
VDD = 15V 1, 2, 3 +25

VDD = 10V 1, 2, 3 +25
VDD = 15V 1, 2, 3 +25oC - 160 ns
VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns

C - 110 ns

o

C - 85 ns

o

C - 125 ns

o

C - 220 ns

Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

UNITSMIN MAX

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

UNITSMIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage

∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V

Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage

∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

VDD/2

Propagation Delay Time TPHL

VDD = 3V, VIN = VDD or GND
VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

TPLH

VOL <
VDD/2

ns

+25oC

Limit

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

3. See Table 2 for +25oC limit.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

V

7-1230

Specifications CD4532BMS

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883

CONFORMANCE GROUP

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

CONFORMANCE GROUPS

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

METHOD GROUP A SUBGROUPS READ AND RECORD

TABLE 7. TOTAL DOSE IRRADIATION

MIL-STD-883

METHOD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

TEST READ AND RECORD

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR

FUNCTION OPEN GROUND VDD 9V ± -0.5V

Static Burn-In 1
(Note 1)

Static Burn-In 2
(Note 1)

Dynamic Burn­In (Note 1)

Irradiation
(Note 2)

NOTES:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

6, 7, 9, 14, 15 1 - 5, 8, 10 - 13 16

6, 7, 9, 14, 15 8 1 - 5, 10 - 13, 16

- 8 5, 16 6, 7, 9, 14, 15 1 - 4, 10 - 13

6, 7, 9, 14, 15 8 1 - 5, 10 - 13, 16

50kHz 25kHz

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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P. O. Box 883, Mail Stop 53-204
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1231

Logic Diagram

D1
11

*

CD4532BMS

VDD

16

D2
12

*

D3
13

*

D4

1

*

D5

2

*

D6

3

*

D7

4

*

D0
10

*

EI

5

*

VDD

Q0

9

Q1

7

Q2

6

GS

14

E0

15

VSS

8

*ALL INPUTS PROTECTED BY

CMOS PROTECTION NETWORK

VSS

FIGURE 1. CD4532BMS LOGIC DIAGRAM

TRUTH TABLE

INPUT OUTPUT

E1 D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0 E0

0XXXXXXXX00000
10000000000001
11XXXXXXX11110
101XXXXXX11100
1001XXXXX11010
10001XXXX11000
100001XXX10110
1000001XX10100
10000001X10010
10000000110000

X = Don’t Care Logic 1 ≡ High Logic 0 ≡ Low

7-1232

Typical Performance Characteristics

CD4532BMS

AMBIENT TEMPERATURE (TA) = +25oC

30

25

20

15

10

5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

AMBIENT TEMPERATURE (TA) = +25oC

15.0

12.5

10.0

7.5

5.0

2.5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

0-5-10-15

0

-5

-10

-15

-20

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

0-5-10-15

0

-5

-10

-25

-15V

-30

FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

600

500

400

300

200

100

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

0 2.5 7.5 12.55 10 15 17.5 20

LOAD CAPACITANCE (CL) = 50pF

SUPPLY VOLTAGE (VDD) (V)

-15V

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

200

150

100

50

0

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

10 20 30 40 50 60 70 80 90 100

SUPPLY VOLTAGE (VDD) = 5V

LOAD CAPACITANCE (CL) (pF)

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

10V

15V

FIGURE 6. TYPICAL PROPAGATION DELAY (DN TO QM ) vs

SUPPLY VOLTAGE

FIGURE 7. TYPICAL PROPAGATION DELAY (E1 TO GS,

E1 TO EQ) vs LOAD CAPACITANCE

7-1233

CD4532BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE (TA) = +25oC

300

SUPPLY VOLTAGE (VDD) = 5V

250

200

150

10V

100

15V

50

0

PROPAGATION DELAY TIME (tPLH, tPHL) (ns)

10 20 30 40 50 60 70 80 90 100

LOAD CAPACITANCE (CL) (pF)

FIGURE 8. TYPICAL PROPAGATION DELAY (DN TO QM) vs

LOAD CAPACITANCE

5

10

8
6

AMBIENT TEMPERATURE (TA) = +25oC

4
2

4

10

8
6

SUPPLY VOLTAGE (VDD) = 15V

4

LOAD CAPACITANCE (CL) = 50pF

2

3

10

8
6
4

2

2

10

8
6
4

2

10

8
6
4

2

DYNAMIC POWER DISSIPATION (PD) (µW)

1

864286422

11010

FREQUENCY (f) (kHz)

FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION vs FREQUENCY

AMBIENT TEMPERATURE (TA) = +25oC

200

150

SUPPLY VOLTAGE (VDD) = 5V

100

10V

50

TRANSITION TIME (tTHL, tTLH) (ns)

0

0 40 60 80 10020

15V

LOAD CAPACITANCE (CL) (pF)

FIGURE 9. TYPICAL TRANSITION TIME vs LOAD

CPACITANCE

10V
50pF

10V
15pF

5V
50pF

2864

2

864

3

10

4

10

Applications

D15

D8

D7

D0

EI

5

EI

4

D7

3
2

1
13
12
11
10

D0

5

EI

4

D7

3

2

1
13
12
11
10

D0

14

GS

6

Q2

7

Q1

9

Q0

15

E0

14

GS

6

Q2

7

Q1

9

Q0

CD4532BMS CD4532BMS

15

E0

FIGURE 11. 16-LEVEL PRIORITY ENCODER

7-1234

CD4071BMS
1
2

5
6

8
9

12
13

Q3’

3

4

10

11

GS’

Q2’

Q1’

Q0’

E0’

CD4532BMS

Applications (Continued)

1/4 CD4071BMS

D9
D8

1/6 CD4069BMS

CD4532BMS

EI

D7

D0

D7

D0

GS

Q2

Q1

Q0

1/4 CD4071BMS

FIGURE 12. 0-TO-9 KEYBOARD ENCODER

TRUTH TABLE

INPUT OUTPUT

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GS Q3’ Q2’ Q1’ Q0’

1XXXXXXXXX01001
01XXXXXXXX01000
001XXXXXXX10111
0001XXXXXX10110
00001XXXXX10101
000001XXXX10100
0000001XXX10011
00000001XX10010
000000001X10001
000000000110000

X = Don’t Care Logic 1 ≡ High Logic 0 ≡ Low

Q3’

Q2’
Q1’

Q0’

Chip Dimensions and Pad Layout

Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10

-3

inch).

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

7-1235