Datasheet CD4516BMS, CD4510BMS Datasheet (Intersil Corporation)

CD4510BMS, CD4516BMS

Data Sheet December 1992 File Number 3338

CMOS Presettable Up/Down Counters

CD4510BMS Presettable BCD Up/Down Counter and the
CD4516BMS Presettable Binary Up/Down counter consist of
four synchronously clocked D-type flip-flops (with a gating
structure to provide T-type flip-flop capability) connected as
counters. These counters can be cleared by a high level on
the RESET line, and can be preset to any binary number
present on the jam inputs by a high level on the PRESET
ENABLE line. The CD4510BMS will count out of non-BCD
counter states in a maximum of two clock pulses in the up
mode, and a maximum of four clock pulses in the down mode.

If the CARRY IN input is held low, the counter advances up or
down on each positive-going clock transition. Synchronous
cascading is accomplished by connecting all clock inputs in
parallel and connecting the CARRY OUT of a less significant
stage to the CARRY IN of a more significant stage.

The CD4510BMS and CD4516BMS can be cascaded in the
ripple mode by connecting the CARRY OUT to the clock of
the next stage. If the UP/DOWN input changes during a ter­minal count, the CARRY OUT must be gated with the clock,
and the UP/DOWN input must change while the clock is
high. This method provides a clean clock signal to the sub­sequent counting stage. (See Figures 13, 14.)

These devices are similar to types MC14510 and MC14516.

Features

• High Voltage Types (20V Rating)

• CD4510BMS - BCD Type

• CD4516BMS - Binary Type

• Medium Speed Operation

- fCL = 8MHz Typ. at 10V

• Synchronous Internal Carry Propagation

• Reset and Preset Capability

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”

o

C

The CD4510BMS and CD4516BMS are supplied in these
16-lead outline packages:

Braze Seal DIP *H4W †H45
Frit Seal DIP *FBF †H1F
Ceramic Flatpack H6W
*CD4510B Only †CD4516B Only

Pinout

CD4510BMS, CD4516BMS

TOP VIEW

VDD

PRESET ENABLE

Q4

P4
P1

CARRY IN

Q1

CARRY OUT

VSS

1
2
3
4
5
6
7
8

16
15

CLOCK
Q3

14

P3

13

P2

12

Q2

11

UP/DOWN

10

9

RESET

Applications

• Up/Down Difference Counting

• Multistage Synchronous Counting

• Multistage Ripple Counting

• Synchronous Frequency Dividers

Functional Diagram

PRESET ENABLE

1

4

P1

12

P2

13

P3

3

P4

CLOCK

UP/DOWN

CARRY IN

RESET

15
10

5

9

6
11
14

2

7

Q1
Q2
Q3
Q4

CARRY OUT

VDD = 16
VSS = 8

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

CD4510BMS, CD4516BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . .-0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA

VDD = 18V, VIN = VDD or GND 3 -55oC-10µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low
(Note 2)

Input Voltage High
(Note 2)

Input Voltage Low
(Note 2)

Input Voltage High
(Note 2)

NOTES: 1. All voltages referenced to device GND, 100% testing being im-

plemented.

2. Go/No Go test with limits applied to inputs.

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

Thermal Resistance. . . . . . . . . . . . . . . . θ

Ceramic DIP and FRIT Package . . . . 80oC/W 20oC/W

Flatpack Package. . . . . . . . . . . . . . . . 70oC/W 20oC/W

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55oC to +100oC (Package Type D, F, K) . . . . . .500mW

For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate

Linearity at 12mW/oC to 200mW

Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC

GROUP A

SUBGROUPS TEMPERATURE

2 +125oC - 1000 µA

2 +125oC -1000 - nA

2 +125oC - 1000 nA

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

3. Foraccuracy,voltage ismeasured differentially toVDD. Limitis

0.050V max.

ja

LIMITS

VDD/2

VOL <
VDD/2

θ

jc

UNITSMIN MAX

V

2

CD4510BMS, CD4516BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1, 2)

Propagation Delay
Clock to Q Output

Propagation Delay
Preset or Reset to Q

Propagation Delay
Clock to Carry Out

Propagation Delay
Carry In to Carry Out

Propagation Delay
Preset or Reset to Carry
Out

Transition Time TTHL

Maximum Clock Input Fre­quency

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

3. Reset to Carry Out (TPLH) only.

TPHL1
TPLH1

TPHL2
TPLH2

TPHL3
TPLH3

TPHL4
TPLH4

TPHL5
TPLH5

TTLH

FCL VDD = 5V, VIN = VDD or GND 9 +25oC 2 - MHz

VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 420 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 480 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 250 ns

VDD = 5V, VIN = VDD or GND
(Note 3)

VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

GROUP A

SUBGROUPS TEMPERATURE

10, 11 +125oC, -55oC - 540 ns

10, 11 +125oC, -55oC - 567 ns

10, 11 +125oC, -55oC - 648 ns

10, 11 +125oC, -55oC - 338 ns

9 +25oC - 640 ns

10, 11 +125oC, -55oC - 864 ns

10, 11 +125oC, -55oC - 270 ns

10, 11 +125oC, -55oC 1.48 - MHz

LIMITS

UNITSMIN MAX

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA

+125oC - 150 µA

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

+125oC - 300 µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

+125oC - 600 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -

55oC

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -

55oC

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -

55oC

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -

55oC

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

-55oC 0.64 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

-55oC 1.6 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

-55oC 4.2 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

-55oC - -0.64 mA

-50mV

-50mV

4.95 - V

9.95 - V

UNITSMIN MAX

3

CD4510BMS, CD4516BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

-55oC - -2.0 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

-55oC - -1.6 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

-55oC - -4.2 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -

55oC

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -

55oC

Propagation Delay
Clock to Q Output

Propagation Delay
Preset or Reset to Q

Propagation Delay
Clock to Carry Out

Propagation Delay
Carry In to Carry Out

Propagation Delay Preset
or Reset to Carry Out

Transition Time TTLH

Maximum Clock Input Fre­quency

Minimum Hold Time
Preset Enable to JN

MinimumDataSetup Time
Preset Enable to JN

Minimum Data Hold Time
Clock to Carry In

Minimum Clock HoldTime
Clock to Up/Down

Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF

NOTES:

1. All voltages referenced to device GND.

2. The parameterslistedon Table 3 are controlledvia design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4. Reset to Carry Out (TPLH) only.

TPHL1
TPLH1

TPHL2
TPLH2

TPHL3
TPLH3

TPHL4
TPLH4

TPHL5
TPLH5

TTHL

FCL VDD = 10V 1, 2 +25oC 4 - MHz

TH VDD = 5V 1, 2, 3 +25oC - 70 ns

TS VDD = 5V 1, 2, 3 +25oC - 25 ns

TH VDD = 5V 1, 2, 3 +25oC - 60 ns

TH VDD = 5V 1, 2, 3 +25oC - 30 ns

VDD = 10V 1, 2, 3 +25oC - 200 ns
VDD = 15V 1, 2, 3 +25oC - 150 ns
VDD = 10V 1, 2, 3 +25oC - 210 ns
VDD = 15V 1, 2, 3 +25oC - 160 ns
VDD = 10V 1, 2, 3 +25oC - 240 ns
VDD = 15V 1, 2, 3 +25oC - 180 ns
VDD = 10V 1, 2, 3 +25oC - 120 ns
VDD = 15V 1, 2, 3 +25oC - 100 ns
VDD = 10V 1, 2, 3, 4 +25oC - 320 ns
VDD = 15V 1, 2, 3, 4 +25oC - 250 ns
VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns

VDD = 15V 1, 2 +25oC 5.5 - MHz

VDD = 10V 1, 2, 3 +25oC - 40 ns
VDD = 15V 1, 2, 3 +25oC - 40 ns

VDD = 10V 1, 2, 3 +25oC - 10 ns
VDD = 15V 1, 2, 3 +25oC - 10 ns

VDD = 10V 1, 2, 3 +25oC - 30 ns
VDD = 15V 1, 2, 3 +25oC - 30 ns

VDD = 10V 1, 2, 3 +25oC - 30 ns
VDD = 15V 1, 2, 3 +25oC - 30 ns

-3V

+7 - V

UNITSMIN MAX

4

CD4510BMS, CD4516BMS

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage

Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage

Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

Propagation Delay Time TPHL

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V

∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

VOL <
VDD = 3V, VIN = VDD or GND
VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

TPLH

3. See Table 2 for +25oC limit.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

VDD/2

VDD/2

+25oC

Limit

UNITSMIN MAX

ns

V

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883

CONFORMANCE GROUP

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

CONFORMANCE GROUPS

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

METHOD GROUP A SUBGROUPS READ AND RECORD

TABLE 7. TOTAL DOSE IRRADIATION

MIL-STD-883

METHOD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

TEST READ AND RECORD

5

CD4510BMS, CD4516BMS

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR

FUNCTION OPEN GROUND VDD 9V ± -0.5V

50kHz 25kHz

CD4510BMS
Static Burn-In 1

(Note 1)
Static Burn-In 2

(Note 1)
Dynamic Burn-

2, 6, 7, 11, 14 1, 3-5, 8-10, 12, 13,

16

15

2, 6, 7, 11, 14 8 1,3-5,9,10, 12, 13,

15, 16

- 1, 3, 4, 8, 9, 12, 13 10, 16 2, 6, 7, 11, 14 15 5

In (Note 1)
Irradiation

(Note 2)

2, 6, 7, 11, 14 8 1,3-5,9,10, 12, 13,

15, 16

NOTES:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

Logic Diagrams

RESET

PRESET*

ENABLE

CLOCK*

CARRY OUT

CARRY IN*

UP/DOWN

P1*

C
T

4Q16

P

QPE

Q

9

*

1

15

7

5

10

*

U/D

U/D

P

C
T

P2*

12Q211

QPE

Q

P

C
T

P3*

13Q314

QPE

Q

C
T

P4*

3Q42

P

QPE

Q

Q4Q3Q3Q2Q2Q1

Q4

VDD

VSS

Q1

ALL INPUTS ARE PROTECTED

*

BY CMOS PROTECTION
NETWORK

6

Q4

U/D

Q3

Q4

U/D

FIGURE 1. CD4510BMS

U/D

Q3 U/D

Q2

U/D

U/D

Q4Q2Q2

Q2Q3U/DQ2Q3Q3Q4

Logic Diagrams (Continued)

CD4510BMS, CD4516BMS

RESET

PRESET*

ENABLE

CLOCK

CARRY OUT

CARRY IN*

UP/DOWN

P1*

C
T

4Q16

P

QPE

Q

9

*

1

15

*

7

5

10

*

U/D

U/D

P

C
T

P2*

12Q211

QPE

Q

P

C
T

P3*

13Q314

QPE

Q

C
T

P4*

3Q42

P

QPE

Q

Q4Q3Q3Q2Q2Q1

Q4

VDD

VSS

Q1

Q3

U/D

Q4Q2

Q4

ALL INPUTS ARE PROTECTED

*

BY CMOS PROTECTION
NETWORK

U/D

Q3

FIGURE 2. CD4516BMS

TRUTH TABLE

CL CI U/D PE R ACTION

X 1 X 0 0 NO COUNT

0100COUNT UP

0000COUNT DOWN
X X X 1 0 PRESET
XXXX1RESET

X = DON’T CARE

U/D

U/D

U/D

Q2Q2Q2

Q2Q3U/DQ2Q3

7

CD4510BMS, CD4516BMS

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC

30

25

20

15

10

5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTA GE (VDS) (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTA GE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

AMBIENT TEMPERATURE (TA) = +25oC

15.0

12.5

10.0

7.5

5.0

2.5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTA GE (VDS) (V)

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

0-5-10-15

0

-5

-10

DRAIN-TO-SOURCE VOLTA GE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

0-5-10-15

0

-5

-15

-10V

-15V

-20

-25

-30

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

200

150

100

TRANSITION TIME (tTLH) (ns)

50

SUPPL Y VOLT A GE (VDD) = 5V

10V
15V

-15V

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

250

200

150

100

50

-10V

SUPPLY VOLTAGE (VDD) = 5V

10V

15V

-10

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

0

0 40 60 80 10020

LOAD CAPACITANCE (CL) (pF)

FIGURE 7. TYPICAL TRANSITION TIME vs LOAD

CAPACITANCE

8

PROPAGATION DELAY TIME (tPLH, tPHL) (ns)

0 20 40 60 80 100

LOAD CAPACITANCE (CL) (pF)

FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD

CAPACITANCE FOR CLOCK-TO-Q OUTPUTS

CD4510BMS, CD4516BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50pF

15

10

(fCL MAX) (MHz)

5

MAXIMUM CLOCK INPUT FREQUENCY

0

5101520

SUPPL Y VOLT A GE (VDD)

4

10

AMBIENT TEMPERATURE (TA)

o

8

= +25

C

6

tr, tf = 20ns

4
2

SUPPLY VOLTS (VDD) = 15V

3

10

8
6

POWER DISSIPATION PER GATE (PD) (µW)

10

10

4

2

2

8
6

4

2

01 1

5V

8642

10V

10V

CL = 50pF
CL = 15pF

8642

10

INPUT FREQUENCY (fCL) (kHz)

8642

2

10

8642

3

10

8642

4

10

FIGURE 9. TYPICALMAXIMUMCLOCK INPUTFREQUENCYvs

SUPPLY VOLTAGE

Test Circuit and Waveform

CL

CL

100µF

CL

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

FIGURE 11. PO WER DISSIPATION TEST CIRCUIT AND INPUT WAVEFORM

ID

500µF

PULSE

GENERATOR

CL

CL

Acquisition System

SAMPLE

AND

HOLD

CONVERSION

LOGIC

ANALOG

DAT A

INPUTS

16 CHANNEL

MULTIPLEXER

CD4067

SELECT

INPUTS

PRESET

INPUTS

AMPLI­FIER

Q1 Q4

CD4516BMS

FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION vs

FREQUENCY

20ns

90%

50%

VARIABLE

WIDTH

10 BIT

START

CLOCK

END

A/D

CONVERTER

NOTE:
This acquisition system can be operated in the random access mode by

jamming in the channel number at the present inputs, or in the sequential
mode by clocking the CD4516BMS.

P ARALLEL
DAT A
OUTPUTS

VDD

10%

20ns

VSS

CLOCK

PRESET ENABLE

FIGURE 12. TYPICAL 16 CHANNEL, 10 BIT DATA ACQUISITION SYSTEM

9

Timing Diagrams

CARRY IN
UP/DOWN

CARRY OUT

CLOCK

RESET

PE

P1
P2

P3
P4

Q1
Q2
Q3
Q4

COUNT

CD4510BMS, CD4516BMS

01234567898765432100967

0

CLOCK

CARRY IN
UP/DOWN

RESET

PE
P1

P2
P3

P4
Q1
Q2
Q3
Q4

CARRY OUT

COUNT

FIGURE 13. CD4510BMS

567891011121314159876543210015

VDD
VSS

0

10

FIGURE 14. CD4516BMS

UP/DOWN

PRESET

ENABLE

CD4510BMS, CD4516BMS

PARALLEL CLOCKING

UP/DRPE

CI CO

CLOCK

RESET

J1 J2 J3 J4

CD4510/16BMS

CL Q1 Q2 Q3 Q4

UP/DRPE

CI CO

J1 J2 J3 J4 UP/DRPE

CD4510/16BMS CD4510/16BMS

CL Q1 Q2 Q3 Q4

CI CO

CL Q1 Q2 Q3 Q4

J1 J2 J3 J4

*

* CARR YOUT lines at the 2nd, 3rd, etc., stages may have a negative-going glitch pulse resulting from differential delays of different CD4010/16BMS

IC’S.These negative going glitches do not affect proper CD4029BMS operation. However,if the CARRYOUT signals are used to trigger other edge­sensitive logic devices, such as FF’S or counters, the CARRY OUT signals should be gated with the clock signal using a 2-input OR gate such as
CD4071BMS.

RIPPLE CLOCKING

UP/DOWN

PRESET

ENABLE

UP/DRPE

CI CO

CLOCK

RESET

J1 J2 J3 J4 UP/DRPE

CD4510/16BMS CD4510/16BMS CD4510/16BMS

CL Q1 Q2 Q3 Q4

CI CO

J1 J2 J3 J4 UP/DRPE

CL Q1 Q2 Q3 Q4

1/4 CD4071B

J1 J2 J3 J4

CI CO

CL Q1 Q2 Q3 Q4

Ripple Clocking Mode: The up/down control can be changed at any count. The only restriction on changing the up/down control is that the
clock input to the first counting stage must be high. For cascading counters operating in a fixed up-count or down-count mode, the OR gates
are not required between stages, and CO is connected directly to the CL input of the next stage with CI grounded.

FIGURE 15. CASCADING COUNTER PACKAGES

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]

11