Datasheet CD4515BMS, CD4514BMS Datasheet (Intersil Corporation)

December 1992

CD4514BMS
CD4515BMS

CMOS 4-Bit

Latch/4-to-16 Line Decoders

Features

• High-Voltage Types (20-Volt Rating)

• CD4514BMS Output “High” on Select

• CD4515BMS Output “Low” on Select

• Strobed Input Latch

• Inhibit Control

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and 25

o

C

• Noise Margin (Full Package-Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• 5V, 10V, and 15V Parametric Ratings

• Standardized, Symmetrical Output Characteristics

• Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
‘B’ Series CMOS Devices"

Applications

• Digital Multiplexing

• Address Decoding

• Hexadecimal/BCD Decoding

• Program-counter Decoding

• Control Decoder

Description

CD4514BMS and CD4515BMS consist of a 4-bit strobed
latch and a 4-to-16-line decoder. The latches hold the last
input data presented prior to the strobe transition from 1 to 0.
Inhibit control allows all outputs to be placed at
0(CD4514BMS) or 1(CD4515BMS) regardless of the state of
the data or strobe inputs.

Pinout

CD4514BMS, CD4515BMS

TOP VIEW

S7
S6
S5
S4
S3

S2
S1
S0

VSS

1
2
3
4
5
6
7
8

9
10
11
12

STROBE

DATA 1
DATA 2

Functional Diagram

VDD = 24
VSS = 12

DATA 1 2
DATA 2 3
DATA 3 21
DATA 4 22

STROBE 1

INHIBIT 23

LATCH

A
B
C
D

24

VDD
INHIBIT

23

DATA 4

22
21

DATA 3

20

S10

19

S11
S8

18
17

S9
S14

16
15

S15
S12

14
13

S13

4 TO 16

DECODER

11 S0

9S1

10 S2

8S3
7S4

6S5
5S6
4S7

18 S8
17 S9
20 S10
19 S11
14 S12
13 S13
16 S14
15 S15

The decode truth table indicates all combinations of data
inputs and appropriate selected outputs.

These devices are similar to industry types MC14514 and
MC14515.

The CD4514BMS and CD4515BMS are supplied in these 24
lead outline packages:

Braze Seal DIP H4V
Frit Seal DIP H1Z
Ceramic Flatpack H4P

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

7-1188

File Number 3195

Specifications CD4514BMS, CD4515BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65

o

C to +125oC

o

C to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA

VDD = 18V, VIN = VDD or GND 3 -55

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

(Note 2)
Input Voltage High

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

(Note 2)
Input Voltage Low

(Note 2)
Input Voltage High

(Note 2)

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs.

Thermal Resistance . . . . . . . . . . . . . . . . θ

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70

ja

o

C/W 20oC/W

Maximum Package Power Dissipation (PD) at +125oC

= -55oC to +100oC (Package Type D, F, K) . . . . . .500mW

For T

A

For T

= +100oC to +125oC (Package Type D, F, K). . . . . .Derate

A

o

C

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

Linearity at 12mW/oC to 200mW

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

GROUP A

LIMITS

SUBGROUPS TEMPERATURE

2 +125oC - 1000 µA

o

C-10µA

o

C -100 - nA

2 +125oC -1000 - nA

2 +125oC - 1000 nA

VOL <

VDD/2

VDD/2

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.

θ

jc

UNITSMIN MAX

V

7-1189

Specifications CD4514BMS, CD4515BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A

PARAMETER SYMBOL CONDITIONS (NOTE 1, 2)

Propagation Delay
Strobe or Data

Propagation Delay
Inhibit

Transition Time TTHL

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

Input Voltage Low VIL VDD = 10V , VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

TPHL1
TPLH1

TPHL2
TPLH2

TTLH

VDD = 5V, VIN = VDD or GND 9 +25oC - 970 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 500 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

SUBGROUPS TEMPERATURE

10, 11 +125oC, -55oC - 1310 ns

10, 11 +125oC, -55oC - 675 ns

10, 11 +125oC, -55oC - 270 ns

+125oC - 150 µA

+125oC - 300 µA

+125oC - 600 µA

-55oC

-55oC

-55oC

-55oC

-55oC 0.64 - mA

-55oC 1.6 - mA

-55oC 4.2 - mA

-55oC - -0.64 mA

-55oC - -2.0 mA

-55oC - -1.6 mA

-55oC - -4.2 mA

-55oC

-55oC

LIMITS

UNITSMIN MAX

LIMITS

UNITSMIN MAX

-50mV

-50mV

4.95 - V

9.95 - V

-3V

+7 - V

7-1190

Specifications CD4514BMS, CD4515BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Propagation Delay
Strobe or Datat

Propagation Delay
Inhibit

Transition Time TTHL

Minimum Data Setup
Time

TPHL1
TPLH1

TPHL2
TPLH2

VDD = 10V 1, 2, 3 +25oC - 370 ns
VDD = 15V 1, 2, 3 +25oC - 270 ns
VDD = 10V 1, 2, 3 +25oC - 220 ns
VDD = 15V 1, 2, 3 +25
VDD = 10V 1, 2, 3 +25

TTLH

VDD = 15V 1, 2, 3 +25oC - 80 ns

TS VDD = 5V 1, 2, 3 +25

VDD = 10V 1, 2, 3 +25

o

C - 170 ns

o

C - 100 ns

o

C - 150 ns

o

C - 70 ns

VDD = 15V 1, 2, 3 +25oC - 40 ns

Minimum Strobe Pulse
Width

TW VDD = 5V 1, 2, 3 +25oC - 250 ns

VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 75 ns

Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

UNITSMIN MAX

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

UNITSMIN MAX

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage

∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V

Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage

∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

VDD/2

Propagation Delay Time TPHL

VDD = 3V, VIN = VDD or GND
VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

TPLH

VOL <

VDD/2

ns

+25oC

Limit

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

3. See Table 2 for +25oC limit.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

V

7-1191

Specifications CD4514BMS, CD4515BMS

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883

CONFORMANCE GROUP

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

CONFORMANCE GROUPS

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

METHOD GROUP A SUBGROUPS READ AND RECORD

TABLE 7. TOTAL DOSE IRRADIATION

MIL-STD-883

METHOD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

TEST READ AND RECORD

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR

FUNCTION OPEN GROUND VDD 9V ± -0.5V

Static Burn-In 1
(Note 1)

Static Burn-In 2
(Note 1)

Dynamic Burn­In (Note 1)

Irradiation
(Note 2)

NOTES:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V

4-11, 13-20 1-3, 12, 21-23 24

4-11, 13-20 12 1-3, 21-24

- 2, 3, 12 21, 22, 24 4-11, 13-20 1 23

50kHz 25kHz

7-1192

Logic Diagram

VDD

VSS

DATA 1 2

DATA 2 3

DATA 3 21

DATA 4 22

STROBE 1

INHIBIT 23

*

*

*

*

*

*

CD4514BMS, CD4515BMS

A

S

Q

R

Q

B

S

Q

R

Q

C

S

Q

R

Q

D

S

Q

R

Q

A B C D

A

B C D

ABC D

ABC D

A BCD

ABCD

ABCD

ABCD

A B CD

A B CD

ABCD

ABCD

A BCD

A BCD

ABCD

ABCD

S0

11

S1

9

10

S2

8

S3

7

S4

6

S5

S6

5

4

S7

S8

18

S9

17

S10

20

19

S11

14

S12

S13

13

16

S14

15 S15

* All inputs protected by CMOS protection network.

DECODER INPUTS SELECTED OUTPUT

INHIBIT

0 0000 S0
0 0001 S1
0 0010 S2
0 0011 S3
0 0100 S4
0 0101 S5
0 0110 S6
0 0111 S7
0 1000 S8
0 1001 S9
0 1010 S10
0 1011 S11
0 1100 S12
0 1101 S13
0 1110 S14
0 1111 S15
1 XXXXAll Outputs = 0, CD4514BMS

1 = HIGH LEVEL 0 = LOW LEVEL X = DON’T CARE

THESE INVENTERS USED ONLY ON CD4515BMS

FIGURE 1. LOGIC DIAGRAM

TRUTH TABLE

CD4514BMS = LOGIC 1 (HIGH)

CD4515BMS = LOGIC 0 (LOW)DCBA

All Outputs = 1, CD4515BMS

7-1193

CD4514BMS, CD4515BMS

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC

30

25

20

15

10

5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

AMBIENT TEMPERATURE (TA) = +25oC

15.0

12.5

10.0

7.5

5.0

2.5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

0-5-10-15

0

-5

-10

-15

-20

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

0-5-10-15

0

-5

-10

-25

-15V

-30

FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

550

SUPPLY VOLTAGE (VDD) = 5V

500
450

400
350
300

250

STROBE OR DATA

200
150
100

PROPAGATION DELAY TIME (tPHL, tPLH) - ns

50

10V

15V

0 40 60 80 10020

LOAD CAPACITANCE (CL) (pF)

FIGURE 6. TYPICAL STROBE OR DATA PROPAGATION

DELAY TIME vs LOAD CAPACITANCE

-15V

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

350

300

SUPPLY VOLTAGE (VDD) = 5V

250

200

150

100

50

INHIBIT PROPAGATION DELAY TIME (tPHL, tPLH) - ns

10V

15V

0 40 60 80 10020

LOAD CAPACITANCE (CL) (pF)

FIGURE 7. TYPICAL INHIBIT PROPAGATION DELAY TIME vs

LOAD CAPACITANCE

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

7-1194

CD4514BMS, CD4515BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE (TA) = +25oC

200

SUPPLY VOLTAGE (VDD) = 5V

150

100

50

TRANSITION TIME (fTHL, fTLH) (ns)

0

0 40 60 80 10020

SUPPLY VOLTAGE (VDD) = 5V

10V
15V

LOAD CAPACITANCE (CL) (pF)

FIGURE 8. TYPICAL LOW-TO-HIGH TRANSITION TIME vs

LOAD CAPACITANCE

6

10

AMBIENT TEMPERATURE (TA) = +25oC

5

10

4

10

10

5V

3

SUPPLY VOLTAGE

10V

AMBIENT TEMPERATURE (TA) = +25oC

500

400

300

STROBE OR DATA

200

100

PROPAGATION DELAY TIME (tPLH, tPHL) - ns)

LOAD CAPACITANCE (CL) = 50pF

0

0101520255

LOAD CAPACITANCE (CL) (pF)

FIGURE 9. TYPICAL STROBE OR DATA PROPAGATION

DELAY TIME vs SUPPLY VOLTAGE

(VDD) = 15V
10V

2

10

POWER DISSIPATION (PD) - µW

10

864286422

1

110

10

FREQUENCY (f) (kHz)

10. TYPICAL POWER DISSIPATION vs FREQUENCY

Waveforms

DATA

STROBE

FIGURE 11. WAVEFORMS FOR SETUP TIME AND STROBE

PULSE WIDTH

tW

50%

tS

tr, tf = 20ns

50%

2

CL = 50pF
CL = 15pF

864

2864

3

10

4

10

7-1195

CD4514BMS, CD4515BMS

Chip Dimensions and Pad Layouts

-3

inch.)

90 100 110

01020304050607080
74
70

60

50

40

30

20

10

0

4-10

(0.102-0.254)

Dimensions in parentheses are in milimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10

109-117

(2.769-2.971)

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

112

71-79

(1.804-2.006)

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
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