Datasheet CD4503BMS Datasheet (Intersil Corporation)

CD4503BMS

December 1992 File Number 3335

CMOS Hex Buffer

CD4503BMS is a hex noninverting buffer with 3 state
outputs having high sink and source current capability. Two
disable controls are provided, one of which controls four
buffers and the other controls the remaining two buffers.

The CD4503BMS is supplied in these 16-lead outline packages:
Braze Seal DIP H4T

Frit Seal DIP H1E
Ceramic Flatpack H6W

Features

• High Voltage Type (20V Rating)

• 3 State Non-Inverting Type

• 1 TTL Load Output Drive Capability

• 2 Output Disable Controls

• 3 State Outputs

• Pin Compatible with Industry Types MM80C97,
MC14503, and 340097

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µA at 18V Over Full Pack­age Temperature Range; 100nA at 18V and +25

o

C

• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”

Applications

• 3 State Hex Buffer for Interfacing ICs with Data Buses

• COS/MOS to TTL Hex Buffer

Pinout

DIS A

D1
Q1
D2
Q2
D3
Q3

VSS

CD4503BMS

TOP VIEW

1
2
3
4
5
6
7
8

Functional Diagram

D1

D2

D3

D4

D5

D6

1

2

4

6

10

12

14

15

3

Q1

5

Q2

7

Q3

9

Q4

11

Q5

13

Q6

DISABLE A

16

VDD

15

DIS B

14

D6

13

DQ6

12

D5

11

Q5

10

D4

9

Q4

DISABLE B

VDD = 16
VSS = 8

4-1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

CD4503BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD). . . . . . . . . . . . . . . .-0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25

VDD = 18V, VIN = VDD or GND 3 -55

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25

VDD = 18V 3 -55

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25

VDD = 18V 3 -55
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25

VDD = 20V, VIN = VDD or GND 7 +25
VDD = 18V, VIN = VDD or GND 8A +125
VDD = 3V, VIN = VDD or GND 8B -55

Input Voltage Low

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25

(Note 2)
Input Voltage High

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25

(Note 2)
Input Voltage Low

(Note 2)
Input Voltage High

(Note 2)
Tri-State Output

Leakage

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

IOZL VIN = VDD or GND

VOUT = 0V

VDD = 20V 1 +25

VDD = 18V 3 -55
Tri-State Output

Leakage

IOZH VIN = VDD or GND

VOUT = VDD

VDD = 20V 1 +25

VDD = 18V 3 -55
NOTES: 1. All voltages referenced to device GND, 100% testing being im-

plemented.

2. Go/No Go test with limits applied to inputs.

Thermal Resistance. . . . . . . . . . . . . . . . θ

Ceramic DIP and FRIT Package . . . . 80oC/W 20oC/W

Flatpack Package. . . . . . . . . . . . . . . . 70oC/W 20oC/W

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55oC to +100oC (Package Type D, F, K) . . . . . .500mW

For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate

Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC

GROUP A

SUBGROUPS TEMPERATURE

2 +125

2 +125

2 +125

o

C, +125oC, -55oC - 50 mV

o

C, +125oC, -55oC 14.95 - V

o

C, +125oC, -55oC - 1.5 V

o

C, +125oC, -55oC 3.5 - V

o

1, 2, 3 +25

1, 2, 3 +25

C, +125oC, -55oC- 4 V

o

C, +125oC, -55oC11 - V

2 +125

2 +125

3. Foraccuracy, voltage is measured differentially to VDD. Limit is

0.050V max.

ja

θ

Linearity at 12mW/oC to 200mW

LIMITS

UNITSMIN MAX

o

C-2µA

o

C - 200 µA

o

C-2µA

o

C -100 - nA

o

C -1000 - nA

o

C -100 - nA

o

C - 100 nA

o

C - 1000 nA

o

C - 100 nA

o

C 2.1 - mA

o

C 5.5 - mA

o

C 16.1 - mA

o

C - -1.02 mA

o

C - -4.8 mA

o

C - -2.6 mA

o

C - -6.8 mA

o

C -2.8 -0.7 V

o

C 0.7 2.8 V

o

C VOH >

o

C

o

C

o

C

o

C -0.4 - µA

o

C -12 - µA

o

C -0.4 - µA

o

C - 0.4 µA

o

C-12µA

o

C - 0.4 µA

VDD/2

VOL <
VDD/2

jc

V

4-2

CD4503BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A

PARAMETER SYMBOL CONDITIONS

Propagation Delay TPHL VDD = 5V, VIN = VDD or GND

(Note 1, 2)

Propagation Delay TPLH VDD = 5V, VIN = VDD or GND

(Note 1, 2)

Propagation Delay3 State TPHZ

TPZH

Propagation Delay3 State TPZL

TPLZ

Transition Time TTHL VDD = 5V, VIN = VDD or GND

Transition Time TTLH VDD = 5V, VIN = VDD or GND

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

3. CL = 50pF, RL = 1K, Input TR, TF < 20ns.

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 1 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 1.3 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 3.8 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 11.2 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.7 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -3.0 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -1.8 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -4.8 mA

VDD = 5V, VIN = VDD or GND
(Note 2, 3)

VDD = 5V, VIN = VDD or GND
(Note 2, 3)

(Note 1, 2)

(Note 1, 2)

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA

SUBGROUPS TEMPERATURE

9 +25oC - 110 ns

10, 11 +125oC, -55oC - 149 ns

9 +25oC - 150 ns

10, 11 +125oC, -55oC - 203 ns

9 +25oC - 140 ns

10, 11 +125oC, -55oC - 189 ns

9 +25oC - 180 ns

10, 11 +125oC, -55oC - 243 ns

9 +25oC - 70 ns

10, 11 +125oC, -55oC - 95 ns

9 +25oC - 90 ns

10, 11 +125oC, -55oC - 122 ns

+125oC-30µA

+125oC-60µA

+125oC - 120 µA

55oC

55oC

55oC

55oC

-55oC 2.6 - mA

-55oC 6.5 - mA

-55oC 19.2 - mA

-55oC - -1.2 mA

-55oC - -5.8 mA

-55oC - -3.1 mA

-55oC - -8.2 mA

LIMITS

UNITSMIN MAX

LIMITS

UNITSMIN MAX

-50mV

-50mV

4.95 - V

9.95 - V

4-3

CD4503BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -

55oC

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -

55oC

Propagation Delay TPHL VDD = 10V 1, 2, 3 +25oC - 50 ns

VDD = 15V 1, 2, 3 +25oC - 35 ns

Propagation Delay TPLH VDD = 10V 1, 2, 3 +25oC - 70 ns

VDD = 15V 1, 2, 3 +25oC - 50 ns

Propagation Delay TPHZ

TPZH

Propagation Delay TPZL

TPLZ

Transition Time TTHL VDD = 10V 1, 2, 3 +25oC - 40 ns

Transition Time TTLH VDD = 10V 1, 2, 3 +25oC - 45 ns

Input Capacitance CIN Any Inputs 1, 2 +25oC - 7.5 pF

NOTES:

1. All voltages referenced to device GND.

2. Theparameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.

VDD = 10V 1, 2, 4 +25oC - 60 ns
VDD = 15V 1, 2, 4 +25oC - 50 ns
VDD = 10V 1, 2, 4 +25oC - 80 ns
VDD = 15V 1, 2, 4 +25oC - 70 ns

VDD = 15V 1, 2, 3 +25oC - 25 ns

VDD = 15V 1, 2, 3 +25oC - 35 ns

-3V

+7 - V

UNITSMIN MAX

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 7.5 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage

Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage

Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

Propagation Delay Time TPHL

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V

∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

VOL <
VDD = 3V, VIN = VDD or GND
VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

TPLH

3. See Table 2 for +25oC limit.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-1 IDD ± 0.2µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

VDD/2

VDD/2

+25oC

Limit

UNITSMIN MAX

ns

V

4-4

CD4503BMS

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883

CONFORMANCE GROUP

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

CONFORMANCE GROUPS

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

METHOD GROUP A SUBGROUPS READ AND RECORD

TABLE 7. TOTAL DOSE IRRADIATION

MIL-STD-883

METHOD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

TEST READ AND RECORD

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR

FUNCTION OPEN GROUND VDD 9V ± -0.5V

Static Burn-In 1
(Note 1)

Static Burn-In 2
(Note 1)

Dynamic Burn­In (Note 1)

Irradiation
(Note 2)

NOTES:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

3, 5, 7, 9, 11, 13 1, 2, 4, 6, 8,10, 12,

14, 15

3, 5, 7, 9, 11, 13 8 1, 2, 4, 6, 10, 12,

- 1, 8, 15 16 3, 5, 7, 9, 11, 13 2, 4, 6, 10, 12, 14

3, 5, 7, 9, 11, 13 8 1, 2, 4, 6, 10, 12,

16

14-16

14-16

50kHz 25kHz

4-5

Logic Diagram

*

DI

2 (4, 6, 10, 12, 14)

DIS A (B)

*

1 (15)

DISABLE TO OTHER

BUFFERS

ALL INPUTS ARE PROTECTED

*

BY CMOS PROTECTION
NETWORK

FIGURE 1. LOGIC DIAGRAM OF 1 TO 6 IDENTICAL BUFFERS

Typical Performance Characteristics

CD4503BMS

VDD

QN

3 (5, 7, 9, 11, 13)

VSS

VDD

VSS

TRUTH TABLE

DN DIS A (B) Qn

000
101

X 1 High Z

X = Don’t Care

AMBIENT TEMPERATURE (TA) = +25oC

70

60

50

40

30

20

10

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

0

12345678910

DRAIN-TO-SOURCE VOLTA GE (VDS) (V)

FIGURE 2. TYPICAL N-CHANNEL OUTPUT LOW (SINK)

CURRENT CHARACTERISTICS

DRAIN-TO-SOURCE VOLTA GE (VDS) (V)

0-2-4-6

-1-3-5-7-8-9

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10

-20

-30

AMBIENT TEMPERATURE (TA) = +25oC

70

60

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

50

40

30

20

10

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0

12345678910

DRAIN-TO-SOURCE VOLTA GE (VDS) (V)

5V

10V

FIGURE 3. MINIMUM N-CHANNEL OUTPUT LOW (SINK)

CURRENT CHARACTERISTICS

DRAIN-TO-SOURCE VOLTA GE (VDS) (V)

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

0-2-4-6 -1-3-5-7-8-9

-5

-10

-15

-10V

-15V

AMBIENT TEMPERATURE (TA) = +25oC

-40

-50

-60

-70

FIGURE 4. TYPICALP-CHANNEL OUTPUT HIGH (SOURCE)

CURRENT CHARACTERISTICS

4-6

-15V

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

AMBIENT TEMPERATURE (TA) = +25oC

FIGURE 5. MINIMUMP-CHANNEL OUTPUT HIGH (SOURCE)

CURRENT CHARACTERISTICS

-20

-25

-30

-35

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

CD4503BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE (TA) = +25oC

175

150

125

100

75

50

25

PROPAGATION DELAY TIME (tPLH, tPHL) (ns)

tPLH
tPHL

VDD = 5V

VDD = 10V

VDD = 15V

0102030405060708090100

LOAD CAPACITANCE (CL) (pF)

FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

8
6

4
2

10K

8
6

4

VDD = 15V

2

1K

8
6

4
2

100

8
6

POWER DISSIPATION (PD) (µW)

4
2

10

11010

AMBIENT TEMPERATURE (TA) = +25oC

70

60

50

40

5V (tTLH)
5V (tTHL)

30

10V (tTLH)

20

15V (tTLH)
10V (tTHL)

10

TRANSITION TIME (tTHL, tTLH) (ns)

15V (tTHL)

10 30 50 70 90

020

FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACITANCE

VDD = 5V

VDD = 10V

CL = 50pF
CL = 15pF

tr = tf = 20ns

AMBIENT TEMPERATURE (TA) = +25oC

864286422

FREQUENCY (f) (kHz)

2

2864

864

3

10

40 60 80 100

LOAD CAPACITANCE (CL) (pF)

4

10

FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY

Chip Dimensions and Pad Layout

4-7

Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10

-3

inch).

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

CD4503BMS

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly , the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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4-8

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