Datasheet CD4502BMS Datasheet (Intersil Corporation)

CD4502BMS

December 1992

Features

• High Voltage Type (20V Rating)

• 2 TTL Load Output Drive Capability

• 3 State Outputs

• Common Output Disable Control

• Inhibit Control

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”

Applications

CMOS Strobed Hex Inverter/Buffer

Pinout

CD4502BMS

TOP VIEW

16
15
14
13
12
11
10

9

VDD
D6
Q6
D5
INHIBIT
Q5
D4
Q4

1

D3
Q3

2

D1

3

OUTPUT DISABLE

o

C

3 STATE

Q1
D2
Q2

VSS

4
5
6
7
8

Functional Diagram

• 3 State Hex Inverter for Interfacing ICs with Data
Buses

• COS/MOS to TTL Hex Buffer

Description

CD4502BMS consists of six inverter/buffers with 3 state
outputs. A logic “1” on the OUTPUT DISABLE input
produces a high impedance state in all six outputs. This
feature permits common busing of the outputs, thus
simplifying system design. A Logic “1” on the INHIBIT input
switches all six outputs to logic “0” if the OUTPUT DISABLE
input is a logic “0”. This device is capable of driving two
standard TTL loads, which is equivalent to six times the
JEDEC “B” series IOL standard.

The CD4502BMS is supplied in these 16-lead outline packages:
Braze Seal DIP H4T

Frit Seal DIP H1F
Ceramic Flatpack H6W

OUTPUT DISABLE

3 STATE

INHIBIT

D1

D2

D3

D4

D5

D6

VDD = 16
VSS = 8

4

12
3

6

1

10

13

15

5

Q1

7

Q2

2

Q3

9

Q4

11

Q5

14

Q6

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

7-473

File Number

3334

Specifications CD4502BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55

Package Types D, F, K, H

Storage Temperature Range (TSTG) . . . . . . . . . . . -65

o

C to +125oC

o

C to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-2µA

VDD = 18V, VIN = VDD or GND 3 -55

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 3.06 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 7.8 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 20.4 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low

VIL5 VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

(Note 2)
Input Voltage High

VIH5 VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

(Note 2)
Input Voltage Low

(Note 2)
Input Voltage High

(Note 2)
Tri-State Output

Leakage

VIL15 VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH15 VDD = 15V, VOH > 13.5V,

VOL < 1.5V

IOZL VIN = VDD or GND

VDD = 20V 1 +25oC -0.4 - µA

VOUT = 0V

VDD = 18V 3 -55oC -0.4 - µA
Tri-State Output

Leakage

IOZH VIN = VDD or GND

VOUT = VDD

VDD = 20V 1 +25oC - 0.4 µA

VDD = 18V 3 -55oC - 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs.

Thermal Resistance . . . . . . . . . . . . . . . . θ

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55
For TA = +100

o

C

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

o

C to +100oC (Package Type D, F, K). . . . . . 500mW

o

C to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

ja

o

C/W 20oC/W

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

GROUP A

LIMITS

SUBGROUPS TEMPERATURE

2 +125oC - 200 µA

o

C-2µA

o

C -100 - nA

2 +125oC -1000 - nA

2 +125oC - 1000 nA

VOL <

VDD/2

VDD/2

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

2 +125oC -12 - µA

2 +125oC-12µA

3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.

θ

jc

UNITSMIN MAX

V

7-474

Specifications CD4502BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A

PARAMETER SYMBOL CONDITIONS

Propagation Delay
Data or Inhibit to Output

Propagation Delay
Data or Inhibit to Output

Propagation Delay
Inhibit to Output

Propagation Delay
Inhibit to Output

Propagation Delay
Disable to Output

Propagation Delay
Disable to Output

Propagation Delay
Disable to Output

Propagation Delay
Disable to Output

Transition Time TTHL VDD = 5V, VIN = VDD or GND

Transition Time TTLH VDD = 5V, VIN = VDD or GND

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

3. VDD = 5V, CL = 50pF, RL = 1K, Input TR, TF < 20ns.

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 1 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 2.16 - mA

TPHL1 VDD = 5V, VIN = VDD or GND

(Note 1, 2)

TPLH1 VDD = 5V, VIN = VDD or GND

(Note 1, 2)

TPHL2 VDD = 5V, VIN = VDD or GND

(Note 1, 2)

TPLH2 VDD = 5V, VIN = VDD or GND

(Note 1, 2)

TPHZ VDD = 5V, VIN = VDD or GND

(Note 2, 3)

TPZH VDD = 5V, VIN = VDD or GND

(Note 2, 3)

TPLZ VDD = 5V, VIN = VDD or GND

(Note 2, 3)

TPZL VDD = 5V, VIN = VDD or GND

(Note 2, 3)

(Note 1, 2)

(Note 1, 2)

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA

SUBGROUPS TEMPERATURE

9 +25oC - 270 ns

10, 11 +125oC, -55oC - 365 ns

9 +25oC - 380 ns

10, 11 +125oC, -55oC - 513 ns

9 +25oC - 270 ns

10, 11 +125oC, -55oC - 365 ns

9 +25oC - 380 ns

10, 11 +125oC, -55oC - 513 ns

9 +25oC - 120 ns

10, 11 +125oC, -55oC - 162 ns

9 +25oC - 220 ns

10, 11 +125oC, -55oC - 297 ns

9 +25oC - 250 ns

10, 11 +125oC, -55oC - 338 ns

9 +25oC - 250 ns

10, 11 +125oC, -55oC - 338 ns

9 +25oC - 120 ns

10, 11 +125oC, -55oC - 162 ns

9 +25oC - 200 ns

10, 11 +125oC, -55oC - 270 ns

+125oC-30µA

+125oC-60µA

+125oC - 120 µA

-55oC

-55oC

-55oC

-55oC

-55oC 3.84 - mA

LIMITS

UNITSMIN MAX

LIMITS

UNITSMIN MAX

-50mV

-50mV

4.95 - V

9.95 - V

7-475

Specifications CD4502BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2, 4 +125oC 5.4 - mA

-55oC 9.6 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2, 4 +125oC 14.4 - mA

-55oC 25.2 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

-55oC - -0.64 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

-55oC - -2.0 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

-55oC - -1.6 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

-55oC - -4.2 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V,

VOL < 1V

Input Voltage High VIH VDD = 10V, VOH > 9V,

VOL < 1V

Propagation Delay
Data to Output

Propagation Delay
Data to Output

Propagation Delay
Inhibit to Output

Propagation Delay
Inhibit to Output

Propagation Delay
Disable to Output

Propagation Delay
Disable to Output

Propagation Delay
Disable to Output

Propagation Delay
Disable to Output

Transition Time TTHL VDD = 10V 1, 2, 3 +25oC - 60 ns

Transition Time TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns

Input Capacitance CIN Any Inputs 1, 2 +25oC - 7.5 pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.

TPHL1 VDD = 10V 1, 2, 3 +25oC - 120 ns

VDD = 15V 1, 2, 3 +25oC - 80 ns

TPLH1 VDD = 10V 1, 2, 3 +25oC - 180 ns

VDD = 15V 1, 2, 3 +25oC - 130 ns

TPHL2 VDD = 10V 1, 2, 3 +25oC - 120 ns

VDD = 15V 1, 2, 3 +25oC - 80 ns

TPLH2 VDD = 10V 1, 2, 3 +25oC - 180 ns

VDD = 15V 1, 2, 3 +25oC - 130 ns

TPHZ VDD = 10V 1, 2, 4 +25oC - 80 ns

VDD = 15V 1, 2, 4 +25oC - 60 ns

TPZH VDD = 10V 1, 2, 4 +25oC - 100 ns

VDD = 15V 1, 2, 4 +25oC - 80 ns

TPLZ VDD = 10V 1, 2, 4 +25oC - 130 ns

VDD = 15V 1, 2, 4 +25oC - 110 ns

TPZL VDD = 10V 1, 2, 4 +25oC - 110 ns

VDD = 15V 1, 2, 4 +25oC - 80 ns

VDD = 15V 1, 2, 3 +25oC - 40 ns

VDD = 15V 1, 2, 3 +25oC - 80 ns

1, 2 +25oC, +125oC,

-55oC

1, 2 +25oC, +125oC,

-55oC

-3V

+7 - V

UNITSMIN MAX

7-476

Specifications CD4502BMS

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 7.5 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage

Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage

Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

Propagation Delay Time TPHL

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V

∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

VOL <
VDD = 3V, VIN = VDD or GND
VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

TPLH

3. See Table 2 for +25oC limit.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-1 IDD ± 0.2µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

VDD/2

VDD/2

+25oC

Limit

UNITSMIN MAX

ns

V

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883

CONFORMANCE GROUP

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

CONFORMANCE GROUPS

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

METHOD GROUP A SUBGROUPS READ AND RECORD

TABLE 7. TOTAL DOSE IRRADIATION

MIL-STD-883

METHOD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

TEST READ AND RECORD

7-477

Specifications CD4502BMS

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR

FUNCTION OPEN GROUND VDD 9V ± -0.5V

Static Burn-In 1
Note 1

Static Burn-In 2
Note 1

Dynamic Burn-

2, 5, 7, 9, 11, 14 1, 3, 4, 6, 8, 10, 12,

16

13, 15

2, 5, 7, 9, 11, 14 8 1, 3, 4, 6, 10, 12,

13, 15, 16

- 8 16 2, 5, 7, 9, 11, 14 4 1, 3, 6, 10, 12, 13,

In Note 1
Irradiation

Note 2

2, 5, 7, 9, 11, 14 8 1, 3, 4, 6, 10, 12,

13, 15, 16

50kHz 25kHz

15

NOTES:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

Logic Diagram

INVERTER/BUFFER NO. 1

*

DI

3-STATE

*

OUTPUT

DISABLE

*

INHIBIT

TO 5 OTHER

INVERTER/BUFFERS

ALL INPUTS ARE PROTECTED

*

BY CMOS PROTECTION
NETWORK

FIGURE 1. LOGIC DIAGRAM OF 1 OF 6 IDENTICAL INVERTER/BUFFERS

Test Circuit and Waveform

D3

1

Q3

2

D1

3

PULSE

GENERATOR

DISABLE

Q1
D2
Q2

VSS

4
5
6
7
8

TEST CONDITIONS

TEST PIN 15 POINT A

tPHZ VSS VSS

tPLZ VDD VDD
tPZL VDD VDD

tPZH VSS VSS

16
15
14
13
12
11
10

9

VDD
D6
Q6
D5
INHIBIT
Q5
D4
Q4

VSS

VDD

VDD

VSS

VDD

Q1

0.01kµF

1kΩ

CL

TRUTH TABLE

DISABLE INHIBIT Dn Qn

0001
0010
01X0
1XXZ

Logic 0 = Low
Logic 1 = High
Z = High Impedance
X = Don’t Care

A

50%

tPLZ

10%

90%

tPHZ

50%

90%

10%

tPZL

tPZH

VDD

VOL

VOH

VSS

FIGURE 2. DISABLE DELAY TIMES TEST CIRCUIT AND WAVEFORMS

7-478

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC

30

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

25

20

15

10V

10

5

1/6 OUTPUT LOW (SINK) CURRENT (IOL) (mA)

5V

0 5 10 15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

AMBIENT TEMPERATURE (TA) = +25oC

15.0

12.5

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10.0

7.5

10V

5.0

2.5

1/6 OUTPUT LOW (SINK) CURRENT (IOL) (mA)

5V

0 5 10 15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

0-5-10-15

0

-5

-10

-15

-20

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

0-5-10-15

0

-5

-10

-25

-15V

-30

-15V

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

SUPPLY VOLTAGE (VDD) = 15V

15

10

5

OUTPUT VOLTAGE (VO) (V)

10V

5V

0 5 10 15 20 25

INPUT VOLTAGE (VI) (V)

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

5

10

8
6

SUPPLY VOLTAGE (VDD) = 15V

4

DISSIPATION PER INVERTER/BUFFER (PD) (µW)

2

4

10

8
6

4
2

3

10

8
6

4
2

2

10

8
6

4
2

10

0

10

INPUT FREQUENCY (fI) (kHz)

10V

10V

5V

CL = 50pF
CL = 15pF

AMBIENT TEMPERATURE (TA) = +25oC

864286422

1

10

2

10

864

3

10

2864

10

FIGURE 7. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION

OF INPUT FREQUENCY

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

4

7-479

CD4502BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE (TA) = +25oC

150

SUPPLY VOLTAGE (VDD) = 5V (tTLH)

100

5V (tTLH)
10V (tTLH)
15V (tTLH)

50

10V (tTHL)

TRANSITION TIME (tTHL, tTLH) (ns)

15V (tTLH)

020

LOAD CAPACITANCE (CL) (pF)

40 60 80 100

FIGURE 9. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACITANCE

Chip Dimensions and Pad Layout

AMBIENT TEMPERATURE (TA) = +25oC

250

SUPPLY VOLTAGE (VDD) = 5V (tPLH)

200

5V (tPHL)

150

10V (tPLH)

100

15V (tPLH)

10V (tPHL)

50

15V (tPHL)

PROPAGATION DELAY TIME (tPLH, tPHL) (ns)

020

LOAD CAPACITANCE (CL) (pF)

40 60 80 100

FIGURE 10. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10

-3

inch).

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

480