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October 1987
Revised January 1999
CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS005983.prf www.fairchildsemi.com
CD4094BC
8-Bit Shift Register/Latch with 3-STAT E Outputs
General Description
The CD4094BC consists of an 8-bit sh ift register and a 3STATE 8-bit latch. Data is shifted serial ly through the shift
register on the positive transition of the clock. The output of
the last stage (Q
S
) can be used to cascade several
devices. Data on the Q
S
output is transferred to a second
output, Q′
S
, on the following negative clock edge.
The output of each stage of the shift registe r feeds a latch,
which latches data on the negative edge of the STROBE
input. When STROBE is HI GH, data propagates through
the latch to 3-STATE output gates. These gates are
enabled when OUTPUT ENABLE is taken HIGH.
Features
■ Wide supply voltage range: 3.0V to 18V
■ High noise immunity: 0.45 V
DD
(typ.)
■ Low power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
■ 3-STATE outputs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Truth Table
X = Don't Care
= HIGH-to-LOW
= LOW-to-HIGH
Note 1: At the positive clock ed ge, infor m ation in the 7th shift regis t er stage is transferred to Q8 an d Q
S
.
Order Number Package Number Package Description
CD4094BCWM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
CD4094BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Clock Output Strobe Data Parallel Outputs Serial Outputs
Enable
Q1 Q
N
Q
S
(Note 1)
Q′
Σ
0 X X Hi-Z Hi-Z Q7 No Change
0 X X Hi-Z Hi-Z No Change Q7
1 0 X No Change No Change Q7 No Change
1100Q
N
−1 Q7 No Change
1111Q
N
−1 Q7 No Change
1 1 1 No Change No Change No Change Q7
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CD4094BC
Block Diagram
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CD4094BC
Absolute Maximum Ratings(Note 2)
(Note 3)
Recommended Operating
Conditions
(Note 3)
Note 2: “Absolute Maximum Rat ings” are tho se values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be o perated at these limits. The tables of “R ecommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operat ion.
Note 3: V
SS
= 0V unless otherw is e s pecified.
DC Electrical Characteristics (Note 3)
Note 4: IOH and IOL are tested one output at a ti m e.
Supply Voltage (VDD) −0.5 to +18 V
DC
Input Voltage (VIN) −0.5 to VDD +0.5 V
DC
Storage Temperature Range (TS) −65°C to +150°C
Power Dissipation (P
D
)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (T
L
)
(Soldering , 10 seconds) 260°C
DC Supply Voltage (V
DD
) +3.0 to +15 V
DC
Input Voltage (VIN) 0 to VDD V
DC
Operating Temperature Range (TA) −40°C to +85°C
Symbol Parameter Conditions
−40°C +25°C +85°C
Units
Min Max Min Typ Max Min Max
I
DD
Quiescent VDD = 5.0V 20 20 150 µA
Device Current VDD = 10V 40 40 300 µA
VDD = 15V 80 80 600 µA
V
OL
LOW Level VDD = 5.0V 0.05 0 0.05 0.05 V
Output Voltage VDD = 10V |IO| ≤ 1.0 µA 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V
V
OH
HIGH Level VDD = 5.0V 4.95 4.95 5.0 4.95 V
Output Voltage VDD = 10V |IO| ≤ 1 µA9.959.9510.09.95 V
VDD = 15V 14.95 14.95 15.0 14.95 V
V
IL
LOW Level VDD = 5.0V, VO = 0.5V or 4.5V 1.5 1.5 1.5 V
Input Voltage VDD = 10V, VO = 1.0V or 9.0V 3.0 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 V
V
IH
HIGH Level VDD = 5.0V, VO = 0.5V or 4.5V 3.5 3.5 3.5 V
Input Voltage VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 V
I
OL
LOW Level VDD = 5.0V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
Output Current VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA
(Note 4) VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
I
OH
HIGH Level VDD = 5.0V, VO = 4.6V −0.52 −0.44 0.88 −0.36 mA
Output Current VDD = 10V, VO = 9.5V −1.3 −1.1 2.25 −0.9 mA
(Note 4) VDD = 15V, VO = 13.5V −3.6 −3.0 8.8 −2.4 mA
I
IN
Input Current VDD = 15V, VIN = 0V −0.3 −0.3 −1.0 µA
VDD = 15V, VIN = 15V 0.3 0.3 1.0 µA
I
OZ
3-STATE Output VDD = 15V, VIN = 0V or 15V 1 1 10 µA
Leakage Current
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CD4094BC
AC Electrical Charac teristics (Note 5)
TA = 25°C, CL = 50 pF
Note 5: AC Parameters are guara nt eed by DC correlated testing.
Symbol Parameter Conditions Min Typ Max Units
t
PHL
, t
PLH
Propagation Delay VDD = 5.0V 300 600 ns
Clock to Q
S
VDD = 10V 125 250 ns
VDD = 15V 95 190 ns
t
PHL
, t
PLH
Propagation Delay VDD = 5.0V 230 460 ns
Clock to Q′
Σ
VDD = 10V 110 220 ns
VDD = 15V 75 150 ns
t
PHL
, t
PLH
Propagation Delay Clock VDD = 5.0V 420 840 ns
to Parallel Out VDD = 10V 195 390 ns
VDD = 15V 135 270 ns
t
PHL
, t
PLH
Propagation Delay Strobe VDD = 5.0V 290 580 ns
to Parallel Out VDD = 10V 145 290 ns
VDD = 15V 100 200 ns
t
PHZ
Propagation Delay HIGH VDD = 5.0V 140 280 ns
Level to HIGH Impedance VDD = 10V 75 150 ns
VDD = 15V 55 110 ns
t
PLZ
Propagation Delay LOW VDD = 5.0V 140 280 ns
Level to HIGH Impedance VDD = 10V 75 150 ns
VDD = 15V 55 110 ns
t
PZH
Propagation Delay HIGH VDD = 5.0V 140 280 ns
Impedance to HIGH Level VDD = 10V 75 150 ns
VDD = 15V 55 110 ns
t
PZL
Propagation Delay HIGH VDD = 5.0V 140 280 ns
Impedance to LOW Level VDD = 10V 75 150 ns
VDD = 15V 55 110 ns
t
THL
, t
TLH
Transition Time VDD = 5.0V 100 200 ns
VDD = 10V 50 100 ns
VDD = 15V 40 80 ns
t
SU
Set-Up Time VDD = 5.0V 80 40 ns
Data to Clock VDD = 10V 40 20 ns
VDD = 15V 20 10 ns
tr, t
f
Maximum Clock Rise VDD = 5.0V 1 ms
and Fall Time VDD = 10V 1 ms
VDD = 15V 1 ms
t
PC
Minimum Clo ck VDD = 5.0V 200 100 ns
Pulse Width VDD = 10V 100 50 ns
VDD = 15V 83 40 ns
t
PS
Minimum Strobe VDD = 5.0V 200 100 ns
Pulse Width VDD = 10V 80 40 ns
VDD = 15V 70 35 ns
f
max
Maximum Clock Frequency VDD = 5.0V 1.5 3.0 MHz
VDD = 10V 3.0 6.0 MHz
VDD = 15V 4.0 8.0 MHz
C
IN
Input Capacitance Any Input 5.0 7.5 pF
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CD4094BC
Timing Diagram
Test Circuits and Timing Diagrams for 3-STATE
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CD4094BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M16B
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t d evices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injur y to the
user.
2. A critical comp onent in any com ponent of a l ife support
device or system whose failure to p erform can be r easonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
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