Datasheet CD4063BMS Datasheet (Intersil Corporation)

CD4063BMS

December 1992

Features

• High Voltage Type (20V Rating)

• Expansion to 8, 12, 16 . . . 4N Bits by Cascading Units

• Medium Speed Operation

- Compares Two 4-Bit Words in 250ns (Typ.) at 10V

• 100% Tested for Quiescent Current at 20V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25

• Noise Margin (Full Package Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”

Applications

• Servo Motor Controls

• Process Controllers

Description

CD4063BMS is a 4-bit magnitude comparator designed for use
in computer and logic applications that require the comparison of
two 4-bit words. This logic circuit determines whether one 4-bit
word (Binary or BCD) is “less than”, “equal to”, or “greater than” a
second 4-bit word.

CMOS 4-Bit Magnitude Comparator

Pinout

CD4063BMS

TOP VIEW

VDD

1

B3

VSS

2
3
4
5
6
7
8

(A < B) IN
(A = B) IN
(A > B) IN

(A > B) OUT

o

C

(A = B) OUT
(A < B) OUT

Functional Diagram

4

A > B
A = B
A < B

4

CASCADING

INPUTS

WORD A

WORD B

16

A3

15

B2

14

A2

13

A1

12

B1

11

A0

10

B0

9

A > B
A = B
A < B

The CD4063BMS has eight comparing inputs (A3, B3, through
A0, B0), three outputs (A < B, A = B, A > B) and three cascading
inputs (A < B, A = B, A > B) that permit systems designers to
expand the comparator function to 8, 12, 16 . . . 4N bits. When a
single CD4063BMS is used, the cascading inputs are connected
as follows: (A < B) = low, (A = B) = high, (A > B) = low.

For words longer than 4 bits, CD4063BMS devices may be cas­caded by connecting the outputs of the less significant compara­tor to the corresponding cascading inputs of the more significant
comparator. Cascading inputs (A < B, A = B, and A > B) on the
least significant comparator are connected to a low, a high, and a
low level, respectively.

The CD4063BMS is supplied in these 16 lead outline pack­ages:

Braze Seal DIP H4T
Frit Seal DIP H1E
Ceramic Flatpack H6W

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

7-958

File Number

3318

Specifications CD4063BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55

Package Types D, F, K, H

Storage Temperature Range (TSTG) . . . . . . . . . . . -65

o

C to +125oC

o

C to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25

VDD = 18V, VIN = VDD or GND 3 -55oC-10µA

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

(Note 2)
Input Voltage High

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

(Note 2)
Input Voltage Low

(Note 2)
Input Voltage High

(Note 2)

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

NOTES:

1. All voltages referenced to device GND. 100% testing being implemented

2. Go/No Go test with limit applied to inputs

Thermal Resistance . . . . . . . . . . . . . . . . θ

Ceramic DIP Package. . . . . . . . . . . . . 80oC/W 20C/W

Flatpack Package . . . . . . . . . . . . . . . . 20

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55
For TA = +100

o

C

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

o

C to +100oC (Package Type D, F, K). . . . . . 500mW

o

C to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

ja

o

C/W 20oC/W

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

GROUP A

LIMITS

SUBGROUPS TEMPERATURE

o

C-10µA

2 +125oC - 1000 µA

o

C -100 - nA

2 +125oC -1000 - nA

2 +125oC - 1000 nA

VOL <

VDD/2

VDD/2

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.

θ

jc

UNITSMIN MAX

V

7-959

Specifications CD4063BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

(NOTE 1, 2)

PARAMETER SYMBOL

Propagation Delay Com­parator Input to Output

Propagation Delay
Cascade Input to Output

Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

NOTES:

1. VDD = 5V, CL = 50pF, RL = 200K; input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL <

TPHL
TPLH

TPHL
TPLH

VDD = 5V, VIN = VDD or GND 9 +25oC - 1250 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 1000 ns

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA

1V

CONDITIONS

GROUP A

SUBGROUPS TEMPERATURE

10, 11 +125oC, -55oC - 1688 ns

10, 11 +125oC, -55oC - 1350 ns

10, 11 +125oC, -55oC - 270 ns

+125oC - 150 µA

+125oC - 300 µA

+125oC - 600 µA

-55oC

-55oC

-55oC

-55oC

-55oC 0.64 - mA

-55oC 1.6 - mA

-55oC 4.2 - mA

-55oC - -0.64 mA

-55oC - -2.0 mA

-55oC - -2.6 mA

-55oC - -4.2 mA

1, 2 +25oC, +125oC,

-55oC

LIMITS

UNITSMIN MAX

LIMITS

UNITSMIN MAX

-50mV

-50mV

4.95 - V

9.95 - V

-3V

7-960

Specifications CD4063BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Input Voltage High VIH VDD = 10V, VOH > 9V, VOL <

1V

Propagation Delay
Comparator Input to Output

Propagation Delay
Cascade Input to Output

Transition Time TTHL

TPHL1
TPLH1

TPHL2
TPLH2

TTLH

VDD = 10V 1, 2, 3 +25oC - 500 ns
VDD = 15V 1, 2, 3 +25oC - 350 ns
VDD = 10V 1, 2, 3 +25oC - 400 ns
VDD = 15V 1, 2, 3 +25oC - 280 ns
VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns

1, 2 +25oC, +125oC,

-55oC

+7 - V

Input Capacitance CIN 1, 2 +25oC - 7.5 pF

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K; input TR, TF < 20ns

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

o

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25
N Threshold Voltage

∆VNTH VDD = 10V, ISS= -10µA 1, 4 +25

C-25µA

o

C -2.8 -0.2 V

o

C-±1V

Delta

o

P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1, 4 +25
P Threshold Voltage

∆VPTH VSS = 0V, IDD = 10µA 1, 4 +25

C 0.2 2.8 V

o

C-±1V

Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25

VDD = 3V, VIN = VDD or GND

Propagation Delay Time TPHL

VDD = 5V (Worst Case) 1, 2, 3, 4 +25

TPLH

o

C VOH >

VDD/2

o

C - 1.35 x

VOL <
VDD/2

+25oC

Limit

NOTES:

1. All voltages referenced to device GND.

2. VDD = 5V, CL = 50pF, RL = 200K; input TR, TF = 20ns

o

3. See Table 2 for +25

C limit.

4. Read and record

UNITSMIN MAX

UNITSMIN MAX

V

ns

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

7-961

Specifications CD4063BMS

TABLE 6. APPLICABLE SUBGROUPS

CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD

Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 5% parametric, 3% functional; cumulative for static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

CONFORMANCE GROUPS METHOD

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9, Deltas Table 4

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR

FUNCTION OPEN GROUND VDD 9V ± -0.5V

Static Burn-In 1

5-7 1, 2, 4, 8-15 3, 16

50kHz 25kHz

Note 1
Static Burn-In 2

5-7 3, 8 1, 2, 4, 9-16

Note 1
Dynamic Burn-

In Note 1
Irradiation

- 1, 2, 4, 8, 10, 11,

3, 16 5-7 12, 15 9, 14

13

5-7 3, 8 1, 2, 4, 9-16

Note 2

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V

VDD

A0 A1 A2 A3

CD4063

(A < B) IN
(A = B) IN
(A > B) IN

(A < B) OUT
(A = B) OUT
(A > B) OUT

A4 A5 A6 A7

CD4063

A8 A9 A10 A11

CD4063

B0 B1 B2 B3

tP TOTAL = tP (COMPARE INPUTS) + 2 x tP (CASCADE INPUTS), AT VDD = 10V
(3 STAGES)

= 250 + (2 x 200) = 650ns (TYP.)

B4 B5 B6 B7

B8 B9 B10 B11

FIGURE 1. TYPICAL SPEED CHARACTERISTICS OF A 12-BIT COMPARATOR

7-962

Logic Diagram

COMPARING

INPUTS

(A < B) IN

CASCADING

INPUTS

ALL INPUTS PROTECTED

*

BY THE CMOS
PROTECTION NETWORK

(A > B) IN

(A = B) IN

A0

A1

A2

A3

B0

B1

B2

B3

10

12

13

15

9

11

14

1

2

4

3

*

*

*

*

*

*

*

*

*

*

*

TERMINAL

INPUT

A0
A0

A1
A1

A2
A2

A3
A3
B0
B0
B1
B1

B2
B2

B3
B3

(

A < B) i - I

(A > B) i - I

VDD

CD4063BMS

A3
B3

A3
B3

A2
B2

A2
B2

A1
B1

A1
B1

A0
B0

A0
B0

(

B3
A3

B3
A3

B2
A2

B2
A2

B1
A1

B1
A1

B0
A0

B0

VSS

A0
(

A < B) i - I

A > B) i - I

A < B

A > B

(A < B) OUT

7

(A = B) OUT

6

(A > B) OUT

5

FIGURE 2. LOGIC DIAGRAM

TRUTH TABLE

INPUTS

OUTPUTSCOMPARING CASCADING

A3, B3 A2, B2 A1, B1 A0, B0 A <B A = B A > B A < B A = B A > B

A3 > B3
A3 = B3
A3 = B3
A3 = B3

A3 = B3
A3 = B3
A3 = B3

A3 = B3
A3 = B3
A3 = B3
A3 < B3

X
A2 > B2
A2 = B2
A2 = B2

A2 = B2
A2 = B2
A2 = B2

A2 = B2
A2 = B2
A2 < B2

X

X

X
A1 > B1
A1 = B1

A1 = B1
A1 = B1
A1 = B1

A1 = B1
A1 < B1

X

X

X
X
X

A0 > B0
A0 = B0

A0 = B0
A0 = B0

A0 < B0

X
X
X

X
X
X
X

0
0
1

X
X
X
X

X
X
X
X

0
1
0

X
X
X
X

X
X
X
X

1
0
0

X
X
X
X

0
0
0
0

0
0
1

1
1
1
1

0
0
0
0

0
1
0

0
0
0
0

X = Don’t Care Logic 1 = High Level Logic 0 = Low Level

7-963

1
1
1
1

1
0
0

0
0
0
0

Typical Performance Characteristics

CD4063BMS

AMBIENT TEMPERATURE (TA) = +25oC

30

25

20

15

10

5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

AMBIENT TEMPERATURE (TA) = +25oC

15.0

12.5

10.0

7.5

5.0

2.5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN

CHARACTERISTICS

0-5-10-15

0

-5

-10

-15

-20

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

0-5-10-15

0

-5

-10

-25

-15V

-30

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

700

SUPPLY VOLTAGE (VDD) = 5V

600

500

400

300

200

100

0

PROPAGATION DELAY TIME (tTHL, tTLH) (ns)

10 30 40 50 60 70 80 90

AMBIENT TEMPERATURE (TA) = +25oC

10V

15V

20

LOAD CAPACITANCE (CL) (pF)

-15V

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

1750

1500

1250

1000

750

500

250

PROPAGATION DELAY TIME (tTHL, tTLH) (ns)

0

AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50pF

2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0
SUPPLY VOLTAGE (VDD) (V)

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 7. TYPICAL PROPAGA TION DELAY TIME vs LOAD

CAPACITANCE (“COMPARING INPUTS” TO OUTPUTS)

FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs SUPPLY

VOLTAGE (“COMPARING INPUTS” TO OUTPUTS)

7-964

CD4063BMS

Typical Performance Characteristics (Continued)

4

10

AMBIENT TEMPERATURE (TA) = +25oC

AMBIENT TEMPERATURE (TA) = +25oC

200

150

100

50

TRANSITION TIME (tTHL, tTLH) (ns)

0

0 40 60 80 10020

SUPPLY VOLTAGE (VDD) = 5V

LOAD CAPACITANCE (CL) (pF)

10V
15V

6
4

2

3

10

SUPPLY VOLTAGE (VDD) = 15V

6

LOAD CAPACITANCE (CL) = 50pF

4
2

2

10

6
4

2

10

6
4

2

POWER DISSIPATION PER GATE (PD) (µW)

1

0.1 1 10 10

864286422

INPUT FREQUENCY (f) (kHz)

5V, 50pF

2864

864

2

10V, 50pF

10V, 15pF

10

2864

3

FIGURE 9. TYPICAL TRANSITION TIME vs LOAD CAP ACITANCE FIGURE 10. TYPICAL POWER DISSIPATION vs FREQUENCY

Chip Dimensions and Pad Layout

Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10

-3

inch).

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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