Datasheet CD4052BE, CD4052BM, CD4051BE Specification

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Page 1

INH

C B A 0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Ch 0

Ch 1

Ch 2

Ch 3

Ch 4

Ch 5

Ch 6

Ch 7

C B A

COM

ax OR ay

bx OR by

cx OR cy

INH

X COM

Y COM

B A 0 0

0 1

1 0

1 1

Ch X0

Ch Y0

Ch X1

Ch Y1

Ch X2

Ch Y2

Ch X3

Ch Y3

CD4051B

CD4052B

CD4053B

Product Folder

Order Now

Technical Documents

Tools & Software

Support & Community

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

CD405xB CMOS Single 8-Channel Analog Multiplexer/Demultiplexer

with Logic-Level Conversion

1 Features

• Wide Range of Digital and Analog Signal Levels – Digital: 3 V to 20 V – Analog: ≤ 20 V

• Low ON Resistance, 125 Ω (Typical) Over 15 V Signal Input Range for VDD– VEE= 18 V

• High OFF Resistance, Channel Leakage of ±100 pA (Typical) at VDD– VEE= 18 V

• Logic-Level Conversion for Digital Addressing Signals of 3 V to 20 V (VDD– VSS= 3 V to 20 V) to Switch Analog Signals to 20 V 20 V) Matched Switch Characteristics, rON= 5 Ω (Typical) for VDD– VEE= 15 V Very Low Quiescent Power Dissipation Under All Digital-Control Input and Supply Conditions, 0.2 µW (Typical) at VDD– VSS= VDD– VEE= 10 V

• Binary Address Decoding on Chip

• 5 V, 10 V, and 15 V Parametric Ratings

• 100% Tested for Quiescent Current at 20 V

• Maximum Input Current of 1 µA at 18 V Over Full Package Temperature Range, 100 nA at 18 V and 25°C

• Break-Before-Make Switching Eliminates Channel Overlap

P-P

P-P(VDD

P-P

– VEE=

3 Description

The CD405xB analog multiplexers and demultiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. These multiplexer circuits dissipate extremely low quiescent power over the full VDD– VSSand VDD– VEEsupply-voltage ranges, independent of the logic state of the control signals.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

CDIP (16) 19.50 mm × 6.92 mm PDIP (16) 19.30 mm × 6.35 mm

CD405xB

SOIC (16) 9.90 mm × 3.91 mm SOP (16) 10.30 mm × 5.30 mm TSSOP (16) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Diagrams of CD405xB

(1)

2 Applications

• Analog and Digital Multiplexing and Demultiplexing

• A/D and D/A Conversion

• Signal Gating

• Factory Automation

• Televisions

• Appliances

• Consumer Audio

• Programmable Logic Circuits

• Sensors

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Page 2

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

www.ti.com

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 AC Performance Characteristics............................... 8

6.7 Typical Characteristics.............................................. 9

7 Parameter Measurement Information ................ 10

8 Detailed Description............................................ 15

8.1 Overview................................................................. 15

8.2 Functional Block Diagrams..................................... 15

8.3 Feature Description................................................. 17

8.4 Device Functional Modes........................................ 18

9 Application and Implementation ........................ 19

9.1 Application Information............................................ 19

9.2 Typical Application ................................................. 19

10 Power Supply Recommendations ..................... 20

11 Layout................................................................... 21

11.1 Layout Guidelines ................................................. 21

11.2 Layout Example .................................................... 21

12 Device and Documentation Support ................. 22

12.1 Documentation Support ........................................ 22

12.2 Related Links ........................................................ 22

12.3 Receiving Notification of Documentation Updates 22

12.4 Community Resources.......................................... 22

12.5 Trademarks........................................................... 22

12.6 Electrostatic Discharge Caution............................ 22

12.7 Glossary................................................................ 22

13 Mechanical, Packaging, and Orderable

Information........................................................... 22

4 Revision History

Changes from Revision H (April 2015) to Revision I Page

• Added: ON Channel Leakage Current to the Electrical Characteristics table ....................................................................... 6

• Added Note 3 to the Electrical Characteristics table.............................................................................................................. 6

• Added Figure 13................................................................................................................................................................... 11

Changes from Revision G (October 2003) to Revision H Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

• Added Device Information table. ............................................................................................................................................ 1

Product Folder Links: CD4051B CD4052B CD4053B

Page 3

OUT/IN CX OR CY

IN/OUT CX

INH

OUT/IN ax OR ay

OUT/IN bx OR by

IN/OUT

COMMON “Y” OUT/IN

INH

COMMON “X” OUT/IN

Y CHANNELS

IN/OUT

Y CHANNELS

IN/OUT

X CHANNELS IN/OUT

COM OUT/IN

INH

CHANNELS IN/OUT

CHANNELS

IN/OUT

CHANNELS

IN/OUT

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5 Pin Configuration and Functions

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

CD4051B E, M, NS, and PW Package

16-Pin PDIP, CDIP, SOIC, SOP, and TSSOP

(Top View)

CD4053B E, M, NS, and PW Package 16-Pin PDIP, CDIP, SOP, and TSSOP

CD4052B E, M, NS, and PW Package 16-Pin PDIP, CDIP, SOP, and TSSOP

(Top View)

NO. NAME

1 CH 4 IN/OUT I/O Channel 4 in/out 2 CH 6 IN/OUT I/O Channel 6 in/out 3 COM OUT/IN I/O Common out/in 4 CH 7 IN/OUT I/O Channel 7 in/out 5 CH 5 IN/OUT I/O Channel 5 in/out 6 INH I Disables all channels. See Table 1. 7 V 8 V 9 C I Channel select C. See Table 1. 10 B I Channel select B. See Table 1. 11 A I Channel select A. See Table 1. 12 CH 3 IN/OUT I/O Channel 3 in/out 13 CH 0 IN/OUT I/O Channel 0 in/out 14 CH 1 IN/OUT I/O Channel 1 in/out 15 CH 2 IN/OUT I/O Channel 2 in/out 16 V

Pin Functions CD4051B

EE SS

I/O DESCRIPTION

— Negative power input — Ground

— Positive power input

Product Folder Links: CD4051B CD4052B CD4053B

Page 4

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

Pin Functions CD4052B

NO. NAME

1 Y CH 0 IN/OUT I/O Channel Y0 in/out 2 Y CH 2 IN/OUT I/O Channel Y2 in/out 3 Y COM OUT/IN I/O Y common out/in 4 Y CH 3 IN/OUT I/O Channel Y3 in/out 5 Y CH 1 IN/OUT I/O Channel Y1 in/out 6 INH I Disables all channels. See Table 1. 7 V 8 V

EE SS

9 B I Channel select B. See Table 1. 10 A I Channel select A. See Table 1. 11 X CH 3 IN/OUT I/O Channel X3 in/out 12 X CH 0 IN/OUT I/O Channel X0 in/out 13 X COM IN/OUT I/O X common out/in 14 X CH 1 IN/OUT I/O Channel in/out 15 X CH 2 IN/OUT I/O Channel in/out 16 V

I/O DESCRIPTION

— Negative power input — Ground

— Positive power input

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Pin Functions CD4053B

NO. NAME

1 BY IN/OUT I/O B channel Y in/out 2 BX IN/OUT I/O B channel X in/out 3 CY IN/OUT I/O C channel Y in/out

CX OR CY

OUT/IN 5 CX IN/OUT I/O C channel X in/out 6 INH I Disables all channels. See Table 1. 7 V 8 V

EE SS

9 C I Channel select C. See Table 1. 10 B I Channel select B. See Table 1. 11 A I Channel select A. See Table 1. 12 AX IN/OUT I/O A channel X in/out 13 AY IN/OUT I/O A channel Y in/out

15 16 V

AX OR AY

OUT/IN

BX OR BY

OUT/IN

I/O DESCRIPTION

I/O C common out/in

— Negative power input — Ground

I/O A common out/in

I/O B common out/in

— Positive power input

Product Folder Links: CD4051B CD4052B CD4053B

Page 5

CD4051B,CD4052B,CD4053B

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SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)

Supply Voltage V+ to V-, Voltages Referenced to VSSTerminal –0.5 20 V DC Input Voltage –0.5 VDD+ 0.5 V DC Input Current Any One Input –10 10 mA

JMAX1

JMAX2

stg

Maximum junction temperature, ceramic package 175 °C Maximum junction temperature, plastic package 150 °C Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

CD4051B in PDIP, CDIP, SOIC, SOP, TSSOP Packages

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(ESD)

CD4053B in PDIP, CDIP, SOP and TSSOP Packages

(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

(2)

C101

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Charged-device model (CDM), per JEDEC specification JESD22-

(2)

C101

(1)

MIN MAX UNIT

VALUE UNIT

(1)

+3000 +2000

+2500 +1500

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).

MIN MAX UNIT

Temperature Range –55 125 °C

6.4 Thermal Information

CD405xB

THERMAL METRIC

(1)

16 PINS 16 PINS 16 PINS 16 PINS

Junction-to-ambient thermal resistance 67 73 64 108 °C/W

θJA

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(TSSOP)

UNITE (PDIP) M (SOIC) NS (SOP)

Product Folder Links: CD4051B CD4052B CD4053B

Page 6

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

6.5 Electrical Characteristics

Over operating free-air temperature range, V

PARAMETER

SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)

Quiescent Device Current, IDDMax

Drain to Source ON Resistance rONMax 0 ≤ VIS≤ V

Change in ON Resistance (Between Any Two Channels), ∆r

OFF Channel Leakage Current: Any Channel OFF (Max) or ALL Channels OFF (Common OUT/IN) (Max)

ON Channel Leakage Current: Any Channel ON (Max) or ALL Channels ON (Common OUT/IN) (Max)

Input, C

CD4051

Capacitance

Feed through, C

CD4052 18

CD4053 9

IOS

VIS(V) VEE(V) VSS(V) VDD(V) TEMP

5 or 0 -5 0 10.5 85°C ± 300

= ±5 V, and RL= 100 Ω, (unless otherwise noted)

SUPPLY

5 0 0 18 85°C ± 300

TEST CONDITIONS MIN TYP MAX UNIT

–55°C 5 –40°C 5

0 0 5

0 0 10

0 0 15

0 0 5

0 0 15 5

0 0 18

–5 –5 –5 25°C 5

25°C 0.04 5

85°C 150 125°C 150 –55°C 10 –40°C 10

25°C 0.04 10

85°C 300 125°C 300 –55°C 20 –40°C 20

25°C 0.04 20

85°C 600 125°C 600 –55°C 100 –40°C 100

25°C 0.08 100

85°C 3000 125°C 3000 –55°C 800 –40°C 850

25°C 470 1050

85°C 1200 125°C 1300 –55°C 310 –40°C 300

25°C 180 400

85°C 520 125°C 550 –55°C 200 –40°C 210

25°C 125 240

85°C 300 125°C 300

25°C

–55°C ± 100 –40°C

25°C ± 0.01 ± 100

85°C ± 1000 125°C

25°C

(1)

0.2

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(2)

(3)

µA

Ω

Ω0 0 10 10

pFOutput, C

(1) Peak-to-Peak voltage symmetrical about (VDD– VEE) / 2. (2) Determined by minimum feasible leakage measurement for automatic testing. (3) Does not apply to Hi-Rel CD4051BF and CD4051BFA3 devices.

Product Folder Links: CD4051B CD4052B CD4053B

Page 7

CD4051B,CD4052B,CD4053B

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SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

Electrical Characteristics (continued)

Over operating free-air temperature range, V

PARAMETER

Propagation Delay Time (Signal Input to Output)

CONTROL (ADDRESS OR INHIBIT), V

Input Low Voltage, VIL, Max

Input High Voltage, VIH, Min

Input Current, IIN(Max) VIN= 0, 18 18

Propagation Delay Time

Input Capacitance, CIN(Any Address or Inhibit Input) 5 7.5 pF

Address-to-Signal OUT (Channels ON or OFF) (See Figure 10, Figure 11, and Figure 15)

Inhibit-to-Signal OUT (Channel Turning ON) (See Figure 11)

Inhibit-to-Signal OUT (Channel Turning OFF) (See Figure 17)

VIS(V) VEE(V) VSS(V) VDD(V) TEMP

VIL= V through 1 kΩ ; VIH= V through 1 kΩ

tr, tf= 20

CL= 50 pF, RL= 10 kΩ

tr, tf= 20

CL= 50 pF,

RL= 1 kΩ

tr, tf= 20

CL= 50 pF, RL= 10 kΩ

= ±5 V, and RL= 100 Ω, (unless otherwise noted)

SUPPLY

ns,

TEST CONDITIONS MIN TYP MAX UNIT

RL= 200 kΩ , 5 CL= 50 pF, 10 15 30 tr, tf= 20 ns 15 10 20

VEE= VSS, RL= 1 kΩ to VSS, IIS< 2 µA on All OFF Channels

0 0 5 450 720 0 0 10 160 320 0 0 15 120 240

–5 0 5 225 450

0 0 5 400 720 0 0 10 160 320 0 0 15 120 240

–10 0 5 200 400

0 0 5 200 450 0 0 10 90 210 0 0 15 70 160

–10 0 5 130 300

25°C

–55°C 1.5 –40°C 1.5

25°C 1.5

85°C 1.5 125°C 1.5 –55°C 3 –40°C 3

25°C 3

85°C 3 125°C 3 –55°C 4 –40°C 4

25°C 4

85°C 4 125°C 4 –55°C 3.5 –40°C 3.5

25°C 3.5

85°C 3.5 125°C 3.5 –55°C 7 –40°C 7

25°C 7

85°C 7 125°C 7 –55°C 11 –40°C 11

25°C 11

85°C 11 125°C 11 –55°C ±0.1 –40°C ±0.1

25°C

85°C ± 1 125°C ± 1

(1)

30 60

–5

± 10

± 0.1

µA

Product Folder Links: CD4051B CD4052B CD4053B

Page 8

20 40

Log dB

–

20 40

Log dB

–

20 3

Log

–

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

6.6 AC Performance Characteristics

PARAMETER

Cutoff (–3dB) Frequency Channel ON (Sine Wave Input)

Total Harmonic Distortion, THD

–40dB Feedthrough Frequency (All Channels OFF)

–40dB Signal Crosstalk Frequency

Address-or-Inhibit-toSignal Crosstalk

(1) Peak-to-Peak voltage symmetrical about (VDD- VEE) / 2. (2) Both ends of channel.

VIS(V) VDD(V) RL(kΩ)

(1)

VEE= VSS, fIS= 1 kHz Sine Wave

(1)

VEE= VSS, CD4052 10

(1)

VEE= VSS,

VEE= 0, VSS= 0, tr, tf= 20 ns, VCC= VDD– VSS(Square Wave)

10 1 VOSat Common OUT/IN

VEE= VSS,

5 10 0.2% 15 0.12%

10 1

10 1 Between Any two Channels 3

10 10

(2)

TEST CONDITIONS

CD4053 30 CD4052 25 CD4051 20

VOSat Any Channel 60

CD4053 8

VOSat Common OUT/IN

CD4051 12

VOSat Any Channel 8

Between Sections, CD4052 Only

Between Any Two Sections, CD4053 Only

Measured on Common 6 Measured on Any Channel 10 In Pin 2, Out Pin 14 2.5 In Pin 15, Out Pin 14 6

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TYP UNIT

MHz

0.3%

MHz

65 65

PEAK

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Page 9

T = 25 C

ALTERNATING “O”

C = 50pF

AND “I” PATTERN

101010

543

V = 15V

V = 5V

C = 15pF

SWITCHING FREQUENCY (kHz)

, POWER DISSIPATION PACKAGE ( W)µ

TEST CIRCUIT

1011

14 15

CD4051

100Ω

B/D

CD4029

A B C

V = 10V

-6 -4 -2 0 2 4 6 V , INPUT SIGNAL VOLTAGE (V)

, OUTPUT SIGNAL VOLTAGE (V)

-6

-4

-2

V = 5V

V = 0V

V = -5V

T = 25 C

R = 100k , R = 10k

L L

Ω Ω

100Ω

500Ω

1kΩ

-10 -7.5 -5 -2.5 0 2.5 5 7.5 10

100

200

300

400

600

500

V , INPUT SIGNAL VOLTAGE (V)

, CHANNEL ON RESISTANCE ( )Ω

T = 25 C

15V

10V

V - V = 5V

DD EE

-10 -7.5 -5 -2.5 0 2.5 5 7.5 10

100

150

200

250

V , INPUT SIGNAL VOLTAGE (V)

, CHANNEL ON RESISTANCE ( )Ω

V - V = 15V

DD EE

T = 125 C

T = 25 C

T = -55 C

-4 -3 -2 -1 0 1 2 3 4

100

200

300

400

500

600

, CHANNEL ON RESISTANCE ( )Ω

T = 125 C

T = -55 C

T = 25 C

V - V = 5V

DD EE

-10 -7.5 -5 -2.5 0 2.5 5 7.5 10

100

150

200

250

300

V , INPUT SIGNAL VOLTAGE (V)

, CHANNEL ON RESISTANCE ( )Ω

T = 125 C

T = 25 C

T = -55 C

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6.7 Typical Characteristics

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

Figure 1. Channel ON Resistance vs Input Signal Voltage

(All Types)

Figure 3. Channel ON Resistance vs Input Signal Voltage

(All Types)

Figure 2. Channel ON Resistance vs Input Signal Voltage

(All Types)

Figure 4. Channel ON Resistance vs Input Signal Voltage

(All Types)

Figure 5. ON Characteristics for 1 of 8 Channels

(CD4051B)

Figure 6. Dynamic Power Dissipation vs Switching

Product Folder Links: CD4051B CD4052B CD4053B

Frequency (CD4051B)

Page 10

t = 20ns

10%

90%

50%

10%

50%

90%

10%

50%

90%

t = 20ns

TURN-OFF TIME

TURN-ON TIME

t = 20ns

10%

90%

50%

10%

50%

90%

10%

90%

t = 20ns

TURN-OFF TIME

TURN-ON

TIME

V = 5V

V = 0V

V = -7.5V

7 8

(B)

(C)

(D)

(A)

V = 7.5V

7.5V 1616 1616

7 8

V = 5V

V = 15V

V = 0V

7 8

V = -10V

V = 0V

V = -5V

1010

SWITCHING FREQUENCY (kHz)

, POWER DISSIPATION PACKAGE (

µW)

V = 15V

V = 5V

T = 25 C

ALTERNATING “O”

C = 50pF

AND “I” PATTERN

6 7

14 15

13 12

CD4052

100Ω

B/D

CD4029

A B

TEST CIRCUIT

V = 10V

C = 15pF

101010

V = 15V

V = 10V

V = 5V

T = 25 C

ALTERNATING “O”

C = 50pF

AND “I” PATTERN

C = 15pF

SWITCHING FREQUENCY (kHz)

, POWER DISSIPATION PACKAGE (

µW)

TEST CIRCUIT

9 3 5

10 11

6 7

CD4053

100Ω

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

Typical Characteristics (continued)

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Figure 7. Dynamic Power Dissipation vs Switching

Frequency (CD4052B)

7 Parameter Measurement Information

Figure 9. Typical Bias Voltages

The ADDRESS (digital-control inputs) and INHIBIT logic levels are: 0 = V and 1 = VDD. The analog signal (through the TG) may swing from VEEto VDD.

Figure 8. Dynamic Power Dissipation vs Switching

Frequency (CD4053B)

NOTE

Figure 10. Waveforms, Channel Being Turned ON

(RL= 1 kΩ)

Product Folder Links: CD4051B CD4052B CD4053B

Figure 11. Waveforms, Channel Being Turned OFF

(RL= 1 kΩ)

Page 11

CD4051

CD4052

CD4053

CLOCK

R C

OUTPUT

L L

OUTPUT

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

VDD VDD

CD4053

CD4052

CD4051

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

CD4053

CD4052

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CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

Parameter Measurement Information (continued)

Figure 12. OFF Channel Leakage Current - Any Channel OFF

Figure 13. On Channel Leakage Current - Any Channel On

Figure 14. OFF Channel Leakage Current - All Channels OFF

Figure 15. Propagation Delay - Address Input to Signal Output

Product Folder Links: CD4051B CD4052B CD4053B

Page 12

CD4053

1 2 3 4 5 6 7 8 9

CD4052

1 2 3 4 5 6 7 8 9

X-Y

PLOTTER

1kΩ

RANGE

“ON”

KEITHLEY

160 DIGITAL

MULTIMETER

H.P.

MOSELEY

7030A

10k

CD4051B

µA

MEASURE < 2 A ON ALLµ “OFF” CHANNELS (e.g., CHANNEL 6)

1 2 3 4 5 6 7 8 9

µA

MEASURE < 2 A ON ALL

“OFF” CHANNELS (e.g., CHANNEL by)

CD4053B

1 2 3 4 5 6 7 8 9

µA

MEASURE < 2 A ON ALLµ “OFF” CHANNELS (e.g., CHANNEL 2x)

CD4052B

1 2 3 4 5 6 7 8 9

t AND t

CLOCK

PHL PLH

OUTPUT

CD4051

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

CD4052

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

CD4053

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

OUTPUT

t AND t

CLOCK

PHL PLH

CLOCK

50pF

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

Parameter Measurement Information (continued)

Figure 16. Propagation Delay - Inhibit Input to Signal Output

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Figure 18. Quiescent Device Current Figure 19. Channel ON Resistance Measurement

Figure 17. Input Voltage Test Circuits (Noise Immunity)

Product Folder Links: CD4051B CD4052B CD4053B

Circuit

Page 13

LINK

DIFF.

AMPLIFIER/

LINE DRIVER

DIFF.

RECEIVER

DEMULTIPLEXING

DIFF.

MULTIPLEXING

DIFFERENTIAL

SIGNALS

CD4052

P-P

ON OR OFF

CHANNEL IN Y

ON OR OFF

CHANNEL IN X

OFF

CHANNEL

COMMON

CHANNEL

RF VM

CHANNEL

P-P

OFF

CHANNEL

RF VM

OFF

CHANNEL

6 7 8

P-P

CD4051

CD4053

NOTE: Measure inputs sequentially, to both V and V connect all

DD SS

unused inputs to either V or V .

DD SS

1 2 3 4 5 6 7 8 9

CD4052

NOTE: Measure inputs sequentially, to both V and V connect all

DD SS

unused inputs to either V or V .

DD SS

1 2 3 4 5 6 7 8 9

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CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

Parameter Measurement Information (continued)

Figure 20. Input Current

Figure 21. Feedthrough (All Types) Figure 22. Crosstalk Between Any Two Channels

(All Types)

Figure 23. Crosstalk Between Duals or Triplets (CD4052B, CD4053B)

Special Considerations: In applications where separate power sources are used to drive VDDand the signal inputs,

the VDDcurrent capability should exceed VDD/RL(RL= effective external load). This provision avoids permanent current flow or clamp action on the VDDsupply when power is applied or removed from the CD4051B, CD4052B or CD4053B.

Figure 24. Typical Time-Division Application of the CD4052B

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Page 14

1/2

CD4556

A B C

CD4051B

INH

A B C

CD4051B

INH

A B C

CD4051B

INH

A B C

COMMON

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

Parameter Measurement Information (continued)

Figure 25. 24-to-1 MUX Addressing

www.ti.com

Product Folder Links: CD4051B CD4052B CD4053B

Page 15

INH

134 2 5 1 12 15 14

COMMON

OUT/IN

01234567

BINARY

1 OF 8

DECODER

WITH

INHIBIT

LOGIC LEVEL

CONVERSION

8 7

CHANNEL IN/OUT

CD4051B,CD4052B,CD4053B

www.ti.com

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

8 Detailed Description

8.1 Overview

The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20 V digital signal amplitudes of 4.5 V to 20 V (if VDD– VSS= 3 V, a VDD– VEEof up to 13 V can be controlled; for VDD– VEElevel differences above 13 V, a VDD– VSSof at least 4.5 V is required). For example, if VDD= +4.5 V, VSS= 0 V, and VEE= –13.5 V, analog signals from –13.5 V to +4.5 V can be controlled by digital inputs of 0 V to 5 V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD– VSSand VDD– V supply-voltage ranges, independent of the logic state of the control signals. When a logic 1 is present at the inhibit input terminal, all channels are off.

The CD4051B device is a single 8-channel multiplexer having three binary control inputs, A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to the output.

The CD4052B device is a differential 4-channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs.

The CD4053B device is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole, double-throw configuration.

When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs and the COMMON OUT/IN terminals are the inputs.

can be achieved by

P-P

8.2 Functional Block Diagrams

All inputs are protected by standard CMOS protection network.

Figure 26. Functional Block Diagram, CD4051B

Product Folder Links: CD4051B CD4052B CD4053B

Page 16

INH

123 5 1 2 13

COMMON

OUT/IN

axaybxbycxcy

V V

SS EE

IN/OUT

BINARY TO

1 OF 2

DECODERS

WITH

INHIBIT

LOGIC LEVEL

CONVERSION

COMMON

OUT/IN

COMMON

OUT/IN

ax OR ay

bx OR by

cx OR cy

1211 15 14

0123

3210

X CHANNELS IN/OUT

Y CHANNELS IN/OUT

BINARY

1 OF 4

DECODER

WITH

INHIBIT

COMMON Y

OUT/IN

COMMON X

OUT/IN

INH

V V

SS EE

4251

LOGIC

LEVEL

CONVERSION

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

Functional Block Diagrams (continued)

www.ti.com

All inputs are protected by standard CMOS protection network.

Figure 27. Functional Block Diagram, CD4052B

Figure 28. Functional Block Diagram, CD4053B

All inputs are protected by standard CMOS protection network.

Product Folder Links: CD4051B CD4052B CD4053B

Page 17

CD4051B,CD4052B,CD4053B

www.ti.com

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

8.3 Feature Description

The CD405xB line of multiplexers and demultiplexers can accept a wide range of digital and analog signal levels. Digital signals range from 3 V to 20 V, and analog signals are accepted at levels ≤ 20 V. They have low ON resistance, typically 125 Ω over 15 V loss through the switch. Matched switch characteristics are typically rON= 5 Ω for VDD– VEE= 15 V.

The CD405xB devices also have high OFF resistance, which keeps from wasting power when the switch is in the OFF position, with typical channel leakage of ±100 pA at VDD– VEE= 18 V. Very low quiescent power dissipation under all digital-control input and supply conditions, typically 0.2 µW at VDD– VSS= VDD– VEE= 10 V keeps power consumption total very low. All devices have been 100% tested for quiescent current at 20 V with maximum input current of 1 µA at 18 V over the full package temperature range, and only 100 nA at 18 V and 25°C.

Logic-level conversion for digital addressing signals of 3 V to 20 V (VDD– VSS= 3 V to 20 V) to switch analog signals to 20 V

P-P(VDD

– VEE= 20 V). Binary address decoding on chip makes channel selection easy. When

channels are changed, a break-before-make system eliminates channel overlap.

signal input range for VDD– VEE= 18 V. This allows for very little signal

P-P

Product Folder Links: CD4051B CD4052B CD4053B

Page 18

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

8.4 Device Functional Modes

www.ti.com

Table 1. Truth Table

INPUT STATES

INHIBIT C B A

CD4051B

0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 X X X None

CD4052B

0 0 0 0x, 0y 0 0 1 1x, 1y 0 1 0 2x, 2y 0 1 1 3x, 3y 1 X X None

CD4053B

0 X X 0 ax 0 X X 1 ay 0 X 0 X bx 0 X 1 X by 0 0 X X cx 0 1 X X cy 1 X X X None

(1) X = Don't Care

(1)

ON CHANNEL(S)

Product Folder Links: CD4051B CD4052B CD4053B

Page 19

INH

C B A 0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0 1 1 1

Ch 0

Ch 1

Ch 2

Ch 3

Ch 4

Ch 5

Ch 6

Ch 7

C B A

COM

CD4051B

Microcontroller

Input Channel Select

Pull-down resistors (10NŸ)

3.3 V

CD4051B,CD4052B,CD4053B

www.ti.com

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CD405xB multiplexers and demultiplexers can be used for a wide variety of applications.

9.2 Typical Application

One application of the CD4051B is to use it in conjunction with a microcontroller to poll a keypad. Figure 29 shows the basic schematic for such a polling system. The microcontroller uses the channel select pins to cycle through the different channels while reading the input to see if a user is pressing any of the keys. This is a very robust setup, allowing for multiple simultaneous key-presses with very little power consumption. It also uses very few pins on the microcontroller. The down side of polling is that the microcontroller must continually scan the keys for a press and can do little else during this process.

Figure 29. The CD4051B Being Used to Help Read Button Presses on a Keypad.

9.2.1 Design Requirements

These devices use CMOS technology and have balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing.

Product Folder Links: CD4051B CD4052B CD4053B

Page 20

-6 -4 -2 0 2 4 6 V , INPUT SIGNAL VOLTAGE (V)

, OUTPUT SIGNAL VOLTAGE (V)

-6

-4

-2

V = 5V

V = 0V

V = -5V

T = 25 C

R = 100k , R = 10k

L L

Ω Ω

100Ω

500Ω

1kΩ

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

www.ti.com

Typical Application (continued)

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions – For switch time specifications, see propagation delay times in Electrical Characteristics. – Inputs should not be pushed more than 0.5 V above VDDor below VEE. – For input voltage level specifications for control inputs, see VIHand VILin Electrical Characteristics.

2. Recommended Output Conditions – Outputs should not be pulled above VDDor below VEE.

3. Input/output current consideration: The CD405xB series of parts do not have internal current drive circuitry and thus cannot sink or source current. Any current will be passed through the device.

9.2.3 Application Curve

Figure 30. ON Characteristics for 1 of 8 Channels

(CD4051B)

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

Electrical Characteristics.

Each VCCterminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or

0.022-μF capacitor is recommended for each VCCbecause the VCCpins will be tied together internally. For devices with dual supply pins operating at different voltages, for example VCCand VDD, a 0.1-µF bypass capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.

Product Folder Links: CD4051B CD4052B CD4053B

Page 21

WORST

BETTER

BEST

1W min.

CD4051B,CD4052B,CD4053B

www.ti.com

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

11 Layout

11.1 Layout Guidelines

Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and so they will have to turn corners. Figure 31 shows progressively better techniques of rounding corners. Only the last example maintains constant trace width and minimizes reflections.

11.2 Layout Example

Figure 31. Trace Example

Product Folder Links: CD4051B CD4052B CD4053B

Page 22

CD4051B,CD4052B,CD4053B

SCHS047I –AUGUST 1998–REVISED SEPTEMBER 2017

www.ti.com

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

• Implications of Slow or Floating CMOS Inputs, SCBA004

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now.

Table 2. Related Links

PARTS PRODUCT FOLDER ORDER NOW

CD4051B Click here Click here Click here Click here Click here CD4052B Click here Click here Click here Click here Click here CD4053B Click here Click here Click here Click here Click here

TECHNICAL

DOCUMENTS

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

12.4 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: CD4051B CD4052B CD4053B

Page 23

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

7901502EA ACTIVE CDIP J 16 1 Non-RoHS

8101801EA ACTIVE CDIP J 16 1 Non-RoHS

CD4051BE ACTIVE PDIP N 16 25 RoHS & Green NIPDAU | SN N / A for Pkg Type -55 to 125 CD4051BE

CD4051BEE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4051BE

CD4051BF ACTIVE CDIP J 16 1 Non-RoHS

CD4051BF3A ACTIVE CDIP J 16 1 Non-RoHS

CD4051BM ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM

CD4051BM96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CD4051BM CD4051BM96G3 ACTIVE SOIC D 16 2500 RoHS & Green SN Level-1-260C-UNLIM -55 to 125 CD4051BM CD4051BM96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM

CD4051BMG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM

CD4051BMT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM

CD4051BNSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051B

CD4051BNSRE4 ACTIVE SO NS 16 2000 TBD Call TI Call TI -55 to 125

CD4051BPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM051B

CD4051BPWE4 ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM051B

CD4051BPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CM051B

CD4051BPWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM051B

CD4052BE ACTIVE PDIP N 16 25 RoHS & Green NIPDAU | SN N / A for Pkg Type -55 to 125 CD4052BE

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& Green

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

SNPB N / A for Pkg Type -55 to 125 7901502EA

SNPB N / A for Pkg Type -55 to 125 8101801EA

SNPB N / A for Pkg Type -55 to 125 CD4051BF

SNPB N / A for Pkg Type -55 to 125 CD4051BF3A

CD4052BF3A

CD4053BF3A

18-Aug-2022

Samples

(4/5)

Samples

Addendum-Page 1

Page 24

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

CD4052BEE4 ACTIVE PDIP N 16 25 RoHS &

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

NIPDAU N / A for Pkg Type -55 to 125 CD4052BE

Non-Green

CD4052BF ACTIVE CDIP J 16 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 CD4052BF

& Green

CD4052BF3A ACTIVE CDIP J 16 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 7901502EA

& Green

CD4052BM ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM

CD4052BM96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CD4052BM CD4052BM96G3 ACTIVE SOIC D 16 2500 RoHS & Green SN Level-1-260C-UNLIM -55 to 125 CD4052BM CD4052BM96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM

CD4052BMG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM

CD4052BMT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM

CD4052BNSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052B

CD4052BPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM052B

CD4052BPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CM052B CD4052BPWRG3 ACTIVE TSSOP PW 16 2000 RoHS & Green SN Level-1-260C-UNLIM -55 to 125 CM052B CD4052BPWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM052B

CD4053BE ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4053BE

CD4053BEE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4053BE

CD4053BF ACTIVE CDIP J 16 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 CD4053BF

& Green

CD4053BF3A ACTIVE CDIP J 16 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 8101801EA

& Green

CD4053BM ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M

CD4053BM96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CD4053M

CD4052BF3A

CD4053BF3A

18-Aug-2022

Samples

(4/5)

Samples

Addendum-Page 2

Page 25

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

CD4053BM96E4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M CD4053BM96G3 ACTIVE SOIC D 16 2500 RoHS & Green SN Level-1-260C-UNLIM -55 to 125 CD4053M CD4053BM96G4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M

CD4053BMG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M

CD4053BMT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M

CD4053BNSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053B

CD4053BPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM053B

CD4053BPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 CM053B CD4053BPWRG3 ACTIVE TSSOP PW 16 2000 RoHS & Green SN Level-1-260C-UNLIM -55 to 125 CM053B CD4053BPWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM053B

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

18-Aug-2022

(4/5)

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Samples

Addendum-Page 3

Page 26

PACKAGE OPTION ADDENDUM

www.ti.com

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

18-Aug-2022

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD4051B, CD4051B-MIL, CD4052B, CD4052B-MIL, CD4053B, CD4053B-MIL :

Catalog : CD4051B, CD4052B, CD4053B

•

Automotive : CD4051B-Q1, CD4051B-Q1, CD4053B-Q1, CD4053B-Q1

•

Military : CD4051B-MIL, CD4052B-MIL, CD4053B-MIL

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 4

Page 27

PACKAGE MATERIALS INFORMATION

Reel Width (W1)

REEL DIMENSIONS

A0 B0 K0

Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1Q2 Q2

Q3 Q3Q4 Q4

User Direction of Feed

Reel

Diameter

www.ti.com 12-Aug-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

CD4051BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD4051BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

CD4051BM96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD4051BM96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD4051BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD4051BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

CD4051BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD4051BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD4051BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD4051BPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD4052BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

CD4052BM96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD4052BM96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD4052BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

CD4052BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

CD4052BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Device Package

Type

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

Page 28

PACKAGE MATERIALS INFORMATION

www.ti.com 12-Aug-2022

Device Package

Type

CD4052BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD4052BPWRG3 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD4052BPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD4053BM96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1

CD4053BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD4053BM96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD4053BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

CD4053BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD4053BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD4053BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD4053BPWRG3 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD4053BPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 2

Page 29

PACKAGE MATERIALS INFORMATION

TAPE AND REEL BOX DIMENSIONS

Width (mm)

www.ti.com 12-Aug-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD4051BM96 SOIC D 16 2500 356.0 356.0 35.0 CD4051BM96 SOIC D 16 2500 340.5 336.1 32.0

CD4051BM96 SOIC D 16 2500 364.0 364.0 27.0 CD4051BM96G3 SOIC D 16 2500 364.0 364.0 27.0 CD4051BM96G4 SOIC D 16 2500 356.0 356.0 35.0 CD4051BM96G4 SOIC D 16 2500 340.5 336.1 32.0

CD4051BNSR SO NS 16 2000 356.0 356.0 35.0

CD4051BPWR TSSOP PW 16 2000 367.0 367.0 35.0 CD4051BPWR TSSOP PW 16 2000 364.0 364.0 27.0

CD4051BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0

CD4052BM96 SOIC D 16 2500 340.5 336.1 32.0

CD4052BM96 SOIC D 16 2500 364.0 364.0 27.0 CD4052BM96G3 SOIC D 16 2500 364.0 364.0 27.0 CD4052BM96G4 SOIC D 16 2500 340.5 336.1 32.0

CD4052BNSR SO NS 16 2000 356.0 356.0 35.0

CD4052BPWR TSSOP PW 16 2000 367.0 367.0 35.0 CD4052BPWR TSSOP PW 16 2000 364.0 364.0 27.0

CD4052BPWRG3 TSSOP PW 16 2000 364.0 364.0 27.0

Pack Materials-Page 3

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PACKAGE MATERIALS INFORMATION

www.ti.com 12-Aug-2022

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD4052BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0

CD4053BM96 SOIC D 16 2500 364.0 364.0 27.0

CD4053BM96 SOIC D 16 2500 340.5 336.1 32.0 CD4053BM96G3 SOIC D 16 2500 364.0 364.0 27.0 CD4053BM96G4 SOIC D 16 2500 340.5 336.1 32.0

CD4053BNSR SO NS 16 2000 356.0 356.0 35.0

CD4053BPWR TSSOP PW 16 2000 367.0 367.0 35.0

CD4053BPWR TSSOP PW 16 2000 364.0 364.0 27.0 CD4053BPWRG3 TSSOP PW 16 2000 364.0 364.0 27.0 CD4053BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0

Pack Materials-Page 4

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PACKAGE MATERIALS INFORMATION

www.ti.com 12-Aug-2022

TUBE

T - Tube

height

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

CD4051BE N PDIP 16 25 506 13.97 11230 4.32 CD4051BE N PDIP 16 25 506.1 9 600 5.4

CD4051BE N PDIP 16 25 506 13.97 11230 4.32 CD4051BEE4 N PDIP 16 25 506 13.97 11230 4.32 CD4051BEE4 N PDIP 16 25 506 13.97 11230 4.32

CD4051BM D SOIC 16 40 506.6 8 3940 4.32

CD4051BM D SOIC 16 40 507 8 3940 4.32 CD4051BMG4 D SOIC 16 40 507 8 3940 4.32 CD4051BMG4 D SOIC 16 40 506.6 8 3940 4.32

CD4051BPW PW TSSOP 16 90 530 10.2 3600 3.5

CD4051BPWE4 PW TSSOP 16 90 530 10.2 3600 3.5

CD4052BE N PDIP 16 25 506 13.97 11230 4.32

CD4052BE N PDIP 16 25 506.1 9 600 5.4

CD4052BEE4 N PDIP 16 25 506.1 9 600 5.4 CD4052BEE4 N PDIP 16 25 506 13.97 11230 4.32 CD4052BEE4 N PDIP 16 25 506 13.97 11230 4.32

CD4052BM D SOIC 16 40 507 8 3940 4.32 CD4052BMG4 D SOIC 16 40 507 8 3940 4.32

CD4052BPW PW TSSOP 16 90 530 10.2 3600 3.5

CD4053BE N PDIP 16 25 506 13.97 11230 4.32

CD4053BEE4 N PDIP 16 25 506 13.97 11230 4.32 CD4053BEE4 N PDIP 16 25 506 13.97 11230 4.32

CD4053BM D SOIC 16 40 507 8 3940 4.32 CD4053BMG4 D SOIC 16 40 507 8 3940 4.32

CD4053BPW PW TSSOP 16 90 530 10.2 3600 3.5

L - Tube length

Pack Materials-Page 5

Page 32

Page 33

Page 34

PACKAGE OUTLINE

5.1

4.9

NOTE 3

SCALE 2.500

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

SEATING

6.6

TYP

6.2 PIN 1 INDEX AREA

4.5

4.3

NOTE 4

14X 0.65

4.55

0.30

16X

0.19

0.1 C A B

1.2 MAX

PLANE

0.1 C

(0.15) TYP

SEE DETAIL A

GAGE PLANE

0.25

0.75

-80

0.50

A 20

DETAIL A

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

0.15

0.05

www.ti.com

Page 35

EXAMPLE BOARD LAYOUT

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

16X (0.45)

14X (0.65)

16X (1.5)

SYMM

(R0.05) TYP

SYMM

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SOLDER MASK

OPENING

EXPOSED METAL

0.05 MAX ALL AROUND

NON-SOLDER MASK

DEFINED

(PREFERRED)

METAL

15.000

SOLDER MASK DETAILS

METAL UNDER SOLDER MASK

0.05 MIN ALL AROUND

SOLDER MASK

DEFINED

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SOLDER MASK OPENING

EXPOSED METAL

4220204/A 02/2017

www.ti.com

Page 36

EXAMPLE STENCIL DESIGN

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

16X (0.45)

14X (0.65)

16X (1.5)

SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

(R0.05) TYP

SYMM

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

Page 37

Page 38

Page 39

Page 40

PACKAGE OUTLINE

10.4

10.0

NOTE 3

SCALE 1.500

8.2

TYP

7.4 PIN 1 ID

AREA

5.4

5.2

NOTE 4

14X 1.27

8.89

0.51

16X

0.35

0.25 C A B

SOP - 2.00 mm max heightNS0016A

SOP

SEATING PLANE

0.1 C

2.00 MAX

0.15 TYP

SEE DETAIL A

GAGE PLANE

0 - 10

0.25

1.05

0.55 (1.25)

0.3

0.1

DETAIL A

TYPICAL

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com

Page 41

EXAMPLE BOARD LAYOUT

SOP - 2.00 mm max heightNS0016A

SOP

16X (1.85)

16X (0.6)

14X (1.27)

(R0.05) TYP

SYMM

(7)

SEE DETAILS

SYMM

LAND PATTERN EXAMPLE

SCALE:7X

METAL

0.07 MAX ALL AROUND

NON SOLDER MASK

DEFINED

SOLDER MASK OPENING

SOLDER MASK

OPENING

0.07 MIN ALL AROUND

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL

4220735/A 12/2021

www.ti.com

Page 42

EXAMPLE STENCIL DESIGN

SOP - 2.00 mm max heightNS0016A

SOP

16X (1.85)

16X (0.6)

14X (1.27)

(R0.05) TYP

SYMM

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:7X

SYMM

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

Page 43

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Datasheet CD4052BE, CD4052BM, CD4051BE Specification

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features

3 Description

2 Applications

Table of Contents

4 Revision History

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

6.6 AC Performance Characteristics

6.7 Typical Characteristics

7 Parameter Measurement Information

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagrams

8.3 Feature Description

8.4 Device Functional Modes

9 Application and Implementation

9.1 Application Information

9.2 Typical Application

9.2.1 Design Requirements

9.2.2 Detailed Design Procedure

9.2.3 Application Curve

10 Power Supply Recommendations

11 Layout

11.1 Layout Guidelines

11.2 Layout Example

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

12.2 Related Links

12.3 Receiving Notification of Documentation Updates

12.4 Community Resources

12.5 Trademarks

12.6 Electrostatic Discharge Caution

12.7 Glossary

13 Mechanical, Packaging, and Orderable Information