Datasheet CD4051BCSJX, CD4051BCSJ, CD4051BCN, CD4051BCMX, CD4051BCMTCX Datasheet (Fairchild Semiconductor)
...Page 1
© 2000 Fairchild Semiconductor Corporation DS005662 www.fairchildsemi.com
November 1983
Revised August 2000
CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multi plexer/Demultiplexe r • Dual 4-Channel Analog
Multiplexer/Demultiplexer • Triple 2-Channel Analog Mult iplexer/Demultiplexer
CD4051BC • CD4052BC • CD4053BC
Single 8-Channel Analog Multiplexer/Demultiplexer •
Dual 4-Channel Analog Multiplexer/Demultiplexer •
Triple 2-Channel Analog Multiplexer/Demultiplexer
General Description
The CD4051BC, CD4 052BC, an d CD405 3BC analo g multiplexers/demultiplexers are digitally controlled analog
switches having low “ON” impedance and very low “OFF”
leakage currents. Cont rol of analog signals up to 15V
p-p
can be achieved by di gital s ignal amplitud es of 3−15V. For
example, if V
DD
= 5V, V
SS
= 0V and V
EE
= −5V, analog sig-
nals from
−5V to +5V can be contro lled by dig ital input s of
0
−5V. The multiplexer circuits dissipate extremely low qui-
escent power over the full V
DD−VSS
and V
DD−VEE
supply
voltage ranges, independent of the logic state of the control
signals. When a logical “1” is present at the inhibit input terminal all channels are “OFF”.
CD4051BC is a single 8-c hannel multiplexe r having three
binary control input s. A , B, and C, and an inhibit i n put . T he
three binary signals select 1 of 8 channels to be turned
“ON” and connect the input to the output.
CD4052BC is a differential 4-channel mu ltiplexer having
two binary control inputs, A and B, and an inhibit input. The
two binary input sig nals select 1 or 4 pairs of channels to
be turned on and connect the differen tial analog inputs to
the differential outputs.
CD4053BC is a triple 2-channel multiplexer having three
separate digital con trol inputs, A, B , and C, and an in hibit
input. Each control in put selects one of a pair of ch annels
which are connected in a single-pole double-throw configuration.
Features
■ Wide range of digital and analog signal levels:
digital 3 – 15V, analog to 15V
p-p
■ Low “ON” resistance: 80Ω (typ.) over entire 15V
p-p
signal-input range for V
DD
− V
EE
= 15V
■ High “OFF” resistance:
channel leakage of
±10 pA (typ.) at V
DD
− V
EE
= 10V
■ Logic level conversion for digital addressing signals of
3 – 15V (V
DD
− V
SS
= 3 – 15V) to switch analog signals
to 15 V
p-p
(V
DD
− V
EE
= 15V)
■ Matched switch characteristics:
∆R
ON
= 5Ω (typ.) for V
DD
− V
EE
= 15V
■ Very low quiescent power dissipation under all
digital-control input and supply conditions:
1
µ W (typ.) at V
DD
− V
SS
= V
DD
− V
EE
= 10V
■ Binary address decoding on chip
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Order Number Package Number Package Description
CD4051BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
CD4051BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4051BCMTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
CD4051BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
CD4052BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
CD4052BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4052BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
CD4053BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
CD4053BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4053BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Page 2
www.fairchildsemi.com 2
CD4051BC • CD4052BC • CD4053BC
Connection Diagrams
Pin Assignments for DIP and SOIC
CD4051BC CD4052BC
CD4053BC
Truth Table
*Don’t Care condition.
INPUT STATES “ON” CHANNELS
INHIBIT C B A CD4051B CD4052B CD4053B
0 0 0 0 0 0X, 0Y cx, bx, ax
0 0 0 1 1 1X, 1Y cx, bx, ay
0 0 1 0 2 2X, 2Y cx, by, ax
0 0 1 1 3 3X, 3Y cx, by, ay
0 1 0 0 4 cy, bx, ax
0 1 0 1 5 cy, bx, ay
01106 cy, by, ax
01117 cy, by, ay
1 * * * NONE NONE NONE
Page 3
3 www.fairchildsemi.com
CD4051BC • CD4052BC • CD4053BC
Logic Diagrams
CD4051BC
CD4052BC
Page 4
www.fairchildsemi.com 4
CD4051BC • CD4052BC • CD4053BC
Logic Diagrams (Continued)
CD4053BC
Page 5
5 www.fairchildsemi.com
CD4051BC • CD4052BC • CD4053BC
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: “Absolute Maximum Ratings” are those values bey ond which the
safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devic es should be operated at these limits. Th e Electrical Characteri stic s tables provide condit ions
for actual device operation.
DC Electrical Characteristics (Note 2)
DC Supply Voltage (V
DD
) −0.5 VDC to +18 V
DC
Input Voltage (VIN) −0.5 VDC to V
DD
+0.5 V
DC
Storage Temperature
Range (T
S
) −65°C to +150°C
Power Dissipation (P
D
)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (T
L
)
(soldering, 10 seconds) 260
°C
DC Supply Voltage (V
DD
) +5 VDC to +15 V
DC
Input Voltage (VIN) 0V to VDD V
DC
Operating Temperature Range (TA)
CD4051BC/CD4052BC/CD4053BC
−40°C to +85°C
Symbol Parameter Conditions
−40°C +25°+85°C
Units
Min Max Min Typ Max Min Max
Control A, B, C and Inhibit
I
IN
Input Current V
DD
= 15V, V
EE
= 0V
−0.1 −10
−5
−0.1
−1.0 µA
V
IN
= 0V
V
DD
= 15V, V
EE
= 0V
0.1 10
−5
0.1 1.0 µA
V
IN
= 15V
I
DD
Quiescent Device Current V
DD
= 5V 20 20 150 µA
V
DD
= 10V 40 40 300 µA
V
DD
= 15V 80 80 600 µA
Signal Inputs (VIS) and Outputs (VOS)
R
ON
“ON” Resistance (Peak RL = 10 kΩ V
DD
= 2.5V,
850 270 1050 1200 Ω
for V
EE
≤ V
IS
≤ VDD) (any channel V
EE
= −2.5V
selected) or V
DD
= 5V,
V
EE
= 0V
V
DD
= 5V,
330 120 400 520 Ω
V
EE
= −5V
or V
DD
= 10V,
V
EE
= 0V
V
DD
= 7.5V,
210 80 240 300 Ω
V
EE
= −7.5V
or V
DD
= 15V,
V
EE
= 0V
∆R
ON
∆ “ON” Resistance RL = 10 kΩ V
DD
= 2.5V,
10 Ω
Between Any Two (any channel V
EE
= −2.5V
Channels selected) or V
DD
= 5V,
V
EE
= 0V
V
DD
= 5V
10 Ω
V
EE
= −5V
or V
DD
= 10V,
V
EE
= 0V
V
DD
= 7.5V,
5 Ω
V
EE
= −7.5V
or V
DD
= 15V,
V
EE
= 0V
“OFF” Channel Leakage VDD=7.5V, VEE=−7.5V
Current, any channel “OFF” O/I=±7.5V, I/O=0V ±50 ±0.01 ±50 ±500 nA
“OFF” Channel Leakage Inhibit = 7.5V CD4051 ±200 ±0.08 ±200 ±2000 nA
Current, all channels V
DD
= 7.5V,
“OFF” (Common V
EE
= −7.5V, D4052 ±200 ±0.04 ±200 ±2000 nA
OUT/IN) O/I = 0V
I/O = ±7.5V CD4053 ±200 ±0.02 ±200 ±2000 nA
Control Inputs A, B, C and Inhibit
Page 6
www.fairchildsemi.com 6
CD4051BC • CD4052BC • CD4053BC
DC Electrical Characteristics (Continued)
Note 2: All voltages measured with respect to VSS unless otherw ise specifie d.
Symbol Parameter Conditions
−40°C +25°+85°C
Units
Min Max Min Typ Max Min Max
V
IL
LOW Level Input Voltage V
EE
= VSS RL = 1 kΩ to V
SS
IIS<2 µA on all OFF Channels
V
IS
= VDD thru 1 kΩ
V
DD
= 5V 1.5 1.5 1.5 V
V
DD
= 10V 3.0 3.0 3.0 V
V
DD
= 15V 4.0 4.0 4.0 V
V
IH
HIGH Level Input Voltage V
DD
= 5 3.5 3.5 3.5 V
V
DD
= 10 7 7 7 V
V
DD
= 15 11 11 11 V
I
IN
Input Current V
DD
= 15V, V
EE
= 0V
−0.1 −10
−5
−0.1 −1.0 µA
V
IN
= 0V
V
DD
= 15V, V
EE
= 0V
0.1 10
−5
0.1 1.0 µA
VIN = 15V
Page 7
7 www.fairchildsemi.com
CD4051BC • CD4052BC • CD4053BC
AC Electrical Characteristics (Note 3)
T
A
= 25°C, tr = t
f
= 20 ns, unless otherwise specified.
Note 3: AC Parameters are guar ant eed by DC correlated te s tin g.
Note 4: A, B are two arbitrary channels with A turned “ON” and B “OFF”.
Symbol Parameter Conditions V
DD
Min Typ Max Units
t
PZH,
Propagation Delay Time from V
EE
= V
SS
= 0V 5V 600 1200 ns
t
PZL
Inhibit to Signal Output RL = 1 kΩ 10V 225 450 ns
(channel turning on) C
L
= 50 pF 15V 160 320 ns
t
PHZ,
Propagation Delay Time from V
EE
= V
SS
= 0V 5V 210 420 ns
t
PLZ
Inhibit to Signal Output RL = 1 kΩ 10V 100 200 ns
(channel turning off) C
L
= 50 pF 15V 75 150 ns
C
IN
Input Capacitance
Control input 57.5pF
Signal Input (IN/OUT) 10 15 pF
C
OUT
Output Capacitance
(common OUT/IN)
CD4051 10V 30 pF
CD4052 V
EE
= V
SS
= 0V 10V 15 pF
CD4053 10V 8 pF
C
IOS
Feedthrough Capacitance 0.2 pF
C
PD
Power Dissipation Capacitance
CD4051 110 pF
CD4052 140 pF
CD4053 70 pF
Signal Inputs (VIS) and Outputs (VOS)
Sine Wave Response R
L
= 10 kΩ
(Distortion) f
IS
= 1 kHz 10V 0.04 %
V
IS
= 5 V
p-p
V
EE
= V
SI
= 0V
Frequency Response, Channel R
L
= 1 kΩ, V
EE
= 0V, V
IS
= 5V
p-p
, 10V 40 MHz
“ON” (Sine Wave Input) 20 log10 VOS/V
IS
= −3 dB
Feedthrough, Channel “OFF” R
L
= 1 kΩ, V
EE
= V
SS
= 0V, V
IS
= 5V
p-p
, 10V 10 MHz
20 log
10 VOS/VIS
= −40 dB
Crosstalk Between Any Two R
L
= 1 kΩ, V
EE
= VSS = 0V, VIS(A) = 5V
p-p
10V 3 MHz
Channels (frequency at 40 dB) 20 log10 VOS(B)/VIS(A) = −40 dB (Note 4)
t
PHL
Propagation Delay Signal V
EE
= V
SS
= 0V 5V 25 55 ns
t
PLH
Input to Signal Output CL = 50 pF 10V 15 35 ns
15V 10 25 ns
Control Inputs, A, B, C and Inhibit
Control Input to Signal V
EE
= V
SS
= 0V, RL = 10 kΩ at both ends
Crosstalk of channel. 10V 65 mV (peak)
Input Square Wave Amplitude = 10V
t
PHL,
Propagation Delay Time from V
EE
= V
SS
= 0V 5V 500 1000 ns
t
PLH
Address to Signal Output CL = 50 pF 10V 180 360 ns
(channels “ON” or “OFF”) 15V 120 240 ns
Page 8
www.fairchildsemi.com 8
CD4051BC • CD4052BC • CD4053BC
Special Considerations
In certain applications the external load-resistor current
may include both V
DD
and signal-line components. To
avoid drawing V
DD
current when switch current f lows into
IN/OUT pin, the voltage drop across the bidirectional
switch must not exceed 0.6V at T
A
≤ 25°C, or 0.4V at
T
A
> 25°C (calculated from R
ON
values shown). No V
DD
current will flow through RL if the switch current flows into
OUT/IN pin.
Typical Performance Characteristics
“ON” Resistance vs Signal
Voltage for T
A
= 25°C
“ON” Resistance as a
Function of Temperature for
V
DD
− V
EE
= 15V
“ON” Resistance as a
Function of Temperature for
V
DD
− V
EE
= 10V
“ON” Resistance as a
Function of Temperature for
V
DD
− V
EE
= 5V
Page 9
9 www.fairchildsemi.com
CD4051BC • CD4052BC • CD4053BC
Switching Time Waveforms
Page 10
www.fairchildsemi.com 10
CD4051BC • CD4052BC • CD4053BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
Page 11
11 www.fairchildsemi.com
CD4051BC • CD4052BC • CD4053BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
Page 12
www.fairchildsemi.com 12
CD4051BC • CD4052BC • CD4053BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Page 13
13 www.fairchildsemi.com
CD4051BC • CD4052BC • CD4053BC Singl e 8-Channel Analog Mul tiplexer/Demultiplexe r • Dual 4-Channel Anal og
Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re asonably expected to result in a significant injury to the
user.
2. A critical componen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be reasonably expected to cause the failure of the l ife support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Loading...