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October 1987
Revised January 1999
CD4046BC Micropower Phase-Locked Loop
© 1999 Fairchild Semiconductor Corporation DS005968.prf www.fairchildsemi.com
CD4046BC
Micropower Phase-Locke d Loop
General Description
The CD4046BC microp ower phase-lo cked loop (PLL) consists of a low power, linear, voltage-controlled oscillator
(VCO), a source follower, a zener diode, and t wo phase
comparators. The two phase compara tors have a comm on
signal input and a common comparator input. The signal
input can be directly coup led for a large voltage signal, or
capacitively coupled to the self- biasing a mplif ier at t he si gnal input for a small voltage signal.
Phase comparator I, an exclusive OR gate, provides a digital error signal (phase comp. I Out) and maintains 90°
phase shifts at the VCO ce nter frequency. Between signal
input and comparator input (both at 50% duty cycle), it may
lock onto the signal input fr eq uen cies t hat are close to harmonics of the VCO center frequency.
Phase comparator II is an ed ge-controlled digi tal memory
network. It provides a di gital error signal (phas e comp. II
Out) and lock-in signal (phase pulses) to indica te a locked
condition and maintains a 0° phase shift between signal
input and comparator input.
The linear voltage-con trolled oscillator (VCO) produces an
output signal (VCO Out) whose frequency is determined by
the voltage at the VCO
IN
input, and the capacitor and resis-
tors connected to pin C1
A
, C1B, R1 and R2.
The source follower output of the VCO
IN
(demodulator Out)
is used with an external resistor of 10 kΩ or more.
The INHIBIT input, when high, disables the VCO and
source follower to minimize standby power consumption .
The zener diode is provided for power supply regul ation, if
necessary.
Features
■ Wide supply voltage range: 3.0V to 18V
■ Low dynamic power consu mption: 70 µW (typ.) at f
o
=
10 kHz, V
DD
= 5V
■ VCO frequency: 1.3 MHz (typ.) at V
DD
= 10V
■ Low frequency dr ift: 0.06%/°C at V
DD
= 10V with tem-
perature
■ High VCO linearity: 1% (typ.)
Applications
• FM demodulator and modulator
• Frequency synthesis and multiplication
• Frequency discrimination
• Data synchronization and conditioning
• Voltage-to-frequency conversion
• Tone decoding
• FSK modulation
• Motor speed control
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for SOIC and DIP
Top View
Order Number Package Number Package Description
CD4046BCM M16A 16-Lead Small Outline integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CD4046BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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CD4046BC
Block Diagram
FIGURE 1.
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CD4046BC
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
(Note 2)
Note 1: “Absolute Maximum Rat ings” are tho se values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be op erated at these lim its. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device o peration.
Note 2: V
SS
= 0V unless otherw is e s pecified.
DC Electrical Characteristics (Note 2)
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: I
OH
and IOL are tested one output at a ti m e.
DC Supply Voltage (VDD) −0.5 to +18 V
DC
Input Voltage (VIN) −0.5 to VDD +0.5 V
DC
Storage Temperature Range (TS) −65°C to +150°C
Power Dissipation (P
D
)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (T
L
)
(Soldering , 10 seconds) 260°C
DC Supply Voltage (V
DD
) 3 to 15 V
DC
Input Voltage (VIN) 0 to VDD V
DC
Operating Temperature Range (TA) −40°C to +85°C
Symbol Parameter Conditions
−40°C +25°C +85°C
Units
Min Max Min Typ Max Min Max
I
DD
Quiescent Device Current Pin 5 = V
DD,
Pin 14 = V
DD,
Pin 3, 9 = V
SS
VDD = 5V 20 0.005 20 150 µA
VDD = 10V 40 0.01 40 300 µA
VDD = 15V 80 0.015 80 600 µA
Pin 5 = VDD, Pin 14 = Open,
Pin 3, 9 = V
SS
VDD = 5V 70 5 55 205 µA
VDD = 10V 530 20 410 710 µA
VDD = 15V 1500 50 1200 1800 µA
V
OL
LOW Level Output Voltage VDD = 5V 0.05 0 0.05 0.05 V
VDD = 10V 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V
V
OH
HIGH Level Output Voltage VDD = 5V 4.95 4.95 5 4.95 V
VDD = 10V 9.95 9.95 10 9.95 V
VDD = 15V 14.95 14.95 15 14.95 V
V
IL
LOW Level Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 V
Comparator and Signal In VDD = 10V, VO = 1V or 9V 3.0 4.5 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 6.25 4.0 4.0 V
V
IH
HIGH Level Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 V
Comparator and Signal In VDD = 10V, VO = 1V or 9V 7.0 7.0 5.5 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0 V
I
OL
LOW Level Output Current VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
(Note 4) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA
VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
I
OH
HIGH Level Output Current VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
(Note 4) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA
VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA
I
IN
Input Current All Inputs Except Signal Input
VDD = 15V, VIN = 0V −0.3 −10−5−0.3 −1.0 µA
VDD = 15V, VIN = 15V 0.3 10−50.3 1.0 µA
C
IN
Input Capacitance Any Input (Note 3) 7.5 pF
P
T
Total Power Dissipation fo = 10 kHz, R1 = 1 MΩ,
R2 = ∞, ςΧΟΙΝ = ς∆∆/2
VDD = 5V 0.07 mW
VDD = 10V 0.6 mW
VDD = 15V 2.4 mW
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CD4046BC
AC Electrical Charac teristics (Note 5)
TA = 25°C, CL = 50 pF
Symbol Parameter Conditions Min Typ Max Units
VCO SECTION
I
DD
Operating Current fo = 10 kHz, R1 = 1 MΩ,
R2 = ∞, ςΧΟΙΝ = ς∆∆/2
VDD = 5V 20 µA
VDD = 10V 90 µA
VDD = 15V 200 µA
f
MAX
Maximum Operating Frequency C1 = 50 pF, R1 = 10 kΩ,
R2 = ∞, ςΧΟΙΝ = ς
∆∆
VDD = 5V 0.4 0.8 MHz
VDD = 10V 0.6 1.2 MHz
VDD = 15V 1.0 1.6 MHz
Linearity VCOIN = 2.5V ±0.3V,
R1 ≥ 10 kΩ, VDD = 5V 1 %
VCOIN = 5V ±2.5V,
R1 ≥ 400 kΩ, VDD = 10V 1 %
VCOIN = 7.5V ±5V,
R1 ≥ 1 MΩ, VDD = 15V 1 %
Temperature-Frequency Stability %/°C∝1/φ. ς
∆∆
No Frequency Offset, f
MIN
= 0R2 = ∞
VDD = 5V 0.12–0.24 %/°C
VDD = 10V 0.04–0.08 %/°C
VDD = 15V 0.015–0.03 %/°C
Frequency Offset, f
MIN
≠ 0 VDD = 5V 0.06–0.12 %/°C
VDD = 10V 0.05–0.1 %/°C
VDD = 15V 0.03–0.06 %/°C
VCO
IN
Input Resistance VDD = 5V 10
6
MΩ
VDD = 10V 10
6
MΩ
VDD = 15V 10
6
MΩ
VCO Output Duty Cycle VDD = 5V 50 %
VDD = 10V 50 %
VDD = 15V 50 %
t
THL
VCO Output Transition Time VDD = 5V 90 200 ns
t
THL
VDD = 10V 50 100 ns
VDD = 15V 45 80 ns
PHASE COMPARATORS SECTION
R
IN
Input Resistance
Signal Input VDD = 5V 1 3 MΩ
VDD = 10V 0.2 0.7 MΩ
VDD = 15V 0.1 0.3 MΩ
Comparator Input VDD = 5V 10
6
MΩ
VDD = 10V 10
6
MΩ
VDD = 15V 10
6
MΩ
AC-Coupled Signal Input Voltage
Sensitivity
C
SERIES
= 1000 pF
f = 50 kHz
VDD = 5V 200 400 mV
VDD = 10V 400 800 mV
VDD = 15V 700 1400 mV
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CD4046BC
AC Electrical Characteristics (Continued)
Note 5: AC Parameters are guaranteed by DC correlated testin g.
Phase Comparator State Diagrams
FIGURE 2.
Symbol Parameter Conditions Min Typ Max Units
DEMODULATOR OUTPUT
VCOIN−
V
DEM
Offset Voltage RS ≥ 10 kΩ, VDD = 5V 1.50 2.2 V
RS ≥ 10 kΩ, VDD = 10V 1.50 2.2 V
RS ≥ 50 kΩ, VDD = 15V 1.50 2.2 V
Linearity RS ≥ 50 kΩ
VCOIN = 2.5V ±0.3V, VDD = 5V 0.1 %
VCOIN = 5V ±2.5V, VDD = 10V 0.6 %
VCOIN = 7.5V ±5V, VDD = 15V 0.8 %
ZENER DIODE
V
Z
Zener Diode Voltage IZ = 50 µA 6.3 7.0 7.7 V
R
Z
Zener Dynamic Resistance IZ = 1 mA 100 Ω
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CD4046BC
Typical Waveforms
FIGURE 3. Typical Waveform Employing Phase Comparator I in Locked Condition
FIGURE 4. Typical Waveform Employing Phase Comparator II in Locked Condition
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CD4046BC
Typical Performance Characteristics
Typical Center Frequency vs C1
for R1 = 10 kΩ, 100 kΩ and 1 MΩ
FIGURE 5.
Typical Frequency vs C1
for R2 = 10 kΩ, 100 kΩ and 1 MΩ
FIGURE 6.
Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) = PD (fo) + PD (f
MIN
) + PD (RS); Phase
Comparator II, P
D
(Total) = PD (f
MIN
).
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CD4046BC
Typical f
MAX/fMIN
vs R2/R1
FIGURE 7.
Typical VCO Power Dissipation
at Center Frequency vs R1
FIGURE 8.
Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) = PD (fo) + PD (f
MIN
) + PD (RS); Phase
Comparator II, P
D
(Total) = PD (f
MIN
).
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CD4046BC
Typical VCO Power Dissipation at f
MIN
vs R2
FIGURE 9.
Typical Source Follower Power Dissipation vs R
S
FIGURE 10.
Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) = PD (fo) + PD (f
MIN
) + PD (RS); Phase
Comparator II, P
D
(Total) = PD (f
MIN
).
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CD4046BC
FIGURE 11. Typical VCO Linearity vs R1 and C1
Note: To obtain approximate total power dissipation of PLL system for no-signal input: Phase Comparator I, PD (Total) = PD (fo) + PD (f
MIN
) + PD (RS); Phase
Comparator II, P
D
(Total) = PD (f
MIN
).
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CD4046BC
Design Information
This information is a guid e for approximating the value of
external components for the CD4046B in a phase-lockedloop system. The selected external com ponents must be
within the following ranges: R1, R2 ≥ 10 kΩ, R
S
≥ 10 kΩ,
C1 ≥ 50 pF.
In addition to the given design information, refer to Figure
5, Figure 6, Fig ure 7 for R1, R2 a nd C1 co mponent s elections.
Using Phase Comparator I Using Phase Comparator II
Characteristics V CO Without Offset VCO With Offset VCO Without Offset VCO With Offset
R2 = ∞ R2 = ∞
VCO Frequency
For No Signal Input VCO in PLL system will adjust VCO in PLL system will adjust to
to center frequency, f
o
lowest operating frequency, f
min
Frequency Lock 2 fL = full VCO frequency range
Range, 2 f
L
2 fL = f
max
− f
min
Frequency Capture
Range, 2 f
C
Loop Filter Component
Selection
For 2 f
C
, see Ref. fC = f
L
Phase Angle Between 90° at center frequency (fo), approximating Always 0° in lock
Single and Comparator 0° and 180° at ends of lock range (2 f
L
)
Locks on Harmonics Yes No
of Center Frequency
Signal Input Noise High Low
Rejection
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CD4046BC
References
G.S. Moschytz, “Miniaturized RC Filters Using Phase-Locked Loop”, BSTJ, May, 1965.
Floyd Gardner, “Phaselock Techniques”, John Wiley & Sons, 1966.
Using Phase Comparator I Using Phase Comparator II
Characteristics VCO Without Offset VCO With Offset VCO Without Offset VCO With Offset
R2 = ∞ R2 = ∞
VCO Component
Selection
Given: f
o
.Given: f
o
and fL.Given: f
max
. Given: f
min
and f
max
.
Use f
o
with Calculate f
min
Calculate fo from Use f
min
with
Figure 5 to from the equation the equation Figure 6 to
determine R1 and C1. f
min
= fo − fL. to determine R2 and
C1.
Use f
min
with Figu re 6 to
determine R2 and C1.
Calculate
Use f
o
with Figure 5 to
Calculate determine R1 and C1. Us e
with Figure 7
from the equation to determine ratio
R2/R1 to obtain R1.
Use
with Figure 7
to determine ratio R2/
R1 to obtain R1.
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CD4046BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change sai d circuitry and specifications.
CD4046BC Micropower Phase-Locked Loop
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component in any c omponent of a life suppor t
device or system whose failure to perform can be reasonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
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