Datasheet CD4043BCSJX, CD4043BCSJ, CD4043BCN, CD4043BCMX, CD4043BCM Datasheet (Fairchild Semiconductor)

October 1987
Revised January 1999

CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches

© 1999 Fairchild Semiconductor Corporation DS005967.prf www.fairchildsemi.com

CD4043BC • CD4044BC
Quad 3-STATE NOR R/S Latches •

Quad 3-STATE NAND R/S Latches

General Description

The CD4043BC are quad cross-couple 3-STATE CMOS
NOR latches, and the CD4044BC are quad cross-couple 3­STATE CMOS NAND latches. Each latch has a separate Q
output and individual SET and RESET inputs. There is a
common 3-STATE ENABLE input for all four latches. A

logic “1” on the ENABLE inpu t conne cts the latch sta tes to
the Q outputs. A logic “0” on the ENABLE input discon­nects the latch states from the Q outputs resulting in an
open circuit condition on the Q output. The 3-S TATE fea­ture allows common bussing of the outputs.

Features

■ Wide supply voltage range: 3V to 15V

■ Low power: 100 nW (typ.)

■ High noise immunity: 0.45 V

DD

(typ.)

■ Separate SET and RESET inputs for each latch

■ NOR and NAND configuration

■ 3-ST ATE output with common output enable

Applications

• Multiple bus storage

• Strobed register

• Four bits of independent storage with output enable

• General digital logic

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignments for DIP, SOIC and SOP

CD4043BC

Top View

Pin Assignments for DIP and SOIC

CD4044BC

Top V iew

Order Number Package Number Package Description

CD4043BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CD4043BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD4044BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

CD4044BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

CD4044BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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CD4043BC • CD4044BC

Block Diagrams

CD4043BC CD4044BC

Truth Tables

CD4043BC

CD4044BC

OC = 3-STATE
NC = No change
X = Don’t care

∆ = Dominated by S = 1 input
∆∆ = Dominated by R = 0 input

SREQ

XX0OC
001NC
1011
0110
111∆

SREQ

XX0OC
111NC
0111
1010
001∆∆

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CD4043BC • CD4044BC

Absolute Maximum Ratings(Note 1)

(Note 2)

Recommended Operating
Conditions

(Note 2)

Note 1: “Absolute Maximum Rat ings” are tho se values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be o perated at these limits. The tables of “R ecom­mended Operating Conditions” and “Electrical Characteristics” provide con­ditions for actual device operat ion.

Note 2: V

SS

= 0V unless otherw is e s pecified.

DC Electrical Characteristics (Note 2)

Note 3: IOH and IOL are tested one output at a ti m e.

Supply Voltage (VDD) −0.5V to +18V
Input Voltage (V

IN

) −0.5V to VDD +0.5V

Storage Temperature Range (T

S

) −65°C to +150°C

Power Dissipation (P

D

)
Dual-In-Line 700 mW
Small Outline 500 mW

Lead Temperature (T

L

)
(Soldering, 10 seconds ) 260°C

Supply Voltage (V

DD

) 3.0V to 15V

Input Voltage (V

IN

) 0 to VDD V

Operating Temperature Range (T

A

)

CD4043BC, CD4044BC −40°C to +85°C

Symbol Parameter Conditions

−40°C +25°C +85°C

Units

Min Max Min Typ Max Min Max

I

DD

Quiescent VDD = 5V, VIN = VDD or V

SS

20 0.01 20 150 µA

Device Current VDD = 10V, VIN = VDD or V

SS

40 0.01 40 300 µA

VDD = 15V, VIN = VDD or V

SS

80 0.02 80 600 µA

V

OL

LOW Level |IO| ≤ 1 µA, VIL = 0V, VIH = V

DD

Output Voltage VDD = 5.0V 0.05 0 0.05 0.05 V

VDD = 10V 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V

V

OH

HIGH Level |IO| ≤ 1 µA, VIL = 0V, VIH = V

DD

Output Voltage VDD = 5.0V 4.95 4.95 5.0 4.95 V

VDD = 10V 9.95 9.95 10 9.95 V
VDD = 15V 14.95 14.95 15 14.95 V

V

IL

LOW Level |IO| ≤ 1 µA
Input Voltage VDD = 5.0V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 V

VDD = 10V, VO = 1.0V or 9.0V 3.0 4.5 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0 V

V

IH

HIGH Level |IO| ≤ 1 µA
Input Voltage VDD = 5.0V, VO = 0.5V or 4.5V 3.5 3.5 3.5 V

VDD = 5.0V, VO = 1.0V or 9.0V 7.0 7.0 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11 11 11 V

I

OL

LOW Level VIL = 0V, VIH = V

DD

Output Current VDD = 5.0V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
(Note 3) VDD = 10V, VO = 0.5V 1.3 1.1 2.2 0.9 mA

VDD = 15V, VO = 1.5V 3.6 3.0 6.0 2.4 mA

I

OH

HIGH Level VIL = 0V, VIH = V

DD

Output Current VDD = 5.0V, VO = 4.6V −0.52 −0.44 −0.32 −0.36 mA
(Note 3) VDD = 10V, VO = 9.5V −1.3 −1.1 −0.8 −0.9 mA

VDD = 15V, VO = 13.5V −3.6 −3.0 −2.4 −2.4 mA

I

IN

Input Current VDD = 15V, VIN = 0V −0.3 −0.3 −1.0 µA

VDD = 15V, VIN = 15V 0.3 0.3 1.0 µA

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CD4043BC • CD4044BC

AC Electrical Charac teristics (Note 4)

TA = 25°C, CL = 50 pF, RL = 200k, input tr = tf = 20 ns, unless otherwise noted

Note 4: AC Parameters are guara nt eed by DC correlated testin g.

Timing Waveforms

CD4043B CD4044B

Enable Timing

Symbol Parameter Conditions Min Typ Max Units

t

PLH

, t

PHL

Propagation Delay S or R to Q VDD = 5.0V 175 350 ns

VDD = 10V 75 175 ns
VDD = 15V 60 120 ns

t

PZH

, t

PHZ

Propagation Delay Enable to Q (HIGH) VDD = 5.0V 115 230 ns

VDD = 10V 55 110 ns
VDD = 15V 40 80 ns

t

PZL

, t

PLZ

Propagation Delay Enable to Q (LOW) VDD = 5.0V 100 200 ns

VDD = 10V 50 100 ns
VDD = 15V 40 80 ns

t

THL

, t

TLH

Transition Time VDD = 5.0V 100 200 ns

VDD = 10V 50 100 ns
VDD = 15V 40 80 ns

t

WO

Minimum SET or RESET Pulse Width VDD = 5.0V 80 160 ns

VDD = 10V 40 80 ns
VDD = 15V 20 40 ns

C

IN

Input Capacitance 5.0 7.5 pF

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CD4043BC • CD4044BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or system s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant injury to the
user.

2. A critical component in any c omponent of a life suppor t
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E