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CD4034BCN
Specification
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Datasheet CD4034BCN Specification

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Page 1
February 1988
CD4034BM/CD4034BC 8-Stage TRI-STATEÉBidirectional Parallel/Serial Input/Output Bus Register
The CD4034BM/CD4034BC is an 8-bit CMOS static shift register with two parallel bidirectional data ports (A and B) which, when combined with serial shifting operations, can be used to (1) bidirectionally transfer parallel data between two buses, (2) convert serial data to parallel form and direct them to either of two buses, (3) store (recirculate) parallel data, or (4) accept parallel data from either of two buses and convert them to serial form. These operations are con­trolled by five control inputs:
A ENABLE (AE): ‘‘A’’ data port is enabled only when AE is at logical ‘‘1’’. This allows the use of a common bus for multiple packages.
A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B): This input controls the direction of data flow. When at logical ‘’1’’, data flows from port A to B (A is input, B is output). When at logical ‘‘0’’, the data flow direction is reversed.
ASYNCHRONOUS/SYNCHRONOUS (A/S): When A/S is at logical ‘‘0’’, data transfer occurs at positive tran­sition of the CLOCK. When A/S is at logical ‘‘1’’, data transfer is independent of the CLOCK for parallel opera­tion. In serial mode, A/S input is internally disabled such that operation is always synchronous. (Asynchronous serial operation is not possible.)
PARALLEL/SERIAL (P/S): A logical ‘‘1’’ P/S input al­lows data transfer into the registers via A or B port (syn­chronous if A/S
e
logical ‘‘0’’, asynchronous if A/S logical ‘‘1’’). A logical ‘‘0’’ P/S allows serial data to transfer into the register synchronously with the positive transition of the CLOCK, independent of the A/S input.
CLOCK: Single phase, enabled only in synchronous mode. (Either P/S
e
or P/S
e
logical ‘‘0’’.
logical ‘‘1’’ and A/Selogical ‘‘0’’
All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave.
All inputs are protected against damage due to static dis­charge by diode clamps to V
DD
and VSS.
Features
Y
Wide supply voltage range 3.0V to 18V
Y
High noise immunity 0.45 VDD(typ.)
Y
Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS
Y
RCA CD4034B second source
Applications
Y
Parallel Input/Parallel Output Parallel Input/Serial Output Serial Input/Parallel Output Serial Input/Serial Output register
Y
Shift right/shift left register
Y
Shift right/shift left with parallel loading
Y
Address register
Y
Buffer register
Y
Bus system register with enable parallel lines at bus
e
side
Y
Double bus register system
Y
Up-down Johnson or ring counter
Y
Pseudo-random code generators
Y
Sample and hold register (storage, counting, display)
Y
Frequency and phase comparator
CD4034BM/CD4034BC 8-Stage TRI-STATE Bidirectional
Parallel/Serial Input/Output Bus Register
Connection Diagram
Dual-In-Line Package
Order Number CD4034B
Top View
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5963
TL/F/5963– 1
Page 2
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
DC Supply Voltage (V
DD
)
Input Voltage (VIN)
Storage Temp. Range (TS)
b
b
0.5 VDCto V
0.5 VDCtoa18 V
a
0.5 V
DD
b
65§Ctoa150§C
DC
DC
Recommended Operating Conditions
DC Supply Voltage (VDD)
Input Voltage (VIN)0V
Operating Temperature Range (TA)
CD4034BM CD4034BC
(Note 2)
a
3VDCtoa15 V
to VDDV
DC
b
55§Ctoa125§C
b
40§Ctoa85§C
Power Dissipation (PD)
Dual-In-Line 700 mW Small Outline 500 mW
Lead Temperature (T
(Soldering, 10 seconds) 260
)
L
C
§
DC Electrical Characteristics CD4034BM (Note 2)
b
Symbol Parameter Conditions
55§C
Min Max Min Typ Max Min Max
I
V
V
V
V
I
I
I
I
Quiescent Device Current V
DD
Low Level Output Voltage V
OL
High Level Output Voltage V
OH
Low Level Input Voltage V
IL
High Level Input Voltage V
IH
Low Level Output Current V
OL
(Note 3) V
High Level Output Current V
OH
(Note 3) V
Input Curent V
IN
TRI-STATE Leakage V
OZ
Current V
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.
Note 2: V
Note 3: I
e
0V unless otherwise specified.
SS
and IOLare tested one output at a time.
OH
e
DD
e
V
DD
e
V
DD
e
DD
e
V
DD
e
V
DD
e
DD
e
V
DD
e
V
DD
e
DD
e
V
DD
e
V
DD
e
DD
e
V
DD
e
V
DD
e
DD
e
DD
e
V
DD
e
DD
e
DD
e
V
DD
e
DD
e
V
DD
e
DD
e
DD
e
5V, V 10V, V 15V, V
IN
IN
IN
VDDor V
e
VDDor V
e
VDDor V
SS
SS
SS
5 5 150 mA 10 10 300 mA 20 20 600 mA
5V 0.05 0.05 0.05 V 10V 0.05 0.05 0.05 V 15V 0.05 0.05 0.05 V
5V 4.95 4.95 4.95 V 10V 9.95 9.95 9.95 V 15V 14.95 14.95 14.95 V
e
5V, V 10V, V 15V, V
5V, V 10V, V 15V, V
5V, V 10V, V 15V, V
5V, V 10V, V 15V, V
15V, V 15V, V
15V, V 15V, V
0.5V or 4.5V 1.5 1.5 1.5 V
O
e
1.0V or 9.0V 3.0 3.0 3.0 V
O
e
1.5V or 13.5V 4.0 4.0 4.0 V
O
e
0.5V or 4.5V 3.5 3.5 3.5 V
O
e
1.0V or 9.0V 7.0 7.0 7.0 V
O
e
1.5V or 13.5V 11.0 11.0 11.0 V
O
e
0.4V 0.64 0.51 0.36 mA
O
e
0.5V 1.6 1.3 0.9 mA
O
e
1.5V 4.2 3.4 2.4 mA
O
e
4.6V
O
e
9.5V
O
e
13.5V
O
e
0V
IN
e
15V 0.1 10-50.1 1.0 mA
IN
e
0V
O
e
15V 0.1 10
O
b
0.64
b
1.6
b
4.2
b
0.1
b
0.1
b
0.51
b
1.3
b
3.4
b
0.1b10
b
0.1b10
a
25§C
b
-5
-5
-5
0.1 1.0 mA
a
125§C
0.36 mA
b
0.9 mA
b
2.4 mA
b
1.0 mA
b
1.0 mA
DC
DC
Units
2
Page 3
DC Electrical Characteristics CD4034BC (Note 2)
Symbol Parameter Conditions
I
V
V
V
V
I
I
I
I
Quiescent Device Current V
DD
Low Level Output Voltage V
OL
High Level Output Voltage V
OH
Low Level Input Voltage V
IL
High Level Input Voltage V
IH
Low Level Output Current V
OL
(Note 3) V
High Level Output Current V
OH
(Note 3) V
Input Current V
IN
TRI-STATE Leakage V
OZ
Current V
e
DD
e
V
DD
e
V
DD
e
DD
e
V
DD
e
V
DD
e
DD
e
V
DD
e
V
DD
e
DD
e
V
DD
e
V
DD
e
DD
e
V
DD
e
V
DD
e
DD
e
DD
e
V
DD
e
DD
e
DD
e
V
DD
e
DD
e
V
DD
e
DD
e
DD
e
5V, V 10V, V 15V, V
IN
IN
IN
VDDor V
e
VDDor V
e
VDDor V
5V 0.05 0.05 0.05 V 10V 0.05 0.05 0.05 V 15V 0.05 0.05 0.05 V
5V 4.95 4.95 4.95 V 10V 9.95 9.95 9.95 V 15V 14.95 14.95 14.95 V
e
5V, V 10V, V 15V, V
5V, V 10V, V 15V, V
5V, V 10V, V 15V, V
5V, V
10V, V
15V, V
15V, V 15V, V
15V, V 15V, V
0.5V or 4.5V 1.5 1.5 1.5 V
O
e
1.0V or 9.0V 3.0 3.0 3.0 V
O
e
1.5V or 13.5V 4.0 4.0 4.0 V
O
e
0.5V or 4.5V 3.5 3.5 3.5 V
O
e
1.0V or 9.0V 7.0 7.0 7.0 V
O
e
1.5V or 13.5V 11.0 11.0 11.0 V
O
e
0.4V 0.52 0.44 0.36 mA
O
e
0.5V 1.3 1.1 0.9 mA
O
e
1.5V 3.6 3.0 2.4 mA
O
e
4.6V
O
e
9.5V
O
e
13.5V
O
e
0V
IN
e
15V 0.3 10-50.3 1.0 mA
IN
e
0V
O
e
15V 0.3 10-50.3 1.0 mA
O
b
40§C
a
25§C
Min Max Min Typ Max Min Max
SS
SS
SS
20 20 150 mA 40 40 300 mA 80 80 600 mA
b
0.52
b
1.3
b
3.6
b
0.3
b
0.3
b
0.44
b
1.1
b
3.0
b
0.3b10
b
0.3b10
-5
-5
a
85§C
b
0.36 mA
b
0.9 mA
b
2.4 mA
b
1.0 mA
b
1.0 mA
Units
AC Electrical Characteristics*
e
T
A
25§C, C
L
e
50 pF, R
e
200k, input t
L
e
e
20 ns, unless otherwise specified
t
r
f
Symbol Parameter Conditions Min Typ Max Units
t
PHL,tPLH
t
PHL,tPLH
t
PHZ,tPLZ
t
PZH,tPZL
Propagation Delay Time, A (B) V Synchronous Parallel Data or Serial V Data Input, B (A) Parallel Data V Output
Propagation Delay Time, A (B) V A (B) Asynchronous Parallel Data V Input, B (A) Parallel Data Output V
Propagation Delay Time from A/B V or AE to High Impedance State at A V Outputs or from A/B to High V Impedance State at B Outputs
Propagation Delay Time from A/B V or AE to Logical ‘‘1’’ or Logical ‘‘0’’ V State at A Outputs or from A/B to V Logical ‘‘1’’ or Logical ‘‘0’’ State at
e
5V 280 700 ns
DD
e
10V 120 270 ns
DD
e
15V 85 190 ns
DD
e
5V 280 700 ns
DD
e
10V 120 270 ns
DD
e
15V 85 190 ns
DD
DD
DD
DD
DD
DD
DD
e
e
e
e
e
e
5V, R 10V, R 15V, R
5V, R 10V, R 15V, R
e
1.0 kX 95 220 ns
L
e
1.0 kX 60 130 ns
L
e
1.0 kX 45 100 ns
L
e
1.0 kX 180 480 ns
L
e
1.0 kX 75 190 ns
L
e
1.0 kX 55 140 ns
L
B Outputs
3
Page 4
AC Electrical Characteristics*
e
T
A
25§C, C
L
e
50 pF, R
e
L
200k, input t
e
e
t
20 ns, unless otherwise specified (Continued)
r
f
Symbol Parameter Conditions Min Typ Max Units
t
THL,tTLH
f
CL
tWL,t
t
RCL,tFCL
t
SU
t
SU
t
WH
C
IN
Output Transition Time V
Maximum Clock Input Frequency V
Minimum Clock Pulse Width V
WH
Maximum Clock Rise & Fall Time V
Parallel (A or B) and Serial Data V Setup Time V
Control Inputs AE, A/B, P/S, V A/S Setup Time V
Minimum High Level AE, A/B, P/S, V A/S Pulse Width V
Average Input Capacitance A and B Data I/O and A/B Control 7 15 pF
e
5V 100 200 ns
DD
e
V
10V 50 100 ns
DD
e
V
15V 40 80 ns
DD
e
5V 2 4 MHz
DD
e
V
10V 5 10 MHz
DD
e
V
15V 7 14 MHz
DD
e
5V 125 250 ns
DD
e
V
10V 50 100 ns
DD
e
V
15V 35 70 ns
DD
e
5V 15 ms
DD
e
V
10V 15 ms
DD
e
V
15V 15 ms
DD
e
5V 25 70 ns
DD
e
10V 10 30 ns
DD
e
V
15V 7 20 ns
DD
e
5V 110 280 ns
DD
e
10V 35 100 ns
DD
e
V
15V 60 60 ns
DD
e
5V 160 400 ns
DD
e
10V 70 160 ns
DD
e
V
15V 40 90 ns
DD
Input Any Other Input 5 7.5 pF
C
PD
*AC Parameters are guaranteed by DC correlated testing.
Note 4: C AN-90.
Power Dissipation Capacitance (Note 4) 155 pF
determines the no-load power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note,
PD
Logic Diagram
TL/F/5963– 2
4
Page 5
Schematic Diagram
TL/F/5963– 3
5
Page 6
Switching Time Waveforms and Test Circuits
Synchronous Operation
TL/F/5963– 4
TL/F/5963– 7
tr,CLetf,CLe20 ns
TL/F/5963– 5
Asynchronous Operation
TL/F/5963– 6
TL/F/5963– 8
TL/F/5963– 9
TL/F/5963– 10
6
Page 7
Applications
16-Bit Parallel In/Parallel Out, Parallel In/Serial Out,
Serial In/Parallel Out, Serial In/Serial Out Register
TL/F/5963– 11
7
Page 8
Applications (Continued)
16-Bit Serial In/Gated Parallel Out Register
TL/F/5963– 12
Frequency and Phase Comparator
*When f
e
f2,tWis proportional to the phase of f1with respect to f2.
1
TL/F/5963– 13
TL/F/5963– 14
8
Page 9
Applications (Continued)
Shift Right/Shift Left with Parallel Inputs
Shift left input must be disabled during parallel entry.
A ‘‘High’’ (‘‘Low’’) on the Shift Left/Shift Right input allows serial data on the Shift Left Input (Shift Right Input) to enter the register on the positive transition of the clock signal. A ‘‘high’’ on the ‘‘A’’ Enable Input disables the ‘‘A’’ parallel data lines on Registers 1 and 2 and enables the ‘‘A’’ data
TL/F/5963– 15
lines on Registers 3 and 4 and allows parallel data into Reg­isters 1 and 2. Other logic schemes may be used in place of registers 3 and 4 for parallel loading.
When parallel inputs are not used Registers 3 and 4 and associated logic are not required.
9
Page 10
Truth Table
‘‘A’’ Enable P/S A/B A/S Mode Operation*
0 0 0 X Serial Synchronous Serial data input, A- and B-Parallel data outputs disabled.
0 0 1 X Serial Synchronous Serial data input, B-Parallel data output.
0 1 0 0 Parallel B Synchronous Parallel data inputs, A-Parallel data outputs disabled.
0 1 0 1 Parallel B Asynchronous Parallel data inputs, A-Parallel data outputs disabled.
0 1 1 0 Parallel A-Parallel data inputs disabled, B-Parallel data outputs, synchronous data recirculation.
0 1 1 1 Parallel A-Parallel data inputs disabled, B-Parallel data outputs, asynchronous data recirculation.
1 0 0 X Serial Synchronous Serial data input, A-Parallel data output.
1 0 1 X Serial Synchronous Serial data input, B-Parallel data output.
1 1 0 0 Parallel B Synchronous Parallel data input, A-Parallel data output.
1 1 0 1 Parallel B Asynchronous Parallel data input, A-Parallel data output.
1 1 1 0 Parallel A Synchronous Parallel data input, B-Parallel data output.
1 1 1 1 Parallel A Asynchronous Parallel data input, B-Parallel data output.
XeDon’t Care
*For synchronous operation (serial mode or when A/S
e
0 in parallel mode), outputs change state at positive transition of the clock.
10
Page 11
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4034BMJ or CD4034BCJ
NS Package Number J24A
11
Page 12
Physical Dimensions inches (millimeters) (Continued)
Parallel/Serial Input/Output Bus Register
Molded Dual-In-Line Package (N)
Order Number CD4034BMN or CD4034BCN
NS Package Number N24A
CD4034BM/CD4034BC 8-Stage TRI-STATE Bidirectional
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user.
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1111 West Bardin Road Fax: ( Arlington, TX 76017 Email: cnjwge@tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: ( Fax: 1(800) 737-7018 English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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a
49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
a
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