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October 1987
Revised January 1999
CD4028BC BCD-to-Decimal Decoder
© 1999 Fairchild Semiconductor Corporation DS005959.prf www.fairchildsemi.com
CD4028BC
BCD-to-Decimal Decoder
General Description
The CD4028BC is a BCD-to-decimal or binary-to-octal
decoder consisting of 4 in puts, decoding logic gates, and
10 output buffers. A BCD code applied to the 4 inputs, A, B,
C, and D, results in a high level at the selected 1-of-10 decimal decoded outputs. Similarly, a 3-bit binary code applied
to inputs A, B, and C i s deco ded in octal a t o utputs 0–7. A
high level signal at the D input inhibits octal decoding and
causes outputs 0–7 to go LOW.
All inputs are protected against static discharge damage by
diode clamps to V
DD
and VSS.
Features
■ Wide supply voltage range: 3.0V to 15V
■ High noise immunity: 0.45 V
DD
(typ.)
■ Low power TTL compatibility: fan out of 2 driving 74L
or 1 driving 74LS
■ Low power
■ Glitch free outputs
■ “Positive logic” on inputs and outputs
Applications
• Code conversion
• Address decoding
• Indicator-tube decoder
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Order Number Package Number Package Description
CD4028BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CD4028BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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CD4028BC
Truth Table
Logic Diagram
DCBA0123456789
00001000000000
00010100000000
00100010000000
00110001000000
01000000100000 BCD States
01010000010000
01100000001000
1 = HIGH Level01110000000100
0 = LOW Level 10000000000010
10010000000001
10100000000010
10110000000001
11000000000010 Extraordinary States
11010000000001
11100000000010
11110000000001
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CD4028BC
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
(Note 2)
Note 1: “Absolute Maximum Rat ings” are tho se values beyond which the
safety of the device cannot be guaranteed, they are not meant to imply that
the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device o peration.
Note 2: V
SS
= 0V unless otherw is e s pecified.
DC Electrical Characteristics (Note 2)
Note 3: IOL and IOH are tested one output at a ti m e.
Supply Voltage (VDD) −0.5 to +18V
Input Voltage (V
IN
) −0.5 to VDD +0.5V
Storage Temperature Range (T
S
) −65°C to +150°C
Power Dissipation (P
D
)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (T
L
)
(Soldering, 10 seconds ) 260°C
Supply Voltage (V
DD
) 3 to 15V
Input Voltage (V
IN
) 0 to VDDV
Operating Temperature Range (T
A
) −40°C to +85°C
Symbol Parameter Conditions
−40°C +25°C +85°C
Units
Min Max Min Typ Max Min Max
I
DD
Quiescent Device Current VDD = 5V, VIN = VDD or V
SS
20 0.01 20 150 µA
VDD = 10V, VIN = VDD or V
SS
40 0.01 40 300 µA
VDD = 15V, VIN = VDD or V
SS
80 0.02 80 600 µA
V
OL
LOW Level Output Voltage |IO| < 1 µA, VIL = 0V, VIH = V
DD
VDD = 5V 0.05 0 0.05 0.05 V
VDD = 10V 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V
V
OH
HIGH Level Output Voltage |IO| < 1 µA, VIL = 0V, VIH = V
DD
VDD = 5V 4.95 4.95 5 4.95 V
VDD = 10V 9.95 9.95 10 9.95 V
VDD = 15V 14.95 14.95 15 14.95 V
V
IL
LOW Level Input Voltage |IO| < 1 µA
VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 V
VDD = 10V, VO = 1V or 9V 3.0 4.5 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0 V
V
IH
HIGH Level Input Voltage |IO| < 1 µA
VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 V
VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 V
I
OL
LOW Level Output Current VIH = VDD, VIL = 0V
(Note 3) VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
VDD = 10V, VO = 0.5V 1.3 1.1 2.2 0.9 mA
VDD = 15V, VO = 1.5V 3.6 3.0 6.0 2.4 mA
I
OH
HIGH Level Output Current VIH = VDD, VIL = 0V
(Note 3) VDD = 5V, VO = 4.6V −0.2 −0.16 −0.32 −0.12 mA
VDD = 10V, VO = 9.5V −0.5 −0.4 −0.8 −0.3 mA
VDD = 15V, VO = 13.5V −1.4 −1.2 −3.5 −1.0 mA
I
IN
Input Current VDD = 15V, VIN = 0V −0.3 −0.3 −1.0 µA
VDD = 15V, VIN = 15V 0.3 0.3 1.0 µA
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CD4028BC
AC Electrical Charac teristics (Note 4)
T
A
= 25°C, CL = 50 pF, RL = 200k, Input tr = t
f
= 20 ns, unless otherwise specified
Note 4: AC Parameters are guara nt eed by DC correlated testing.
Switching Time Waveforms
Symbol Parameter Conditions Min Typ Max Units
t
PHL
or t
PLH
Propagation Delay Time VCC = 5V 240 480 ns
VCC = 10V 100 200 ns
VCC = 15V 70 140 ns
t
THL
or t
TLH
Transition Time VCC = 5V 175 350 ns
VCC = 10V 75 150 ns
VCC = 15V 60 110 ns
C
IN
Input Capacitance Any Input 5 7.5 pF
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CD4028BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ri ght at any time without notice to change said circuitry and specifications.
CD4028BC BCD-to-Decimal Decoder
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component in any c omponent of a life suppor t
device or system whose failure to perform can be reasonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
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