CD4020BMS, CD4024BMS, and CD4040BMS are ripplecarry binary counters. All counter stages are master-slave
flip-flops. The state of a counter advances one count on the
negative transition of each input pulse; a high level on the
RESET line resets the counter to its all zeros state. Schmitt
trigger action on the input-pulse line permits unlimited rise
and fall times. All inputs and outputs are buffered.
The CD4020BMS, CD4024BMS and the CD4040BMS is
supplied in these 14 lead outline packages:
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
UNITSMINMAX
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETERSYMBOLCONDITIONSNOTESTEMPERATURE
UNITSMINMAX
Supply CurrentIDDVDD = 20V, VIN = VDD or GND1, 4+25oC-25µA
N Threshold VoltageVNTHVDD = 10V, ISS = -10µA1, 4+25oC-2.8-0.2V
N Threshold Voltage
∆VTNDVDD = 10V, ISS = -10µA1, 4+25oC-±1V
Delta
P Threshold VoltageVTPVSS = 0V, IDD = 10µA1, 4+25oC0.22.8V
P Threshold Voltage
∆VTPDVSS = 0V, IDD = 10µA1, 4+25oC-±1V
Delta
FunctionalFVDD = 18V, VIN = VDD or GND1+25oCVOH >
VDD/2
Propagation Delay TimeTPHL
VDD = 3V, VIN = VDD or GND
VDD = 5V1, 2, 3, 4+25oC-1.35 x
TPLH
VOL <
VDD/2
ns
+25oC
Limit
7-362
V
Page 5
Specifications CD4020BMS, CD4024BMS, CD4040BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETERSYMBOLCONDITIONSNOTESTEMPERATURE
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETERSYMBOLDELTA LIMIT
Supply Current - MSI-2IDD± 1.0µA
Output Current (Sink)IOL5± 20% x Pre-Test Reading
Output Current (Source)IOH5A± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
PDA (Note 1)100% 50041, 7, 9, Deltas
Interim Test 3 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
METHODGROUP A SUBGROUPSREAD AND RECORD
3. See Table 2 for +25oC limit.
4. Read and Record
UNITSMINMAX
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
CONFORMANCE GROUPS
Group E Subgroup 250051, 7, 9Table 41, 9Table 4
FUNCTIONOPENGROUNDVDD9V ± -0.5V
PART NUMBER CD4020BMS
Static Burn-In 1
Note 1
Static Burn-In 2
Note 1
Dynamic Burn-
In Note 1
Irradiation
Note 2
PART NUMBER CD4024BMS
Static Burn-In 1
Note 1
1 - 7, 9, 12 - 158, 10, 1116
1 - 7, 9, 12 - 15810, 11, 16
-8, 11161 - 7, 9, 12 - 1510
1 - 7, 9, 12 - 15810, 11, 16
3 - 6, 8 - 131, 2, 714
METHOD
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
PRE-IRRADPOST-IRRADPRE-IRRADPOST-IRRAD
TESTREAD AND RECORD
OSCILLATOR
50kHz25kHz
7-363
Page 6
Specifications CD4020BMS, CD4024BMS, CD4040BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued)
OSCILLATOR
FUNCTIONOPENGROUNDVDD9V ± -0.5V
Static Burn-In 2
3 - 6, 8 - 1371, 2, 14
Note 1
Dynamic Burn-
8, 10, 132, 7143 - 6, 9, 11, 121
In Note 1
Irradiation
3 - 6, 8 - 1371, 2, 14
Note 2
PART NUMBER CD4040BMS
Static Burn-In 1
1 - 7, 9, 12 - 158, 10, 1116
Note 1
Static Burn-In 2
1 - 7, 9, 12 - 15810, 11, 16
Note 1
Dynamic Burn-
-8, 11161 - 7, 9, 12 - 1510
In Note 1
Irradiation
1 - 7, 9, 12 - 15810, 11, 16
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
50kHz25kHz
Functional Diagrams
VDD
16
INPUT
PULSES
RESET
10
14 STAGE
RIPPLE
COUNTER
11
8
VSS
CD4020BMSCD4024BMSCD4040BMS
9
7
5
4
6
13
12
14
15
1
2
3
Q1
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
1
INPUT
PULSES
2
RESET
12 BUFFERED OUTPUTS
NC = 8, 10, 13
VDD
14
7 STAGE
RIPPLE
COUNTER
7
VSS
VDD
16
10
12
Q1
11
Q2
9
Q3
6
Q4
5
Q5
4
Q6
3
Q7
INPUT
PULSES
7 BUFFERED OUTPUTS
11
RESET
12 STAGE
RIPPLE
COUNTER
8
VSS
Q1
9
7
Q2
6
Q3
5
Q4
3
Q5
2
Q6
4
Q7
13
Q8
Q9
12
14
Q10
15
Q11
1
Q12
12 BUFFERED OUTPUTS
7-364
Page 7
Logic Diagrams
CD4020BMS, CD4024BMS, CD4040BMS
Ø1Q1
Ø*
R
*
VDD
FF1
Ø1RQ1
Q1
Ø2Q2
FF2
Ø2RQ2
Ø3Q13
Ø3Q13
FF3 - FF13
Ø14 Q14
FF14
Ø14RQ14
*INPUTS PROTECTED
BY COS/MOS PROTECTION
NETWORK
Q1
VSS
Q4Q13Q14
FIGURE 1. LOGIC DIAGRAM FOR CD4020BMS
Ø1Q1
Ø*
R
*
VDD
FF1
Ø1RQ1
Q1
Ø2Q2
FF2
Ø2RQ2
Ø3Q6
Ø3Q6
FF3 - FF6
Ø7 Q7
FF14
Ø7RQ7
*INPUTS PROTECTED
BY COS/MOS PROTECTION
NETWORK
Q1
VSS
Q2
Q3Q6
Q7
FIGURE 2. LOGIC DIAGRAM FOR CD4024BMS
Ø1Q1
Ø*
R
*
VDD
FF1
Ø1RQ1
Q1
Ø2Q2
FF2
Ø2RQ2
Ø3Q11
Ø3Q11
FF3 - FF11
Ø7 Q12
FF12
Ø7RQ12
*INPUTS PROTECTED
BY COS/MOS PROTECTION
NETWORK
Q1
VSS
FIGURE 3. LOGIC DIAGRAM FOR CD4040BMS
Q2
Q3Q11
Q12
7-365
Page 8
CD4020BMS, CD4024BMS, CD4040BMS
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
30
25
20
15
10
5
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
051015
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
10V
5V
DRAIN-TO-SOURCE VOLTA GE (VDS) (V)
FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTA GE (VDS) (V)
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10V
AMBIENT TEMPERATURE (TA) = +25oC
15.0
12.5
10.0
7.5
5.0
2.5
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
051015
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
10V
5V
DRAIN-TO-SOURCE VOLTA GE (VDS) (V)
FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
0-5-10-15
0
-5
-10
-15
-20
DRAIN-TO-SOURCE VOLTA GE (VDS) (V)
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10V
0-5-10-15
0
-5
-10
-25
-15V
-30
FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
200
150
100
50
TRANSITION TIME (tTHL, tTLH) (ns)
0
040608010020
SUPPL Y VOLT AGE (VDD) = 5V
10V
15V
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
-15V
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
300
200
(φ TO Q1)
100
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
040608010020
SUPPL Y VOLT AGE (VDD) = 5V
10V
15V
LOAD CAPACITANCE (CL) (pF)
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE (φ TO Q1))
-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
7-366
Page 9
CD4020BMS, CD4024BMS, CD4040BMS
Typical Performance Characteristics (Continued)
5
10
8
AMBIENT TEMPERATURE (TA) = +25oC
6
4
2
SUPPL Y VOLT AGE (VDD) = 5V
4
10
8
6
4
2
3
10
8
6
4
2
2
10
8
6
POWER DISSIPATION (PD) (µW)
4
2
10
11010210
86428642864286428642
INPUT PULSE FREQUENCY (fφ) (kHz)
5V
3
10V
10V
CD = 15pF
CL = 50pF
4
10
5
10
∅
p
n
∅
∅
p
n
∅
ON FIRST STAGE ONLY
*
R
∅
p
n
RR
∅
1
*
Q
Q
∅
p
n
Q
∅
FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF INPUT PULSE FREQUENCY FOR
CD4020BMS
Chip Dimensions and Pad Layouts
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10
FIGURE 11. DETAIL OF TYPICAL FLIP-FLOP STAGES
-3
inch)
DIMENSIONS AND PAD LAYOUT FOR CD4020BMS. DIMEN-
SIONS AND PAD LAYOUT FOR CD4040BMS ARE IDENTICAL
METALLIZATION: Thickness: 11kÅ− 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
DIMENSIONS AND PAD LAYOUT FOR CD4024BMSH
7-367
Page 10
CD4020BMS, CD4024BMS, CD4040BMS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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Intersil Corporation
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368
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