Datasheet CD4040BMS, CD4024BMS, CD4020BMS Datasheet (Intersil Corporation)

Page 1
October 1996
CD4020BMS, CD4024BMS,
CD4040BMS
CMOS Ripple-Carry Binary
Counter/Dividers
Features
• Medium Speed Operation
• Fully Static Operation
• Buffered Inputs and Outputs
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• Common Reset
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µa at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25
o
C
• Noise Margin (Over Full Packa ge Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications For Description Of ‘B’ Series CMOS Devices”
Applications
• Control Counters
• Timers
• Frequency Dividers
• Time-Delay Circuits
Description
CD4020BMS - 14 Stage CD4024BMS - 7 Stage CD4040BMS - 12 Stage
Pinouts
RESET
NC = NO CONNECTION
Q12 Q13 Q14
Q6 Q5 Q7 Q4
VSS
Q7 Q6 Q5 Q4
VSS
1 2 3 4 5 6 7 8
1
θ
2 3 4 5 6 7
CD4020BMS
TOP VIEW
CD4024BMS
TOP VIEW
CD4040BMS
TOP VIEW
16 15 14 13 12 11 10
9
14 13 12 11 10
9 8
VDD Q11 Q10 Q8 Q9 RESET
θ
Q1
VDD NC Q1 Q2 NC Q3 NC
CD4020BMS, CD4024BMS, and CD4040BMS are ripple­carry binary counters. All counter stages are master-slave flip-flops. The state of a counter advances one count on the negative transition of each input pulse; a high level on the RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered.
The CD4020BMS, CD4024BMS and the CD4040BMS is supplied in these 14 lead outline packages:
CD4020B CD4024B CD4040B
Braze Seal DIP Frit Seal DIP Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
H4W H4Q H4X
H1F H1B H1F
H6W H3W H6W
7-359
Q12
Q6 Q5 Q7 Q4 Q3 Q2
VSS
16
1 2 3 4 5 6 7 8
VDD
15
Q11
14
Q10
13
Q8
12
Q9 R
11 10
θ
9
Q1
File Number 3300.1
Page 2
Specifications CD4020BMS, CD4024BMS, CD4040BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +125oC
o
C to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1)
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA
VDD = 18V, VIN = VDD or GND 3 -55
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
VDD = 18V 3 -55oC - 100 nA Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >
VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2) Input Voltage High
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2) Input Voltage Low
(Note 2) Input Voltage High
(Note 2)
VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs
Thermal Resistance . . . . . . . . . . . . . . . . θ
Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55 For TA = +100
o
C
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
o
C to +100oC (Package Type D, F, K) . . . . . . 500mW
o
C to +125oC (Package Type D, F, K). . . . . .Derate
Linearity at 12mW/oC to 200mW
ja
o
C/W 20oC/W
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
GROUP A
LIMITS
SUBGROUPS TEMPERATURE
2 +125oC - 1000 µA
o
C-10µA
o
C -100 - nA
2 +125oC -1000 - nA
2 +125oC - 1000 nA
VOL <
VDD/2
VDD/2
1, 2, 3 +25oC, +125oC, -55oC- 4 V
1, 2, 3 +25oC, +125oC, -55oC11 - V
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
θ
jc
UNITSMIN MAX
V
7-360
Page 3
Specifications CD4020BMS, CD4024BMS, CD4040BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1, 2)
Propagation Delay 0 To Q1
Propagation Delay Qn To Qn + 1
Propagation Delay Reset To Q
Transition Time Q1
Maximum Clock Input Frequency
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
TPHL1 TPLH1
TPHL2 TPLH2
TPLH3 TPHL3
TTHL TTLH
FCL VDD = 5V, VIN = VDD or GND 9 +25oC 3.5 - MHz
VDD = 5V, VIN = VDD or GND 9 +25oC - 360 ns
VDD = 5V, VIN = VDD or GND 9 +25oC - 330 ns
VDD = 5V, VIN = VDD or GND 9 +25oC - 280 ns
VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA
SUBGROUPS TEMPERATURE
10, 11 +125oC, -55oC - 486 ns
10, 11 +125oC, -55oC - 446 ns
10, 11 +125oC, -55oC - 378 ns
10, 11 +125oC, -55oC - 270 ns
10, 11 +125oC, -55oC 2.22 - MHz
+125oC - 150 µA
+125oC - 300 µA
+125oC - 600 µA
-55oC
-55oC
-55oC
-55oC
-55oC 0.64 - mA
-55oC 1.6 - mA
-55oC 4.2 - mA
-55oC - -0.64 mA
-55oC - -2.0 mA
-55oC - -1.6 mA
-55oC - -4.2 mA
LIMITS
UNITSMIN MAX
LIMITS
UNITSMIN MAX
-50mV
-50mV
4.95 - V
9.95 - V
7-361
Page 4
Specifications CD4020BMS, CD4024BMS, CD4040BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
Input Voltage Low VIL VDD = 10V, V OH > 9V, VOL < 1V 1, 2 +25oC, +125oC,
-3V
-55oC
o
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25
Propagation Delay Input To Q1
Propagation Delay QN To QN + 1
Propagation Delay Reset To Q
Transition Time TTHL
Maximum Clock Input Frequency
Minimum Reset Pulse Width
TPHL1 TPLH1
TPHL2 TPLH2
VDD = 10V 1, 2, 3 +25oC - 160 ns VDD = 15V 1, 2, 3 +25oC - 130 ns VDD = 10V 1, 2, 3 +25oC - 80 ns VDD = 15V 1, 2, 3 +25oC - 60 ns
TPHL3 VDD = 10V 1, 2, 3 +25oC - 120 ns
VDD = 15V 1, 2, 3 +25oC - 100 ns VDD = 10V 2, 3 +25
TTLH
VDD = 15V 2, 3 +25
FCL VDD = 10V 1, 2, 3 +25oC 8 - MHz
VDD = 15V 1, 2, 3 +25oC 12 - MHz
TW VDD = 5V 1, 2, 3 +25oC - 200 ns
VDD = 10V 1, 2, 3 +25oC - 80 ns
C, +125oC,
o
-55
C
o
C - 100 ns
o
C - 80 ns
7-V
VDD = 15V 1, 2, 3 +25oC - 60 ns
Reset Removal Time TREM VDD = 5V 1, 2, 3 +25oC - 350 ns
VDD = 10V 1, 2, 3 +25oC - 150 ns VDD = 15V 1, 2, 3 +25oC - 100 ns
Minimum Input Pulse Width
TW VDD = 5V 1, 2, 3 +25oC - 140 ns
VDD = 10V 1, 2, 3 +25oC - 60 ns VDD = 15V 1, 2, 3 +25oC - 40 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
UNITSMIN MAX
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V N Threshold Voltage
VTND VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V
Delta P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage
VTPD VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V
Delta Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >
VDD/2
Propagation Delay Time TPHL
VDD = 3V, VIN = VDD or GND VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x
TPLH
VOL < VDD/2
ns
+25oC
Limit
7-362
V
Page 5
Specifications CD4020BMS, CD4024BMS, CD4040BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER SYMBOL DELTA LIMIT
Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading Output Current (Source) IOH5A ± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
METHOD GROUP A SUBGROUPS READ AND RECORD
3. See Table 2 for +25oC limit.
4. Read and Record
UNITSMIN MAX
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
CONFORMANCE GROUPS
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4
FUNCTION OPEN GROUND VDD 9V ± -0.5V
PART NUMBER CD4020BMS Static Burn-In 1
Note 1 Static Burn-In 2
Note 1 Dynamic Burn-
In Note 1 Irradiation
Note 2 PART NUMBER CD4024BMS Static Burn-In 1
Note 1
1 - 7, 9, 12 - 15 8, 10, 11 16
1 - 7, 9, 12 - 15 8 10, 11, 16
- 8, 11 16 1 - 7, 9, 12 - 15 10
1 - 7, 9, 12 - 15 8 10, 11, 16
3 - 6, 8 - 13 1, 2, 7 14
METHOD
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
TEST READ AND RECORD
OSCILLATOR
50kHz 25kHz
7-363
Page 6
Specifications CD4020BMS, CD4024BMS, CD4040BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS (Continued)
OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V
Static Burn-In 2
3 - 6, 8 - 13 7 1, 2, 14
Note 1 Dynamic Burn-
8, 10, 13 2, 7 14 3 - 6, 9, 11, 12 1
In Note 1 Irradiation
3 - 6, 8 - 13 7 1, 2, 14
Note 2 PART NUMBER CD4040BMS Static Burn-In 1
1 - 7, 9, 12 - 15 8, 10, 11 16
Note 1 Static Burn-In 2
1 - 7, 9, 12 - 15 8 10, 11, 16
Note 1 Dynamic Burn-
- 8, 11 16 1 - 7, 9, 12 - 15 10
In Note 1 Irradiation
1 - 7, 9, 12 - 15 8 10, 11, 16
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V
50kHz 25kHz
Functional Diagrams
VDD
16
INPUT
PULSES
RESET
10
14 STAGE
RIPPLE
COUNTER
11
8
VSS
CD4020BMS CD4024BMS CD4040BMS
9 7 5 4 6 13 12 14 15
1 2 3
Q1 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14
1
INPUT PULSES
2
RESET
12 BUFFERED OUTPUTS
NC = 8, 10, 13
VDD
14
7 STAGE
RIPPLE
COUNTER
7
VSS
VDD
16
10
12
Q1
11
Q2
9
Q3
6
Q4
5
Q5
4
Q6
3
Q7
INPUT
PULSES
7 BUFFERED OUTPUTS
11
RESET
12 STAGE
RIPPLE
COUNTER
8
VSS
Q1
9 7
Q2
6
Q3
5
Q4
3
Q5
2
Q6
4
Q7
13
Q8 Q9
12 14
Q10
15
Q11
1
Q12
12 BUFFERED OUTPUTS
7-364
Page 7
Logic Diagrams
CD4020BMS, CD4024BMS, CD4040BMS
Ø1 Q1
Ø*
R
*
VDD
FF1
Ø1RQ1
Q1
Ø2 Q2
FF2
Ø2RQ2
Ø3 Q13
Ø3 Q13
FF3 - FF13
Ø14 Q14
FF14
Ø14RQ14
*INPUTS PROTECTED
BY COS/MOS PROTECTION NETWORK
Q1
VSS
Q4 Q13 Q14
FIGURE 1. LOGIC DIAGRAM FOR CD4020BMS
Ø1 Q1
Ø*
R
*
VDD
FF1
Ø1RQ1
Q1
Ø2 Q2
FF2
Ø2RQ2
Ø3 Q6
Ø3 Q6
FF3 - FF6
Ø7 Q7
FF14
Ø7RQ7
*INPUTS PROTECTED
BY COS/MOS PROTECTION NETWORK
Q1
VSS
Q2
Q3 Q6
Q7
FIGURE 2. LOGIC DIAGRAM FOR CD4024BMS
Ø1 Q1
Ø*
R
*
VDD
FF1
Ø1RQ1
Q1
Ø2 Q2
FF2
Ø2RQ2
Ø3 Q11
Ø3 Q11
FF3 - FF11
Ø7 Q12
FF12
Ø7RQ12
*INPUTS PROTECTED
BY COS/MOS PROTECTION NETWORK
Q1
VSS
FIGURE 3. LOGIC DIAGRAM FOR CD4040BMS
Q2
Q3 Q11
Q12
7-365
Page 8
CD4020BMS, CD4024BMS, CD4040BMS
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
30
25
20
15
10
5
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
0 5 10 15
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
10V
5V
DRAIN-TO-SOURCE VOLTA GE (VDS) (V)
FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTA GE (VDS) (V)
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10V
AMBIENT TEMPERATURE (TA) = +25oC
15.0
12.5
10.0
7.5
5.0
2.5
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
0 5 10 15
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
10V
5V
DRAIN-TO-SOURCE VOLTA GE (VDS) (V)
FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
0-5-10-15
0
-5
-10
-15
-20
DRAIN-TO-SOURCE VOLTA GE (VDS) (V)
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10V
0-5-10-15
0
-5
-10
-25
-15V
-30
FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
200
150
100
50
TRANSITION TIME (tTHL, tTLH) (ns)
0
0 40 60 80 10020
SUPPL Y VOLT AGE (VDD) = 5V
10V 15V
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
-15V
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
300
200
(φ TO Q1)
100
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
0 40608010020
SUPPL Y VOLT AGE (VDD) = 5V
10V
15V
LOAD CAPACITANCE (CL) (pF)
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE (φ TO Q1))
-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
7-366
Page 9
CD4020BMS, CD4024BMS, CD4040BMS
Typical Performance Characteristics (Continued)
5
10
8
AMBIENT TEMPERATURE (TA) = +25oC
6 4
2
SUPPL Y VOLT AGE (VDD) = 5V
4
10
8 6
4 2
3
10
8 6
4 2
2
10
8 6
POWER DISSIPATION (PD) (µW)
4 2
10
11010210
86428642864286428642
INPUT PULSE FREQUENCY (fφ) (kHz)
5V
3
10V
10V
CD = 15pF CL = 50pF
4
10
5
10
p n
p n
ON FIRST STAGE ONLY
*
R
p n
R R
1
*
Q
Q
p n
Q
FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF INPUT PULSE FREQUENCY FOR CD4020BMS
Chip Dimensions and Pad Layouts
Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10
FIGURE 11. DETAIL OF TYPICAL FLIP-FLOP STAGES
-3
inch)
DIMENSIONS AND PAD LAYOUT FOR CD4020BMS. DIMEN-
SIONS AND PAD LAYOUT FOR CD4040BMS ARE IDENTICAL
METALLIZATION: Thickness: 11kÅ14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
DIMENSIONS AND PAD LAYOUT FOR CD4024BMSH
7-367
Page 10
CD4020BMS, CD4024BMS, CD4040BMS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240
EUROPE
Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05
368
ASIA
Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
File Number
Loading...