Page 1
October 1987
Revised January 1999
CD4024BC 7-Stage Ripple Carry Binary Counter
© 1999 Fairchild Semiconductor Corporation DS005957.prf www.fairchildsemi.com
CD4024BC
7-Stage Ripple Carry Binary Counter
General Description
The CD4024BC is a 7-stage ripple-carry binary counter.
Buffered outputs are externally available from stages 1
through 7. The counter is res et to its logi cal “0” stage by a
logical “1” on th e re set i np ut. T he c oun ter is advanced one
count on the negative transition of each clock pulse.
Features
■ Wide supply voltage range: 3.0V to 15V
■ High noise immunity: 0.45 V
DD
(typ.)
■ Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
■ High speed: 12 MHz (typ.)
input pulse rate V
DD
− VSS = 10V
■ Fully static operation
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Order Number Package Number Package Description
CD4024BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
CD4024BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Page 2
www.fairchildsemi.com 2
CD4024BC
Logic Diagrams
Input Logic
Flip-flop logic (1 of 7 identical stages).
Block Diagram
Page 3
3 www.fairchildsemi.com
CD4024BC
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
(Note 1)
Note 1: “Absolute Maximum Rat ings” are tho se values beyond which the
safety of the device cannot be guaranteed, they are not meant to imply that
the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device o peration.
Note 2: V
SS
= 0V unless otherw is e s pecified.
DC Electrical Characteristics (Note 2)
Note 3: IOH and IOL are tested one output at a ti m e.
DC Supply Voltage (VDD) −0.5 to +18 V
DC
Input Voltage (VIN) −0.5 to VDD +0.5 V
DC
Storage Temperature Range (TS) −65°C to +150°C
Power Dissipation (P
D
)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature
(Soldering, 10 seconds) (T
L
)260°C
DC Supply Voltage (V
DD
) +3 to +15 V
DC
Input Voltage (VIN) 0 to VDD V
DC
Operating Temperature Range (TA) −40°C to +85°C
Symbol Parameter Conditions
−40°C +25°C +85°C
Units
Min Max Min Typ Max Min Max
I
DD
Quiescent Device Current VDD = 5V 20 0.3 20 150 µA
VDD = 10V 40 0.5 40 300 µA
VDD = 15V 60 0.7 80 600 µA
V
OL
LOW Level Output Voltage |lO|<1 µA
VDD = 5V 0.05 0 0.05 0.05 V
VDD = 10V 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V
V
OH
HIGH Level Output Voltage |lO|<1 µA
VDD = 5V 4.95 4.95 5 4.95 V
VDD = 10V 9.95 9.95 10 9.95 V
VDD = 15V 14.95 14.95 15 14.95 V
V
IL
LOW Level Input Voltage |lO|<1 µA
VDD = 5V, VO = 0.5V or 4.5V 1.5 2 1.5 1.5 V
VDD = 10V, VO = 1.0V or 9.0V 3.0 4 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 6 4.0 4.0 V
V
IH
HIGH Level Input Voltage |lO|<1 µA
VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3 3.5 V
VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 6 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 9 11.0 V
I
OL
LOW Level Output Current VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
(Note 3) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA
VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
I
OH
HIGH Level Output Current VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
(Note 3) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA
VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA
I
IN
Input Current VDD = 15V, VIN = 0V −0.30 −10−5−0.30 −1.0 µA
VDD = 15V, VIN = 15V 0.30 10−50.30 1.0 µA
Page 4
www.fairchildsemi.com 4
CD4024BC
AC Electrical Charac teristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200 k, tr and tf = 20 ns unless otherwise specified
Note 4: AC Parameters are guara nt eed by DC correlated testing.
Note 5: Capacitance is guaranteed by periodic testing.
Symbol Parameter Conditions Min Typ Max Units
t
PHL
, t
PLH
Propagation Delay Time VDD = 5V 185 350 ns
to Q1 Output VDD = 10V 85 125 ns
VDD = 15V 70 100 ns
t
THL
, t
TLH
Transition Time VDD = 5V 100 200 ns
VDD = 10V 50 100 ns
VDD = 15V 40 80 ns
tWL, t
WH
Minimum Input Pulse Width VDD = 5V 75 200 ns
VDD = 10V 40 110 ns
VDD = 15V 35 90 ns
t
RCL
, t
FCL
Input Rise and Fall Time VDD = 5V 15 µs
VDD = 10V 10 µs
VDD = 15V 8 µs
f
CL
Maximum Input Pulse Frequency VDD = 5V 1.5 5 MHz
VDD = 10V 4 12 MHz
VDD = 15V 5 15 MHz
t
PHL
Reset Propagation Delay Time VDD = 5V 185 350 ns
VDD = 10V 85 125 ns
VDD = 15V 70 100 ns
t
WH
Reset Minimum Pulse Width VDD = 5V 185 350 ns
VDD = 10V 85 125 ns
VDD = 15V 70 100 ns
C
IN
Input Capacitance (Note 5) Any Input 5 7.5 pF
Page 5
5 www.fairchildsemi.com
CD4024BC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M14A
Page 6
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change sai d circuitry and specifications.
CD4024BC 7-Stage Ripple Carry Binary Counter
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component in any c omponent of a life suppor t
device or system whose failure to perform can be reasonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
Loading...