Datasheet CD4019BMS Datasheet (Intersil Corporation)

CD4019BMS

November 1994

Features

• High Voltage Type (20V Rating)

• Medium Speed Operation tPHL = tPLH = 60ns (typ.) at
CL = 50pF, VDD = 10V

• Standardized Symmetrical Output Characteristics

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”

• Maximum Input Current of 1µa at 18V Over Full Pack­age-Temperature Range;

o

- 100nA at 18V and 25

C

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

Applications

• And/Or Select Gating

• Shift-Right/Shift-Left Registers

• True/Complement Selection

• AND/OR/Exclusive-OR Selection

Description

CD4019BMS types consist of four AND/OR select gate con­figurations, each consisting of two 2-input AND gates driving
a single 2-input OR gate. Selection is accomplished by con­trol bits Ka and Kb. In addition to selection of either channel
A or channel B information, the control bits can be applied
simultaneously to accomplish the logical A + B function.

CMOS Quad AND/OR Select Gate

Pinout

CD4019BMS

TOP VIEW

1

B4

2

A3

3

B3

4

A2

5

B2

6

A1

7

B1

8

VSS

Functional Diagram

Ka Kb

14916

15

A4

1

B4

2

A3

3

B3

4

A2
B2
A1
B1

5
6
7

D4 = (A4 Ka) + (B4 Kb)

16

VDD

15

A4

14

Kb

13

D4 = A4 Ka + B4 Kb

12

D3 = A3 Ka + B3 Kb

11

D2 = A2 Ka + B2 Kb

10

D1 = A1 Ka + B1 Kb

9

Ka

VDD

VSS

13

D4

12

D3

11

D2

10

D1

8

The CD4019BMS is supplied in these 16-lead outline pack­ages:

Braze Seal DIP H4T
Frit Seal DIP H1E
Ceramic Flatpack H3X

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

7-307

File Number

3299

Specifications CD4019BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V

(Voltage Referenced to VSS Terminals)

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

Operating Temperature Range. . . . . . . . . . . . . . . . -55

Package Types D, F, K, H

Storage Temperature Range (TSTG). . . . . . . . . . . -65

o

C to +125oC

o

C to +150oC

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265

At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for

10s Maximum

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS (NOTE 1)

Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-2µA

VDD = 18V, VIN = VDD or GND 3 -55

Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25

VDD = 18V 3 -55oC -100 - nA

Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA

VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >

VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC

Input Voltage Low

VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V

(Note 2)
Input Voltage High

VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V

(Note 2)
Input Voltage Low

(Note 2)
Input Voltage High

(Note 2)

VIL VDD = 15V, VOH > 13.5V,

VOL < 1.5V

VIH VDD = 15V, VOH > 13.5V,

VOL < 1.5V

NOTES: 1. All voltages referenced to device GND, 100% testing being

implemented.

2. Go/No Go test with limits applied to inputs

Thermal Resistance . . . . . . . . . . . . . . . . θ

Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W

Flatpack Package . . . . . . . . . . . . . . . . 70

Maximum Package Power Dissipation (PD) at +125oC

For TA = -55
For TA = +100

o

C

Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW

o

C to +100oC (Package Type D, F, K). . . . . .500mW

o

C to +125oC (Package Type D, F, K) . . . . .Derate

Linearity at 12mW/oC to 200mW

ja

o

C/W 20oC/W

For TA = Full Package Temperature Range (All Package Types)

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

GROUP A

LIMITS

SUBGROUPS TEMPERATURE

2 +125oC - 200 µA

o

C-2µA

o

C -100 - nA

2 +125oC -1000 - nA

2 +125oC - 1000 nA

VOL <

VDD/2

VDD/2

1, 2, 3 +25oC, +125oC, -55oC- 4 V

1, 2, 3 +25oC, +125oC, -55oC11 - V

3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.

θ

jc

UNITSMIN MAX

V

7-308

Specifications CD4019BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A

PARAMETER SYMBOL CONDITIONS (NOTE 1, 2)

Propagation Delay TPHL

TPLH

Transition Time TTHL

TTLH

NOTES:

1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 1 µA

Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,

Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,

Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA

Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA

Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA

Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA

Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA

Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA

Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA

Input Voltage Low VIL VDD = 10V , VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,

Input Voltage High VIH VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,

Propagation Delay TPHL

TPLH

VDD = 5V, VIN = VDD or GND 9 +25oC - 300 ns

VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA

VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 2 µA

VDD = 10V 1, 2, 3 +25oC - 120 ns
VDD = 15V 1, 2, 3 +25oC - 100 ns

SUBGROUPS TEMPERATURE

10, 11 +125oC, -55oC - 405 ns

10, 11 +125oC, -55oC - 270 ns

+125oC-30µA

+125oC-60µA

+125oC - 120 µA

-55oC

-55oC

-55oC

-55oC

-55oC 0.64 - mA

-55oC 1.6 - mA

-55oC 4.2 - mA

-55oC - -0.64 mA

-55oC - -2.0 mA

-55oC - -1.6 mA

-55oC - -4.2 mA

-55oC

-55oC

LIMITS

UNITSMIN MAX

LIMITS

UNITSMIN MAX

-50mV

-50mV

4.95 - V

9.95 - V

-3V

7-V

7-309

Specifications CD4019BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Transition Time TTHL

TTLH

Input Capacitance CIN All A and B Inputs 1, 2 +25oC - 7.5 pF
Input Capacitance CIN KA and KB Inputs 1, 2 +25

NOTES:

1. All voltages referenced to device GND.

2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.

3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage

Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage

Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >

Propagation Delay Time TPHL

NOTES: 1. All voltages referenced to device GND.

2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V

∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V

TPLH

VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns

o

C - 15.0 pF

LIMITS

o

C - 7.5 µA

VOL <
VDD = 3V, VIN = VDD or GND
VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x

3. See Table 2 for +25oC limit.

4. Read and Record

VDD/2

VDD/2

+25oC

Limit

UNITSMIN MAX

UNITSMIN MAX

V

ns

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-1 IDD ± 0.2µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883

CONFORMANCE GROUP

Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas

Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A

PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11

METHOD GROUP A SUBGROUPS READ AND RECORD

7-310

Specifications CD4019BMS

TABLE 6. APPLICABLE SUBGROUPS

(Continued)

MIL-STD-883

CONFORMANCE GROUP

METHOD GROUP A SUBGROUPS READ AND RECORD

Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11

Subgroup B-6 Sample 5005 1, 7, 9

Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

CONFORMANCE GROUPS

MIL-STD-883

METHOD

PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD

Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR

FUNCTION OPEN GROUND VDD 9V ± -0.5V

Static Burn-In 1

10 -13 1 - 9, 14, 15 16

50kHz 25kHz

Note 1
Static Burn-In 2

10 -13 8 1 - 7, 9, 14 - 16

Note 1
Dynamic Burn-

- 8 16 10 - 13 - 1 - 7, 9, 14, 15

In Note 1
Irradiation

10 -13 8 1 - 7, 9, 14 - 16

Note 2

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

Logic Diagram

VDD

VSS

*INPUTS PROTECTED

BY CMOS PROTECTION
NETWORK

*Ka

*Kb

*A4

*B4

*A3
*B3
*A2
*B2
*A1
*B1

9

14

VDD = 16
VSS - 8

TRUTH TABLE

Ka Kb An Bn Dn

15

13

D4

1

101X1
100X0
01X11
01X00

2
3
4
5
6

TO 3 MORE
SIMILAR
CIRCUITS

12

D3

11

D2

10

D1

00XX0
11000
11011
11101
11111

X = Don’t Care Case

7

FIGURE 1. CD4019BMS LOGIC DIAGRAM

7-311

Typical Performance Characteritics

CD4019BMS

AMBIENT TEMPERATURE (TA) = +25oC

30

25

20

15

10

5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

AMBIENT TEMPERATURE (TA) = +25oC

15.0

12.5

10.0

7.5

5.0

2.5

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

0 5 10 15

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

10V

5V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

0-5-10-15

0

-5

-10

-15

-20

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10V

0-5-10-15

0

-5

-10

-25

-15V

-30

FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

200

150

100

50

TRANSITION TIME (tTHL, tTLH) (ns)

0

0 40 60 80 10020

SUPPLY VOLTAGE (VDD) = 5V

10V
15V

LOAD CAPACITANCE (CL) (pF)

-15V

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

250

200

150

100

50

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

0

0 40 60 80 10020

LOAD CAPACITANCE (CL) (pF)

SUPPLY VOLTAGE (VDD) = 5V

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

10V

15V

FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACITANCE

FIGURE 7. PROPAGATION DELAY TIME AS A FUNCTION OF

LOAD CAPACITANCE

7-312

CD4019BMS

Typical Performance Characteritics (Continued)

5

10

8

AMBIENT TEMPERATURE (TA) = +25oC

6
4

2

SUPPLY VOLTAGE

4

10

10

10

POWER DISSIPATION (PD) (µW)

10

(VDD) = 15V

8
6

4
2

3

8
6

4
2

2

8
6

4
2

2468 2468 2468 24682468

11010

INPUT FREQUENCY (fIN) (kHz)

2

FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A

FUNCTION OF INPUT FREQUENCY

Typical Applications

5V

10

10V

10V

CL = 50pF
CL = 15pF

3

4

10

5

10

“B” REGISTER “A” REGISTER

Q1

1
0

CD413B OR EQUIV

(Ka)

SELECT

“A” REGISTER

Q2

1
0

OUT 1 OUT 2 OUT 3 OUT 4

Q1

1
0

CD413B OR EQUIV

CD4019B

Q2

1
0

CD4013B

OR EQUIV.

CD4013B

OR EQUIV.

(Kb)
SELECT
“B” REGISTER

FIGURE 9. AND/OR SELECT GATING

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]

313

Typical Applications (Continued)

CD4019BMS

SHIFT
RIGHT

INPUT

(Ka)
SHIFT

LEFT
SELECT

CLOCK

SHIFT
LEFT
OUTPUT

CD4019B

CL

Q1D1

CL CL CL CL

1
0

CD4013B

OR EQUIV. CD4013B OR EQUIV.

Q2D2

1
0

FIGURE 10. “SHIFT LEFT/SHIFT RIGHT” REGISTER

SHIFT
LEFT INPUT

(Kb)
SHIFT

RIGHT
SELECT

Q1D1

1
0

Q2D2

1
0

SHIFT
RIGHT
OUTPUT

(Ka)
TRUE
SELECT

Q1

1
0

Q1 Q2 Q1 Q2

CD4013B

OUT 1 OUT 2 OUT 3 OUT 4

Q2

1
0

OR EQUIV. CD4013B OR EQUIV.

CD4019B

Q1

1
0

FIGURE 11. “TRUE COMPLEMENT” SELECTOR

Q2

1
0

(Kb)
COMPLEMENT
SELECT

7-314

Typical Applications (Continued)

A1 B1 A2 B2 A3 B3 A4 B4

CD4019BMS

K (•)

CD4001B

OR EQUIV

CD4001B OR EQUIV

CD4001B OR EQUIV

A1 ⊕ B1 A1 • B1 A2 ⊕ B2 A2 • B2 A3 ⊕ B3 A3 • B3 A4 ⊕ B4 A4 • B4

CD4019B

OUT1 OUT2 OUT3 OUT4

CD4001B

OR EQUIV

CD4001B

OR EQUIV

FIGURE 12. AND/OR EXCLUSIVE-OR SELECTOR

TRUTH TABLE

K ( • ) K ( ⊕ ) OUT

00 0
10A• B
01A⊕ B
1 1 A + B

K (⊕)

Chip Dimensions and Pad Layout

7-315

METALLIZATION: Thickness: 11kÅ− 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10

-3

inch)