Page 1
October 1987
Revised January 1999
CD40192BC • CD40193BC Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary
Counter
© 1999 Fairchild Semiconductor Corporation DS005988.prf www.fairchildsemi.com
CD40192BC • CD40193BC
Synchronous 4-Bit Up/Down Decade Counter •
Synchronous 4-Bit Up/Down Binary Counter
General Description
The CD40192BC and C D40193BC up/down counte rs are
monolithic complementary MOS (CMOS) integrated circuits. The CD40192BC is a BCD counter, while the
CD40193BC is a binary counter.
Counting up and countin g down i s perfor med by two cou nt
inputs, one being held HIGH while the other is clocked. The
outputs change on the positive-going transition of this
clock.
These counters feature preset inputs that are enabled
when load is a logical “0” an d a clear which forces all ou tputs to “0” when it is a t logica l “1 ”. Th e coun ters a lso have
carry and borrow outputs so that they can be cascaded
using no external circuitry.
All inputs are protected a gainst damage due to static discharge by clamps to V
DD
and VSS.
Features
■ Wide supply voltage range: 3V to 15V
■ High noise immunity: 0.45 V
DD
(typ.)
■ Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
■ Carry and bor row ou tpu ts for ea sy expansi o n to N- bit by
cascading
■ Asynchronous clear
■ Equivalent to: MM74C192 and MM74C193
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
Cascading Packa ges
Order Number Package Number Package Description
CD40192BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD40193BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD40193BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Page 2
www.fairchildsemi.com 2
CD40192BC • CD40193BC
Block Diagrams
CD40192BC Synchronous 4-Bit Up/Down Decade Counter
CD40193BC Synchronous 4-Bit Up/Down Binary Counter
Page 3
3 www.fairchildsemi.com
CD40192BC • CD40193BC
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
(Note 2)
Note 1: “Absolute Maximum Rat ings” are tho se values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be ope rated at these limits. The “Re commended
Operating Cond itions” and E lectrical C haracteris tics tables pr ovide conditions for actual device operatio n.
Note 2: V
SS
= 0V unless otherw is e s pecified.
DC Electrical Characteristics (Note 3)
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: I
OH
and IOL are tested one output at a ti m e.
DC Supply Voltage (VDD) −0.5 to +18 V
DC
Input Voltage (VIN) −0.5toVDD+0.5 V
DC
Storage Temperature Range (TS)
−65°C to +150°C
Power Dissipat ion (P
D
)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (T
L
)
(Soldering , 10 seconds) 260°C
DC Supply Voltage (V
DD
) 3 to 15 V
DC
Input Voltage (VIN) 0 to VDD V
DC
Operating Temperature Range (TA)
CD40192BC, CD40193BC −40°C to +85°C
Symbol Parameter Conditions
−40°C +25°C +85°C
Units
Min Max Min Typ Max Min Max
I
DD
Quiescent Device VDD = 5V, VIN = VDDor V
SS
20 20 150 µA
Current VDD = 10V, VIN = V
DD
or V
SS
40 40 300 µA
VDD = 15V, VIN = VDD or V
SS
80 80 600 µA
V
OL
LOW Level VDD = 5V 0.05 0.05 0.05 V
Output Voltage VDD = 10V 0.05 0.05 0.05 V
VDD = 15V 0.05 0.05 0.05 V
V
OH
HIGH Level VDD = 5V 4.95 4.95 4.95 V
Output Voltage VDD = 10V 9.95 9.95 9.95 V
VDD = 15V 14.95 14.95 14.95 V
V
IL
LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 V
Input Voltage VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 V
V
IH
HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 V
Input Voltage VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 V
I
OL
LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
Current (Note 4) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA
VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
I
OH
HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
Current (Note 4) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA
VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA
I
IN
Input Current VDD = 15V, VIN = 0V −0.3 −10−5 −0.3 −1.0 µA
VDD = 15V, V
IN
= 15V 0.3 10
−5
0.3 1.0 µA
Page 4
www.fairchildsemi.com 4
CD40192BC • CD40193BC
AC Electrical Charac teristics (Note 3)
TA = 25°C, CL = 50 pF, RL = 200 kΩ, input tr = tf = 20 ns, unless otherwise specified.
Note 5: CPD determines th e no load AC power con sumption o f any CMOS device. For comp lete explanatio n, see Family Character istics ap plication n ote,
AN-90.
Symbol Parameter Conditions Min Typ Max Units
t
PHL
or t
PLH
Propagation Delay Time VDD = 5V 250 400 ns
from Count Up or VDD = 10V 100 160 ns
Count Down to Q VDD = 15V 80 130 ns
t
PHL
or t
PLH
Propagation Delay Time VDD = 5V 120 200 ns
from Count Up to Carry VDD = 10V 50 80 ns
VDD = 15V 40 65 ns
t
PHL
or t
PLH
Propagation Delay Time VDD = 5V 120 200 ns
from Count Down VDD = 10V 50 80 ns
to Borrow VDD = 15V 40 65 ns
t
SU
Time Prior to Load VDD = 5V 100 160 ns
That Data Must VDD = 10V 30 50 ns
Be Present VDD = 15V 25 40 ns
t
PHL
Propagation Delay Time VDD = 5V 130 220 ns
from Clear to Q VDD = 10V 60 100 ns
VDD = 15V 50 80 ns
t
PLH
or t
PHL
Propagation Delay Time VDD = 5V 300 480 ns
from Load to Q VDD = 10V 120 190 ns
VDD = 15V 95 150 ns
t
TLH
or t
THL
Output Transition Time VDD = 5V 100 200 ns
VDD = 10V 50 100 ns
VDD = 15V 40 80 ns
f
CL
Maximum Count Frequency VDD = 5V 2.5 4 MHz
VDD = 10V 6 10 MHz
VDD = 15V 7.5 12.5 MHz
t
rCL
or t
fCL
Maximum Count Rise VDD = 5V 15 µs
or Fall Time VDD = 10V 5 µs
VDD = 15V 1 µs
tWH, t
WL
Minimum Count Pulse VDD = 5V 120 200 ns
Width VDD = 10V 35 80 ns
VDD = 15V 28 65 ns
t
WH
Minimum Clear VDD = 5V 300 480 ns
Pulse Width VDD = 10V 120 190 ns
VDD = 15V 95 150 ns
t
WL
Minimum Load VDD = 5V 100 160 ns
Pulse Width VDD = 10V 40 65 ns
VDD = 15V 32 55 ns
C
IN
Average Input Capacitance Load and Data 5 7.5 pF
Inputs (A,B,C,D)
Count Up, Count 10 15 pF
Down and Clear
C
PD
Power Dissipation Capacity (Note 5) 100 pF
Page 5
5 www.fairchildsemi.com
CD40192BC • CD40193BC
Timing Diagrams
CD40192BC
Sequence:
1. Clear outputs to zero.
2. Load (preset) to BCD s even.
3. Count up to eight, nin e, carry, zero, one and two.
4. Count down to one, zero, borrow, nine, eight and seven.
CD40193BC
Sequence:
1. Clear outputs to zero.
2. Load (preset) to bina ry thirteen .
3. Count up to fourteen, fifteen, carry, zero, one and two.
4. Count down to one, zero, borrow, fifteen, fourt een and thirteen.
Page 6
www.fairchildsemi.com 6
CD40192BC • CD40193BC
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A
Page 7
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are i mplied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
CD40192BC • CD40193BC Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Do w n Binary
Counter
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injur y to the
user.
2. A critical compon ent in any com ponent of a li fe support
device or system whose failure to p erform can be r easonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
Loading...