Datasheet CD4013BCSJX, CD4013BCSJ, CD4013BCN, CD4011BCSJX, CD4013BCMX Datasheet (Fairchild Semiconductor)

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October 1987 Revised January 1999

CD4013BC Dual D-Type Flip-Flop

General Description

The CD4013B dual D- type flip-flo p is a monol ithic comp lementary MOS (CMOS ) integrated circuit constructed w ith N- and P-channel enhancement mode transistors. Each flip-flop has indepen dent data, set, re set, and clo ck inputs

and “Q” and “Q

” outputs. These devices can be use d for

shift register application s, and by connecting “Q

” output to the data input, for counter and toggle applications. The logic level present at the “D” input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is indepen dent of the clock and is accomplished by a high level on the set or reset line respectively.

Features

■ Wide supply voltage range: 3.0V to 15V

■ High noise immunity: 0.45 V

(typ.)

■ Low power TTL: fan out of 2 driving 74L compatibility: or 1 driving 74LS

Applications

• Automotive

• Data terminals

• Instrumentation

• Medical electronics

• Alarm system

• Industrial electronics

• Remote metering

• Computers

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP, SOIC and SOP

Top View

Truth Table

No Change x = Don't Care Case

Note 1: Level Change

Order Number Package Number Package Description

CD4013BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow CD4013BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4013BCN N14A 14-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

(Note 1)

DRSQQ



00001



10010



x00QQ x x1001 x x0110 x x1111

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CD4013BC

Schematic Diagrams

Logic Diagram

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CD4013BC

Absolute Maximum Ratings(Note 2)

(Note 3)

Recommended Operating Conditions

(Note 3)

Note 2: “Absolute Maximum Rat ings” are tho se values beyond which the safety of the device cannot be guaranteed, they are not meant to imply that the devices should be o perated at these limits. The tables of “R ecommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operat ion.

Note 3: V

= 0V unless otherw is e s pecified.

DC Electrical Characteristics (Note 3)

Note 4: IOH and IOL are measured on e output at a time .

DC Supply Voltage (VDD) −0.5 VDC to +18 V

Input Voltage (VIN) −0.5 VDC to VDD +0.5 V

Storage Temperature Range (TS) −65°C to +150°C Power Dissipation (P

) Dual-In-Line 700 mW Small Outline 500 mW

Lead Temperature (T

) (Soldering, 10 seconds) 260°C

DC Supply Voltage (V

) +3 VDC to +15 V

Input Voltage (VIN)0 V

to VDD V

Operating Temperature Range (TA) −40°C to +85°C

Symbol Parameter Conditions

−40°C +25°C +85°C

Units

Min Max Min Typ Max Min Max

Quiescent Device VDD = 5V, VIN = VDD or V

4.0 4.0 30 µA

Current VDD = 10V, VIN = VDD or V

8.0 8.0 60 µA

VDD = 15V, VIN = VDD or V

16.0 16.0 120 µA

LOW Level |IO| < 1.0 µA Output Voltage VDD = 5V 0.05 0.05 0.05 V

VDD = 10V 0.05 0.05 0.05 V VDD = 15V 0.05 0.05 0.05 V

HIGH Level |IO| < 1.0 µA Output Voltage VDD = 5V 4.95 4.95 4.95 V

VDD = 10V 9.95 9.95 9.95 V VDD = 15V 14.95 14.95 14.95 V

LOW Level |IO| < 1.0 µA Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5 V

VDD = 10V, VO = 1.0V or 9.0V 3.0 3.0 3.0 V VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 V

HIGH Level |IO| < 1.0 µA Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 V

VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 7.0 V VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 V

LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA Current (Note 4) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA

VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA

HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA Current (Note 4) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA

VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA

Input Current VDD = 15V, VIN = 0V −0.3 −10−5−0.3 −1.0 µA

VDD = 15V, VIN = 15V 0.3 10−50.3 1.0 µA

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CD4013BC

AC Electrical Charac teristics (Note 5)

TA = 25°C, CL = 50 pF, RL = 200k, unless otherwise noted

Note 5: AC Parameters are guara nt eed by DC correlated testin g.

Switching Time Waveforms

Symbol Parameter Conditions Min Typ Max Units

CLOCK OPERATION

PHL

, t

PLH

Propagation Delay Time VDD = 5V 200 350 ns

VDD = 10V 80 160 ns VDD = 15V 65 120 ns

THL

, t

TLH

Transition Time VDD = 5V 100 200 ns

VDD = 10V 50 100 ns VDD = 15V 40 80 ns

tWL, t

Minimum Clock VDD = 5V 100 200 ns Pulse Width VDD = 10V 40 80 ns

VDD = 15V 32 65 ns

RCL

, t

FCL

Maximum Clock Rise and VDD = 5V 15 µs Fall Time VDD = 10V 10 µs

VDD = 15V 5 µs

Minimum Set-Up Time VDD = 5V 20 40 ns

VDD = 10V 15 30 ns VDD = 15V 12 25 ns

Maximum Clock VDD = 5V 2.5 5 MHz Frequency VDD = 10V 6.2 12.5 MHz

VDD = 15V 7.6 15.5 MHz

SET AND RESET OPERATION

PHL(R)

, Propagation Delay Time VDD = 5V 150 300 ns

PLH(S)

VDD = 10V 65 130 ns VDD = 15V 45 90 ns

WH(R)

, Minimum Set and VDD = 5V 90 180 ns

WH(S)

Reset Pulse Width VDD = 10V 40 80 ns

VDD = 15V 25 50 ns

Average Input Capacitance Any Input 5 7.5 pF

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CD4013BC

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

Package Number M14A

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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Fairchild does not assume any responsibility for use of any circuitry descri bed, no circuit patent licenses are implied and Fairchil d reser ves the right at any time without notice to change said circuitr y and specifications.

CD4013BC Dual D-Type Flip-Flop

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t devices or sys tem s ar e devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical co mpone nt in a ny compon ent of a life suppo r t device or system whose failure to perform can be reasonably expected to cause the failure of the life suppor t device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N14A