• Schmitt Trigger Action with No External Components
• Hysteresis Voltage (Typ.)
- 0.9V at VDD = 5V
- 2.3V at VDD = 10V
- 3.5V at VDD = 15V
• Noise Immunity Greater than 50%
• No Limit on Input Rise and Fall Times
• Low VDD to VSS Current During Slow Input Ramp
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
CMOS Hex Schmitt Triggers
Pinout
CD40106BMS
TOP VIEW
A
1
A
2
G =
3
B
B
4
H =
5
C
C
6
I =
VSS
7
o
C
Functional Diagram
1
A
3
B
2
G =
4
H =
VDD
14
F
13
F
12
L =
11
E
E
10
K =
D
9
J =
D
8
A
B
Applications
• Wave and Pulse Shapers
• High Noise Environment Systems
• Monostable Multivibrators
• Astable Multivibrators
Description
CD40106BMS consists of six Schmitt trigger circuits. Each
circuit functions as an inverter with Schmitt trigger action on
the input. The trigger switches at different points for positive
and negative going signals. The difference between the
positive going voltage (VP) and the negative going voltage
(VN) is defined as hysteresis voltage (VH) (see Figure 17).
The CD40106BMS is supplied in these 14 lead outline
packages:
Braze Seal DIPH4Q
Frit Seal DIPH1B
Ceramic FlatpackH3W
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on
initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K., Input TR, TF < 20ns
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETERSYMBOLCONDITIONSNOTESTEMPERATURE
Supply CurrentIDDVDD = 20V, VIN = VDD or GND1, 4+25oC-7.5µA
N Threshold VoltageVNTHVDD = 10V, ISS = -10µA1, 4+25oC-2.8-0.2V
N Threshold Voltage
Delta
P Threshold VoltageVTPVSS = 0V, IDD = 10µA1, 4+25oC0.22.8V
P Threshold Voltage
Delta
FunctionalFVDD = 18V, VIN = VDD or GND1+25oCVOH >
Propagation Delay TimeTPHL
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
∆VTNVDD = 10V, ISS = -10µA1, 4+25oC-±1V
∆VTPVSS = 0V, IDD = 10µA1, 4+25oC-±1V
VOL <
TPLH
VDD = 3V, VIN = VDD or GND
VDD = 5V1, 2, 3, 4+25oC-1.35 x
3. See Table 2 for +25oC limit.
4. Read and Record
VDD/2
VDD/2
+25oC
Limit
UNITSMINMAX
UNITSMINMAX
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETERSYMBOLDELTA LIMIT
Supply Current - MSI-1IDD± 0.2µA
Output Current (Sink)IOL5± 20% x Pre-Test Reading
Output Current (Source)IOH5A± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
PDA (Note 1)100% 50041, 7, 9, Deltas
Interim Test 3 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
FIGURE 17. HYSTERESIS DEFINITION, CHARACTERISTICS, AND TEST SETUP
OUTPUT
CHARACTERISTIC
LOGIC “1”
OUTPUT
REGION
LOGIC “0”
OUTPUT
REGION
VOL
VP
VN
VSS
VDD
VH
INPUT
CHARACTERISTIC
LOGIC “0”
INPUT
REGION
VO
LOGIC “1”
INPUT
REGION
VH
VN
(b) TRANSFER CHARACTERISTIC OF 1 OF 6 GATES
VH = VP - VN
VIN
VP
VOH
VOL
DRIVERLOAD
VIN
VO
FIGURE 18. INPUT AND OUTPUT CHARACTERISTICS
7-1334
Page 9
Chip Dimensions and Pad Layout
CD40106BMS
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10
-3
inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
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Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
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ASIA
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Taiwan Limited
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Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
1335
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