• 4 Sum Outputs Plus Parallel Look-ahead Carry-Output
• High-Speed Operation - Sum In-To-Sum Out, 160ns
Typ; Carry In-To-Carry Out, 5ns Typ. At VDD = 10V,
CL=50pF
• Standardized Symmetrical Output Characteristics
• 100% Tested For Quiescent Current At 20V
• Maximum Input Current of 1µa at 18V Over Full Package-Temperature Range;
- 100nA at 18V and 25oC
• Noise Margin (Over Full Package T emperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Binary Addition/Arithmetic Units
Description
CD4008BMS types consist of four full adder stages with fast
look ahead carry provision from stage to stage. Circuitry is
included to provide a fast “parallel-carry-out” but to permit
high-speed operation in arithmetic sections using several
CD4008BMS’s.
CD4008BMS inputs include the four sets of bits to be added,
A1 to A4 and B1 to B4, in addition to the “Carry In” bit from a
previous section. CD4008BMS outputs include the four sum
bits, S1 to S4. In addition to the high speed “parallel-carryout” which may be utilized at a succeeding CD4008BMS
section.
The CD4008BMS is supplied in these 16-lead outline packages:
Braze Seal DIPH4T
Frit Seal DIPH1F
Ceramic Flatpack H6W
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
UNITSMINMAX
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETERSYMBOLCONDITIONSNOTESTEMPERATURE
UNITSMINMAX
Supply CurrentIDDVDD = 20V, VIN = VDD or GND1, 4+25oC-25µA
N Threshold VoltageVNTHVDD = 10V, ISS = -10µA1, 4+25oC-2.8-0.2V
N Threshold Voltage
∆VNTHVDD = 10V, ISS = -10µA1, 4+25oC-±1V
Delta
P Threshold VoltageVPTHVSS = 0V, IDD = 10µA1, 4+25oC0.22.8V
P Threshold Voltage
∆VPTHVSS = 0V, IDD = 10µA1, 4+25oC-±1V
Delta
FunctionalFVDD = 18V, VIN = VDD or GND1+25oCVOH >
VDD = 3V, VIN = VDD or GND
VDD/2
VOL <
VDD/2
V
7-678
Page 5
Specifications CD4008BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETERSYMBOLCONDITIONSNOTESTEMPERATURE
Propagation Delay TimeTPHL
TPLH
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
Supply Current - MSI-2IDD± 1.0µA
Output Current (Sink)IOL5± 20% x Pre-Test Reading
Output Current (Source)IOH5A± 20% x Pre-Test Reading
CONFORMANCE GROUP
Initial Test (Pre Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
PDA (Note 1)100% 50041, 7, 9, Deltas
Interim Test 3 (Post Burn-In)100% 50041, 7, 9IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
VDD = 5V1, 2, 3, 4+25oC-1.35 x
+25oC
Limit
3. See Table 2 for +25oC limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETERSYMBOLDELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHODGROUP A SUBGROUPSREAD AND RECORD
UNITSMINMAX
ns
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
CONFORMANCE GROUPS
Group E Subgroup 250051, 7, 9Table 41, 9Table 4
FUNCTIONOPENGROUNDVDD9V ± -0.5V
Static Burn-In 1
Note 1
Static Burn-In 2
Note 1
Dynamic BurnIn Note 1
Irradiation
Note 2
10 - 141 - 9, 1516
10 - 1481 - 7, 9, 15, 16
-81610 - 142, 4, 6, 151, 3, 5, 7, 9
10 - 1481 - 7, 9, 15, 16
METHOD
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
PRE-IRRADPOST-IRRADPRE-IRRADPOST-IRRAD
TESTREAD AND RECORD
OSCILLATOR
50kHz25kHz
7-679
Page 6
Specifications CD4008BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTIONOPENGROUNDVDD9V ± -0.5V
50kHz25kHz
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
Typical Propagation Delay
CO
A13 - 16
B13 - 16
A9 - 12
B9 - 12
CD4008
CD4008
Ci
CO
Ci
CO
S13 - 16
S9 - 12
50 + 50 + 90 + 155
50 + 90 + 155
2(50)+ 90+ 155
2(Ci - CO) + (Si - CO) + (Ci - SO) = 345
5090155
(Ci - CO) + (Si - CO) + (Ci - SO)
A5 - 8
A5 - 8
A1 - 4
B1 - 4
CD4008
CO
CD4008
VSS
S5 - 8
Ci
S1 - 4
Ci
90 + 155(Si - CO) + (Ci - SO) =90 + 155
160(Si - SO)
ALL SUMS SETTLED AFTER 345ns
FIGURE 1. PROPAGATION DELAY FOR A 16 BIT ADDER (10V OPERATION)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
680
Page 7
Typical Performance Characteristics
CD4008BMS
AMBIENT TEMPERATURE (TA) = +25oC
500
SUPPLY VOLTAGE (VDD) = 5V
400
300
(tPHL, tPLH) (ns)
200
100
SUM-IN TO SUM-OUT PROPAGATION DELAY TIME
020406080100120140
LOAD CAPACITANCE (CL) (pF)
10V
15V
FIGURE 2. TYPICAL SUM-IN TO SUM-OUT PROPAGATION
DELAY TIME vs LOAD CAPACITANCE
AMBIENT TEMPERATURE (TA) = +25oC
600
500
SUPPLY VOLTAGE (VDD) = 5V
400
AMBIENT TEMPERATURE (TA) = +25oC
150
SUPPLY VOLTAGE (VDD) = 5V
125
100
75
50
DELAY TIME (tPHL, tPLH) (ns)
25
CARRY-IN TO CARRY-OUT PROPAGATION
020406080100120140
LOAD CAPACITANCE (CL) (pF)
10V
15V
FIGURE 3. TYPICAL CARRY-IN TO CARRY-OUT PROPAGA-
TION DELAY TIME vs LOAD CAPACITANCE
AMBIENT TEMPERATURE (TA) = +25oC
300
SUPPLY VOLTAGE (VDD) = 5V
250
200
300
200
DELAY TIME (tPHL, tPLH) (ns)
100
CARRY-IN TO CARRY-OUT PROPAGATION
020406080100120140
LOAD CAPACITANCE (CL) (pF)
10V
15V
FIGURE 4. TYPICAL CARRY-IN TO SUM-OUT PROPAGATION
DELAY TIME vs LOAD CAPACITANCE
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
0-5-10-15
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10V
-15V
0
-5
-10
-15
-20
-25
-30
150
100
DELAY TIME (tPHL, tPLH) (ns)
50
SUM-IN TO CARRY-OUT PROPAGATION
020406080100120140
LOAD CAPACITANCE (CL) (pF)
10V
15V
FIGURE 5. TYPICAL SUM-IN TO CARRY-OUT PROPAGATION
DELAY TIME vs LOAD CAPACITANCE
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
0-5-10-15
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10V
-15V
0
-5
-10
-15
FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
7-681
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
Page 8
CD4008BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (TA) = +25oC
30
25
20
15
10
5
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
051015
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
10V
5V
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 8. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
6
10
AMBIENT TEMPERATURE (TA) = +25oC
5
POWER DISSIPATION/PACKAGE (PD) (µW)
10
4
10
3
10
2
10
10
SUPPLY VOLTAGE (VDD) = 15V
110
FIGURE 10. TYPICAL DISSIPATION CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
15.0
12.5
10.0
7.5
5.0
2.5
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
051015
FIGURE 9. MINIMUM OUTPUT LOW (SINK) CURRENT
10V
5V
3.5V
LOAD CAPACITANCE (CL) = 15pF
10
INPUT FREQUENCY (fφ) (kHz)
(CL) = 50pF
2
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
10V
5V
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
CHARACTERISTICS
5V
3
10
4
10
Chip Dimensions and Pad Layouts
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10
-3
inch)
METALLIZATION: Thickness: 11kÅ− 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-682
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